1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/MIRYamlMapping.h"
20 #include "llvm/IR/BasicBlock.h"
21 #include "llvm/IR/Module.h"
22 #include "llvm/Support/MemoryBuffer.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Support/YAMLTraits.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetSubtargetInfo.h"
32 /// This class prints out the machine functions using the MIR serialization
36 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
39 MIRPrinter(raw_ostream &OS) : OS(OS) {}
41 void print(const MachineFunction &MF);
43 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo);
44 void convert(const Module &M, yaml::MachineBasicBlock &YamlMBB,
45 const MachineBasicBlock &MBB);
48 void initRegisterMaskIds(const MachineFunction &MF);
51 /// This class prints out the machine instructions using the MIR serialization
56 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
59 MIPrinter(const Module &M, raw_ostream &OS,
60 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds)
61 : M(M), OS(OS), RegisterMaskIds(RegisterMaskIds) {}
63 void print(const MachineInstr &MI);
64 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
67 } // end anonymous namespace
72 /// This struct serializes the LLVM IR module.
73 template <> struct BlockScalarTraits<Module> {
74 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
75 Mod.print(OS, nullptr);
77 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
78 llvm_unreachable("LLVM Module is supposed to be parsed separately");
83 } // end namespace yaml
84 } // end namespace llvm
86 void MIRPrinter::print(const MachineFunction &MF) {
87 initRegisterMaskIds(MF);
89 yaml::MachineFunction YamlMF;
90 YamlMF.Name = MF.getName();
91 YamlMF.Alignment = MF.getAlignment();
92 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
93 YamlMF.HasInlineAsm = MF.hasInlineAsm();
94 convert(YamlMF, MF.getRegInfo());
97 const auto &M = *MF.getFunction()->getParent();
98 for (const auto &MBB : MF) {
99 // TODO: Allow printing of non sequentially numbered MBBs.
100 // This is currently needed as the basic block references get their index
101 // from MBB.getNumber(), thus it should be sequential so that the parser can
102 // map back to the correct MBBs when parsing the output.
103 assert(MBB.getNumber() == I++ &&
104 "Can't print MBBs that aren't sequentially numbered");
106 yaml::MachineBasicBlock YamlMBB;
107 convert(M, YamlMBB, MBB);
108 YamlMF.BasicBlocks.push_back(YamlMBB);
110 yaml::Output Out(OS);
114 void MIRPrinter::convert(yaml::MachineFunction &MF,
115 const MachineRegisterInfo &RegInfo) {
116 MF.IsSSA = RegInfo.isSSA();
117 MF.TracksRegLiveness = RegInfo.tracksLiveness();
118 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
121 void MIRPrinter::convert(const Module &M, yaml::MachineBasicBlock &YamlMBB,
122 const MachineBasicBlock &MBB) {
123 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
124 YamlMBB.ID = (unsigned)MBB.getNumber();
125 // TODO: Serialize unnamed BB references.
126 if (const auto *BB = MBB.getBasicBlock())
127 YamlMBB.Name = BB->hasName() ? BB->getName() : "<unnamed bb>";
130 YamlMBB.Alignment = MBB.getAlignment();
131 YamlMBB.AddressTaken = MBB.hasAddressTaken();
132 YamlMBB.IsLandingPad = MBB.isLandingPad();
134 // Print the machine instructions.
135 YamlMBB.Instructions.reserve(MBB.size());
137 for (const auto &MI : MBB) {
138 raw_string_ostream StrOS(Str);
139 MIPrinter(M, StrOS, RegisterMaskIds).print(MI);
140 YamlMBB.Instructions.push_back(StrOS.str());
145 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
146 const auto *TRI = MF.getSubtarget().getRegisterInfo();
148 for (const uint32_t *Mask : TRI->getRegMasks())
149 RegisterMaskIds.insert(std::make_pair(Mask, I++));
152 void MIPrinter::print(const MachineInstr &MI) {
153 const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
154 const auto *TRI = SubTarget.getRegisterInfo();
155 assert(TRI && "Expected target register info");
156 const auto *TII = SubTarget.getInstrInfo();
157 assert(TII && "Expected target instruction info");
159 unsigned I = 0, E = MI.getNumOperands();
160 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
161 !MI.getOperand(I).isImplicit();
165 print(MI.getOperand(I), TRI);
170 OS << TII->getName(MI.getOpcode());
171 // TODO: Print the instruction flags, machine mem operands.
175 bool NeedComma = false;
179 print(MI.getOperand(I), TRI);
184 static void printReg(unsigned Reg, raw_ostream &OS,
185 const TargetRegisterInfo *TRI) {
186 // TODO: Print Stack Slots.
187 // TODO: Print virtual registers.
190 else if (Reg < TRI->getNumRegs())
191 OS << '%' << StringRef(TRI->getName(Reg)).lower();
193 llvm_unreachable("Can't print this kind of register yet");
196 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
197 switch (Op.getType()) {
198 case MachineOperand::MO_Register:
199 // TODO: Print register flags.
200 printReg(Op.getReg(), OS, TRI);
201 // TODO: Print sub register.
203 case MachineOperand::MO_Immediate:
206 case MachineOperand::MO_MachineBasicBlock:
207 OS << "%bb." << Op.getMBB()->getNumber();
208 if (const auto *BB = Op.getMBB()->getBasicBlock()) {
210 OS << '.' << BB->getName();
213 case MachineOperand::MO_GlobalAddress:
214 // FIXME: Make this faster - print as operand will create a slot tracker to
215 // print unnamed values for the whole module every time it's called, which
217 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, &M);
218 // TODO: Print offset and target flags.
220 case MachineOperand::MO_RegisterMask: {
221 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
222 if (RegMaskInfo != RegisterMaskIds.end())
223 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
225 llvm_unreachable("Can't print this machine register mask yet.");
229 // TODO: Print the other machine operands.
230 llvm_unreachable("Can't print this machine operand at the moment");
234 void llvm::printMIR(raw_ostream &OS, const Module &M) {
235 yaml::Output Out(OS);
236 Out << const_cast<Module &>(M);
239 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
240 MIRPrinter Printer(OS);