1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/MIRYamlMapping.h"
20 #include "llvm/IR/BasicBlock.h"
21 #include "llvm/IR/Module.h"
22 #include "llvm/IR/ModuleSlotTracker.h"
23 #include "llvm/Support/MemoryBuffer.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Support/YAMLTraits.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetSubtargetInfo.h"
33 /// This class prints out the machine functions using the MIR serialization
37 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
40 MIRPrinter(raw_ostream &OS) : OS(OS) {}
42 void print(const MachineFunction &MF);
44 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo);
45 void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
46 const MachineBasicBlock &MBB);
49 void initRegisterMaskIds(const MachineFunction &MF);
52 /// This class prints out the machine instructions using the MIR serialization
56 ModuleSlotTracker &MST;
57 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
60 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
61 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds)
62 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds) {}
64 void print(const MachineInstr &MI);
65 void printMBBReference(const MachineBasicBlock &MBB);
66 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
69 } // end anonymous namespace
74 /// This struct serializes the LLVM IR module.
75 template <> struct BlockScalarTraits<Module> {
76 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
77 Mod.print(OS, nullptr);
79 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
80 llvm_unreachable("LLVM Module is supposed to be parsed separately");
85 } // end namespace yaml
86 } // end namespace llvm
88 void MIRPrinter::print(const MachineFunction &MF) {
89 initRegisterMaskIds(MF);
91 yaml::MachineFunction YamlMF;
92 YamlMF.Name = MF.getName();
93 YamlMF.Alignment = MF.getAlignment();
94 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
95 YamlMF.HasInlineAsm = MF.hasInlineAsm();
96 convert(YamlMF, MF.getRegInfo());
99 ModuleSlotTracker MST(MF.getFunction()->getParent());
100 for (const auto &MBB : MF) {
101 // TODO: Allow printing of non sequentially numbered MBBs.
102 // This is currently needed as the basic block references get their index
103 // from MBB.getNumber(), thus it should be sequential so that the parser can
104 // map back to the correct MBBs when parsing the output.
105 assert(MBB.getNumber() == I++ &&
106 "Can't print MBBs that aren't sequentially numbered");
108 yaml::MachineBasicBlock YamlMBB;
109 convert(MST, YamlMBB, MBB);
110 YamlMF.BasicBlocks.push_back(YamlMBB);
112 yaml::Output Out(OS);
116 void MIRPrinter::convert(yaml::MachineFunction &MF,
117 const MachineRegisterInfo &RegInfo) {
118 MF.IsSSA = RegInfo.isSSA();
119 MF.TracksRegLiveness = RegInfo.tracksLiveness();
120 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
123 void MIRPrinter::convert(ModuleSlotTracker &MST,
124 yaml::MachineBasicBlock &YamlMBB,
125 const MachineBasicBlock &MBB) {
126 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
127 YamlMBB.ID = (unsigned)MBB.getNumber();
128 // TODO: Serialize unnamed BB references.
129 if (const auto *BB = MBB.getBasicBlock())
130 YamlMBB.Name.Value = BB->hasName() ? BB->getName() : "<unnamed bb>";
132 YamlMBB.Name.Value = "";
133 YamlMBB.Alignment = MBB.getAlignment();
134 YamlMBB.AddressTaken = MBB.hasAddressTaken();
135 YamlMBB.IsLandingPad = MBB.isLandingPad();
136 for (const auto *SuccMBB : MBB.successors()) {
138 raw_string_ostream StrOS(Str);
139 MIPrinter(StrOS, MST, RegisterMaskIds).printMBBReference(*SuccMBB);
140 YamlMBB.Successors.push_back(StrOS.str());
143 // Print the machine instructions.
144 YamlMBB.Instructions.reserve(MBB.size());
146 for (const auto &MI : MBB) {
147 raw_string_ostream StrOS(Str);
148 MIPrinter(StrOS, MST, RegisterMaskIds).print(MI);
149 YamlMBB.Instructions.push_back(StrOS.str());
154 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
155 const auto *TRI = MF.getSubtarget().getRegisterInfo();
157 for (const uint32_t *Mask : TRI->getRegMasks())
158 RegisterMaskIds.insert(std::make_pair(Mask, I++));
161 void MIPrinter::print(const MachineInstr &MI) {
162 const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
163 const auto *TRI = SubTarget.getRegisterInfo();
164 assert(TRI && "Expected target register info");
165 const auto *TII = SubTarget.getInstrInfo();
166 assert(TII && "Expected target instruction info");
168 unsigned I = 0, E = MI.getNumOperands();
169 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
170 !MI.getOperand(I).isImplicit();
174 print(MI.getOperand(I), TRI);
179 OS << TII->getName(MI.getOpcode());
180 // TODO: Print the instruction flags, machine mem operands.
184 bool NeedComma = false;
188 print(MI.getOperand(I), TRI);
193 static void printReg(unsigned Reg, raw_ostream &OS,
194 const TargetRegisterInfo *TRI) {
195 // TODO: Print Stack Slots.
196 // TODO: Print virtual registers.
199 else if (Reg < TRI->getNumRegs())
200 OS << '%' << StringRef(TRI->getName(Reg)).lower();
202 llvm_unreachable("Can't print this kind of register yet");
205 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
206 OS << "%bb." << MBB.getNumber();
207 if (const auto *BB = MBB.getBasicBlock()) {
209 OS << '.' << BB->getName();
213 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
214 switch (Op.getType()) {
215 case MachineOperand::MO_Register:
216 // TODO: Print the other register flags.
218 OS << (Op.isDef() ? "implicit-def " : "implicit ");
223 printReg(Op.getReg(), OS, TRI);
224 // TODO: Print sub register.
226 case MachineOperand::MO_Immediate:
229 case MachineOperand::MO_MachineBasicBlock:
230 printMBBReference(*Op.getMBB());
232 case MachineOperand::MO_GlobalAddress:
233 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
234 // TODO: Print offset and target flags.
236 case MachineOperand::MO_RegisterMask: {
237 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
238 if (RegMaskInfo != RegisterMaskIds.end())
239 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
241 llvm_unreachable("Can't print this machine register mask yet.");
245 // TODO: Print the other machine operands.
246 llvm_unreachable("Can't print this machine operand at the moment");
250 void llvm::printMIR(raw_ostream &OS, const Module &M) {
251 yaml::Output Out(OS);
252 Out << const_cast<Module &>(M);
255 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
256 MIRPrinter Printer(OS);