1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/MIRYamlMapping.h"
21 #include "llvm/IR/BasicBlock.h"
22 #include "llvm/IR/Instructions.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/IR/ModuleSlotTracker.h"
25 #include "llvm/Support/MemoryBuffer.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Support/YAMLTraits.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetSubtargetInfo.h"
35 /// This structure describes how to print out stack object references.
36 struct FrameIndexOperand {
41 FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
42 : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
44 /// Return an ordinary stack object reference.
45 static FrameIndexOperand create(StringRef Name, unsigned ID) {
46 return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
49 /// Return a fixed stack object reference.
50 static FrameIndexOperand createFixed(unsigned ID) {
51 return FrameIndexOperand("", ID, /*IsFixed=*/true);
55 /// This class prints out the machine functions using the MIR serialization
59 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
60 /// Maps from stack object indices to operand indices which will be used when
61 /// printing frame index machine operands.
62 DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
65 MIRPrinter(raw_ostream &OS) : OS(OS) {}
67 void print(const MachineFunction &MF);
69 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
70 const TargetRegisterInfo *TRI);
71 void convert(yaml::MachineFrameInfo &YamlMFI, const MachineFrameInfo &MFI);
72 void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
73 const MachineJumpTableInfo &JTI);
74 void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
75 const MachineBasicBlock &MBB);
76 void convertStackObjects(yaml::MachineFunction &MF,
77 const MachineFrameInfo &MFI);
80 void initRegisterMaskIds(const MachineFunction &MF);
83 /// This class prints out the machine instructions using the MIR serialization
87 ModuleSlotTracker &MST;
88 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
89 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
92 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
93 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
94 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
95 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
96 StackObjectOperandMapping(StackObjectOperandMapping) {}
98 void print(const MachineInstr &MI);
99 void printMBBReference(const MachineBasicBlock &MBB);
100 void printStackObjectReference(int FrameIndex);
101 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
104 } // end anonymous namespace
109 /// This struct serializes the LLVM IR module.
110 template <> struct BlockScalarTraits<Module> {
111 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
112 Mod.print(OS, nullptr);
114 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
115 llvm_unreachable("LLVM Module is supposed to be parsed separately");
120 } // end namespace yaml
121 } // end namespace llvm
123 static void printReg(unsigned Reg, raw_ostream &OS,
124 const TargetRegisterInfo *TRI) {
125 // TODO: Print Stack Slots.
128 else if (TargetRegisterInfo::isVirtualRegister(Reg))
129 OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
130 else if (Reg < TRI->getNumRegs())
131 OS << '%' << StringRef(TRI->getName(Reg)).lower();
133 llvm_unreachable("Can't print this kind of register yet");
136 void MIRPrinter::print(const MachineFunction &MF) {
137 initRegisterMaskIds(MF);
139 yaml::MachineFunction YamlMF;
140 YamlMF.Name = MF.getName();
141 YamlMF.Alignment = MF.getAlignment();
142 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
143 YamlMF.HasInlineAsm = MF.hasInlineAsm();
144 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
145 convert(YamlMF.FrameInfo, *MF.getFrameInfo());
146 convertStackObjects(YamlMF, *MF.getFrameInfo());
148 ModuleSlotTracker MST(MF.getFunction()->getParent());
149 if (const auto *JumpTableInfo = MF.getJumpTableInfo())
150 convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
152 for (const auto &MBB : MF) {
153 // TODO: Allow printing of non sequentially numbered MBBs.
154 // This is currently needed as the basic block references get their index
155 // from MBB.getNumber(), thus it should be sequential so that the parser can
156 // map back to the correct MBBs when parsing the output.
157 assert(MBB.getNumber() == I++ &&
158 "Can't print MBBs that aren't sequentially numbered");
160 yaml::MachineBasicBlock YamlMBB;
161 convert(MST, YamlMBB, MBB);
162 YamlMF.BasicBlocks.push_back(YamlMBB);
164 yaml::Output Out(OS);
168 void MIRPrinter::convert(yaml::MachineFunction &MF,
169 const MachineRegisterInfo &RegInfo,
170 const TargetRegisterInfo *TRI) {
171 MF.IsSSA = RegInfo.isSSA();
172 MF.TracksRegLiveness = RegInfo.tracksLiveness();
173 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
175 // Print the virtual register definitions.
176 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
177 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
178 yaml::VirtualRegisterDefinition VReg;
181 StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
182 MF.VirtualRegisters.push_back(VReg);
186 void MIRPrinter::convert(yaml::MachineFrameInfo &YamlMFI,
187 const MachineFrameInfo &MFI) {
188 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
189 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
190 YamlMFI.HasStackMap = MFI.hasStackMap();
191 YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
192 YamlMFI.StackSize = MFI.getStackSize();
193 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
194 YamlMFI.MaxAlignment = MFI.getMaxAlignment();
195 YamlMFI.AdjustsStack = MFI.adjustsStack();
196 YamlMFI.HasCalls = MFI.hasCalls();
197 YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
198 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
199 YamlMFI.HasVAStart = MFI.hasVAStart();
200 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
203 void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
204 const MachineFrameInfo &MFI) {
205 // Process fixed stack objects.
207 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
208 if (MFI.isDeadObjectIndex(I))
211 yaml::FixedMachineStackObject YamlObject;
213 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
214 ? yaml::FixedMachineStackObject::SpillSlot
215 : yaml::FixedMachineStackObject::DefaultType;
216 YamlObject.Offset = MFI.getObjectOffset(I);
217 YamlObject.Size = MFI.getObjectSize(I);
218 YamlObject.Alignment = MFI.getObjectAlignment(I);
219 YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
220 YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
221 MF.FixedStackObjects.push_back(YamlObject);
222 StackObjectOperandMapping.insert(
223 std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
226 // Process ordinary stack objects.
228 for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
229 if (MFI.isDeadObjectIndex(I))
232 yaml::MachineStackObject YamlObject;
234 if (const auto *Alloca = MFI.getObjectAllocation(I))
235 YamlObject.Name.Value =
236 Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
237 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
238 ? yaml::MachineStackObject::SpillSlot
239 : MFI.isVariableSizedObjectIndex(I)
240 ? yaml::MachineStackObject::VariableSized
241 : yaml::MachineStackObject::DefaultType;
242 YamlObject.Offset = MFI.getObjectOffset(I);
243 YamlObject.Size = MFI.getObjectSize(I);
244 YamlObject.Alignment = MFI.getObjectAlignment(I);
246 MF.StackObjects.push_back(YamlObject);
247 StackObjectOperandMapping.insert(std::make_pair(
248 I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
252 void MIRPrinter::convert(ModuleSlotTracker &MST,
253 yaml::MachineJumpTable &YamlJTI,
254 const MachineJumpTableInfo &JTI) {
255 YamlJTI.Kind = JTI.getEntryKind();
257 for (const auto &Table : JTI.getJumpTables()) {
259 yaml::MachineJumpTable::Entry Entry;
261 for (const auto *MBB : Table.MBBs) {
262 raw_string_ostream StrOS(Str);
263 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
264 .printMBBReference(*MBB);
265 Entry.Blocks.push_back(StrOS.str());
268 YamlJTI.Entries.push_back(Entry);
272 void MIRPrinter::convert(ModuleSlotTracker &MST,
273 yaml::MachineBasicBlock &YamlMBB,
274 const MachineBasicBlock &MBB) {
275 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
276 YamlMBB.ID = (unsigned)MBB.getNumber();
277 // TODO: Serialize unnamed BB references.
278 if (const auto *BB = MBB.getBasicBlock())
279 YamlMBB.Name.Value = BB->hasName() ? BB->getName() : "<unnamed bb>";
281 YamlMBB.Name.Value = "";
282 YamlMBB.Alignment = MBB.getAlignment();
283 YamlMBB.AddressTaken = MBB.hasAddressTaken();
284 YamlMBB.IsLandingPad = MBB.isLandingPad();
285 for (const auto *SuccMBB : MBB.successors()) {
287 raw_string_ostream StrOS(Str);
288 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
289 .printMBBReference(*SuccMBB);
290 YamlMBB.Successors.push_back(StrOS.str());
292 // Print the live in registers.
293 const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
294 assert(TRI && "Expected target register info");
295 for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
297 raw_string_ostream StrOS(Str);
298 printReg(*I, StrOS, TRI);
299 YamlMBB.LiveIns.push_back(StrOS.str());
301 // Print the machine instructions.
302 YamlMBB.Instructions.reserve(MBB.size());
304 for (const auto &MI : MBB) {
305 raw_string_ostream StrOS(Str);
306 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping).print(MI);
307 YamlMBB.Instructions.push_back(StrOS.str());
312 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
313 const auto *TRI = MF.getSubtarget().getRegisterInfo();
315 for (const uint32_t *Mask : TRI->getRegMasks())
316 RegisterMaskIds.insert(std::make_pair(Mask, I++));
319 void MIPrinter::print(const MachineInstr &MI) {
320 const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
321 const auto *TRI = SubTarget.getRegisterInfo();
322 assert(TRI && "Expected target register info");
323 const auto *TII = SubTarget.getInstrInfo();
324 assert(TII && "Expected target instruction info");
326 unsigned I = 0, E = MI.getNumOperands();
327 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
328 !MI.getOperand(I).isImplicit();
332 print(MI.getOperand(I), TRI);
337 if (MI.getFlag(MachineInstr::FrameSetup))
338 OS << "frame-setup ";
339 OS << TII->getName(MI.getOpcode());
340 // TODO: Print the bundling instruction flags, machine mem operands.
344 bool NeedComma = false;
348 print(MI.getOperand(I), TRI);
353 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
354 OS << "%bb." << MBB.getNumber();
355 if (const auto *BB = MBB.getBasicBlock()) {
357 OS << '.' << BB->getName();
361 void MIPrinter::printStackObjectReference(int FrameIndex) {
362 auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
363 assert(ObjectInfo != StackObjectOperandMapping.end() &&
364 "Invalid frame index");
365 const FrameIndexOperand &Operand = ObjectInfo->second;
366 if (Operand.IsFixed) {
367 OS << "%fixed-stack." << Operand.ID;
370 OS << "%stack." << Operand.ID;
371 if (!Operand.Name.empty())
372 OS << '.' << Operand.Name;
375 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
376 switch (Op.getType()) {
377 case MachineOperand::MO_Register:
378 // TODO: Print the other register flags.
380 OS << (Op.isDef() ? "implicit-def " : "implicit ");
387 printReg(Op.getReg(), OS, TRI);
388 // Print the sub register.
389 if (Op.getSubReg() != 0)
390 OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
392 case MachineOperand::MO_Immediate:
395 case MachineOperand::MO_MachineBasicBlock:
396 printMBBReference(*Op.getMBB());
398 case MachineOperand::MO_FrameIndex:
399 printStackObjectReference(Op.getIndex());
401 case MachineOperand::MO_JumpTableIndex:
402 OS << "%jump-table." << Op.getIndex();
403 // TODO: Print target flags.
405 case MachineOperand::MO_GlobalAddress:
406 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
407 // TODO: Print offset and target flags.
409 case MachineOperand::MO_RegisterMask: {
410 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
411 if (RegMaskInfo != RegisterMaskIds.end())
412 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
414 llvm_unreachable("Can't print this machine register mask yet.");
418 // TODO: Print the other machine operands.
419 llvm_unreachable("Can't print this machine operand at the moment");
423 void llvm::printMIR(raw_ostream &OS, const Module &M) {
424 yaml::Output Out(OS);
425 Out << const_cast<Module &>(M);
428 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
429 MIRPrinter Printer(OS);