1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/MIRYamlMapping.h"
24 #include "llvm/IR/BasicBlock.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/Instructions.h"
27 #include "llvm/IR/IRPrintingPasses.h"
28 #include "llvm/IR/Module.h"
29 #include "llvm/IR/ModuleSlotTracker.h"
30 #include "llvm/MC/MCSymbol.h"
31 #include "llvm/Support/MemoryBuffer.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Support/YAMLTraits.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetSubtargetInfo.h"
41 /// This structure describes how to print out stack object references.
42 struct FrameIndexOperand {
47 FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
48 : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
50 /// Return an ordinary stack object reference.
51 static FrameIndexOperand create(StringRef Name, unsigned ID) {
52 return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
55 /// Return a fixed stack object reference.
56 static FrameIndexOperand createFixed(unsigned ID) {
57 return FrameIndexOperand("", ID, /*IsFixed=*/true);
61 } // end anonymous namespace
65 /// This class prints out the machine functions using the MIR serialization
69 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
70 /// Maps from stack object indices to operand indices which will be used when
71 /// printing frame index machine operands.
72 DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
75 MIRPrinter(raw_ostream &OS) : OS(OS) {}
77 void print(const MachineFunction &MF);
79 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
80 const TargetRegisterInfo *TRI);
81 void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
82 const MachineFrameInfo &MFI);
83 void convert(yaml::MachineFunction &MF,
84 const MachineConstantPool &ConstantPool);
85 void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
86 const MachineJumpTableInfo &JTI);
87 void convertStackObjects(yaml::MachineFunction &MF,
88 const MachineFrameInfo &MFI, MachineModuleInfo &MMI,
89 ModuleSlotTracker &MST,
90 const TargetRegisterInfo *TRI);
93 void initRegisterMaskIds(const MachineFunction &MF);
96 /// This class prints out the machine instructions using the MIR serialization
100 ModuleSlotTracker &MST;
101 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
102 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
105 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
106 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
107 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
108 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
109 StackObjectOperandMapping(StackObjectOperandMapping) {}
111 void print(const MachineBasicBlock &MBB);
113 void print(const MachineInstr &MI);
114 void printMBBReference(const MachineBasicBlock &MBB);
115 void printIRBlockReference(const BasicBlock &BB);
116 void printIRValueReference(const Value &V);
117 void printStackObjectReference(int FrameIndex);
118 void printOffset(int64_t Offset);
119 void printTargetFlags(const MachineOperand &Op);
120 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
121 unsigned I, bool ShouldPrintRegisterTies, bool IsDef = false);
122 void print(const MachineMemOperand &Op);
124 void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
127 } // end namespace llvm
132 /// This struct serializes the LLVM IR module.
133 template <> struct BlockScalarTraits<Module> {
134 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
135 Mod.print(OS, nullptr);
137 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
138 llvm_unreachable("LLVM Module is supposed to be parsed separately");
143 } // end namespace yaml
144 } // end namespace llvm
146 static void printReg(unsigned Reg, raw_ostream &OS,
147 const TargetRegisterInfo *TRI) {
148 // TODO: Print Stack Slots.
151 else if (TargetRegisterInfo::isVirtualRegister(Reg))
152 OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
153 else if (Reg < TRI->getNumRegs())
154 OS << '%' << StringRef(TRI->getName(Reg)).lower();
156 llvm_unreachable("Can't print this kind of register yet");
159 static void printReg(unsigned Reg, yaml::StringValue &Dest,
160 const TargetRegisterInfo *TRI) {
161 raw_string_ostream OS(Dest.Value);
162 printReg(Reg, OS, TRI);
165 void MIRPrinter::print(const MachineFunction &MF) {
166 initRegisterMaskIds(MF);
168 yaml::MachineFunction YamlMF;
169 YamlMF.Name = MF.getName();
170 YamlMF.Alignment = MF.getAlignment();
171 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
172 YamlMF.HasInlineAsm = MF.hasInlineAsm();
173 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
174 ModuleSlotTracker MST(MF.getFunction()->getParent());
175 MST.incorporateFunction(*MF.getFunction());
176 convert(MST, YamlMF.FrameInfo, *MF.getFrameInfo());
177 convertStackObjects(YamlMF, *MF.getFrameInfo(), MF.getMMI(), MST,
178 MF.getSubtarget().getRegisterInfo());
179 if (const auto *ConstantPool = MF.getConstantPool())
180 convert(YamlMF, *ConstantPool);
181 if (const auto *JumpTableInfo = MF.getJumpTableInfo())
182 convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
183 raw_string_ostream StrOS(YamlMF.Body.Value.Value);
184 bool IsNewlineNeeded = false;
185 for (const auto &MBB : MF) {
188 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
190 IsNewlineNeeded = true;
193 yaml::Output Out(OS);
197 void MIRPrinter::convert(yaml::MachineFunction &MF,
198 const MachineRegisterInfo &RegInfo,
199 const TargetRegisterInfo *TRI) {
200 MF.IsSSA = RegInfo.isSSA();
201 MF.TracksRegLiveness = RegInfo.tracksLiveness();
202 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
204 // Print the virtual register definitions.
205 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
206 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
207 yaml::VirtualRegisterDefinition VReg;
210 StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
211 unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
213 printReg(PreferredReg, VReg.PreferredRegister, TRI);
214 MF.VirtualRegisters.push_back(VReg);
217 // Print the live ins.
218 for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
219 yaml::MachineFunctionLiveIn LiveIn;
220 printReg(I->first, LiveIn.Register, TRI);
222 printReg(I->second, LiveIn.VirtualRegister, TRI);
223 MF.LiveIns.push_back(LiveIn);
225 // The used physical register mask is printed as an inverted callee saved
227 const BitVector &UsedPhysRegMask = RegInfo.getUsedPhysRegsMask();
228 if (UsedPhysRegMask.none())
230 std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
231 for (unsigned I = 0, E = UsedPhysRegMask.size(); I != E; ++I) {
232 if (!UsedPhysRegMask[I]) {
233 yaml::FlowStringValue Reg;
234 printReg(I, Reg, TRI);
235 CalleeSavedRegisters.push_back(Reg);
238 MF.CalleeSavedRegisters = CalleeSavedRegisters;
241 void MIRPrinter::convert(ModuleSlotTracker &MST,
242 yaml::MachineFrameInfo &YamlMFI,
243 const MachineFrameInfo &MFI) {
244 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
245 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
246 YamlMFI.HasStackMap = MFI.hasStackMap();
247 YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
248 YamlMFI.StackSize = MFI.getStackSize();
249 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
250 YamlMFI.MaxAlignment = MFI.getMaxAlignment();
251 YamlMFI.AdjustsStack = MFI.adjustsStack();
252 YamlMFI.HasCalls = MFI.hasCalls();
253 YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
254 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
255 YamlMFI.HasVAStart = MFI.hasVAStart();
256 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
257 if (MFI.getSavePoint()) {
258 raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
259 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
260 .printMBBReference(*MFI.getSavePoint());
262 if (MFI.getRestorePoint()) {
263 raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
264 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
265 .printMBBReference(*MFI.getRestorePoint());
269 void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
270 const MachineFrameInfo &MFI,
271 MachineModuleInfo &MMI,
272 ModuleSlotTracker &MST,
273 const TargetRegisterInfo *TRI) {
274 // Process fixed stack objects.
276 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
277 if (MFI.isDeadObjectIndex(I))
280 yaml::FixedMachineStackObject YamlObject;
282 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
283 ? yaml::FixedMachineStackObject::SpillSlot
284 : yaml::FixedMachineStackObject::DefaultType;
285 YamlObject.Offset = MFI.getObjectOffset(I);
286 YamlObject.Size = MFI.getObjectSize(I);
287 YamlObject.Alignment = MFI.getObjectAlignment(I);
288 YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
289 YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
290 MF.FixedStackObjects.push_back(YamlObject);
291 StackObjectOperandMapping.insert(
292 std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
295 // Process ordinary stack objects.
297 for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
298 if (MFI.isDeadObjectIndex(I))
301 yaml::MachineStackObject YamlObject;
303 if (const auto *Alloca = MFI.getObjectAllocation(I))
304 YamlObject.Name.Value =
305 Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
306 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
307 ? yaml::MachineStackObject::SpillSlot
308 : MFI.isVariableSizedObjectIndex(I)
309 ? yaml::MachineStackObject::VariableSized
310 : yaml::MachineStackObject::DefaultType;
311 YamlObject.Offset = MFI.getObjectOffset(I);
312 YamlObject.Size = MFI.getObjectSize(I);
313 YamlObject.Alignment = MFI.getObjectAlignment(I);
315 MF.StackObjects.push_back(YamlObject);
316 StackObjectOperandMapping.insert(std::make_pair(
317 I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
320 for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
321 yaml::StringValue Reg;
322 printReg(CSInfo.getReg(), Reg, TRI);
323 auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
324 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
325 "Invalid stack object index");
326 const FrameIndexOperand &StackObject = StackObjectInfo->second;
327 if (StackObject.IsFixed)
328 MF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
330 MF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
332 for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
333 auto LocalObject = MFI.getLocalFrameObjectMap(I);
334 auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
335 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
336 "Invalid stack object index");
337 const FrameIndexOperand &StackObject = StackObjectInfo->second;
338 assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
339 MF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
342 // Print the stack object references in the frame information class after
343 // converting the stack objects.
344 if (MFI.hasStackProtectorIndex()) {
345 raw_string_ostream StrOS(MF.FrameInfo.StackProtector.Value);
346 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
347 .printStackObjectReference(MFI.getStackProtectorIndex());
350 // Print the debug variable information.
351 for (MachineModuleInfo::VariableDbgInfo &DebugVar :
352 MMI.getVariableDbgInfo()) {
353 auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
354 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
355 "Invalid stack object index");
356 const FrameIndexOperand &StackObject = StackObjectInfo->second;
357 assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
358 auto &Object = MF.StackObjects[StackObject.ID];
360 raw_string_ostream StrOS(Object.DebugVar.Value);
361 DebugVar.Var->printAsOperand(StrOS, MST);
364 raw_string_ostream StrOS(Object.DebugExpr.Value);
365 DebugVar.Expr->printAsOperand(StrOS, MST);
368 raw_string_ostream StrOS(Object.DebugLoc.Value);
369 DebugVar.Loc->printAsOperand(StrOS, MST);
374 void MIRPrinter::convert(yaml::MachineFunction &MF,
375 const MachineConstantPool &ConstantPool) {
377 for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
378 // TODO: Serialize target specific constant pool entries.
379 if (Constant.isMachineConstantPoolEntry())
380 llvm_unreachable("Can't print target specific constant pool entries yet");
382 yaml::MachineConstantPoolValue YamlConstant;
384 raw_string_ostream StrOS(Str);
385 Constant.Val.ConstVal->printAsOperand(StrOS);
386 YamlConstant.ID = ID++;
387 YamlConstant.Value = StrOS.str();
388 YamlConstant.Alignment = Constant.getAlignment();
389 MF.Constants.push_back(YamlConstant);
393 void MIRPrinter::convert(ModuleSlotTracker &MST,
394 yaml::MachineJumpTable &YamlJTI,
395 const MachineJumpTableInfo &JTI) {
396 YamlJTI.Kind = JTI.getEntryKind();
398 for (const auto &Table : JTI.getJumpTables()) {
400 yaml::MachineJumpTable::Entry Entry;
402 for (const auto *MBB : Table.MBBs) {
403 raw_string_ostream StrOS(Str);
404 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
405 .printMBBReference(*MBB);
406 Entry.Blocks.push_back(StrOS.str());
409 YamlJTI.Entries.push_back(Entry);
413 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
414 const auto *TRI = MF.getSubtarget().getRegisterInfo();
416 for (const uint32_t *Mask : TRI->getRegMasks())
417 RegisterMaskIds.insert(std::make_pair(Mask, I++));
420 void MIPrinter::print(const MachineBasicBlock &MBB) {
421 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
422 OS << "bb." << MBB.getNumber();
423 bool HasAttributes = false;
424 if (const auto *BB = MBB.getBasicBlock()) {
426 OS << "." << BB->getName();
428 HasAttributes = true;
430 int Slot = MST.getLocalSlot(BB);
432 OS << "<ir-block badref>";
434 OS << (Twine("%ir-block.") + Twine(Slot)).str();
437 if (MBB.hasAddressTaken()) {
438 OS << (HasAttributes ? ", " : " (");
439 OS << "address-taken";
440 HasAttributes = true;
442 if (MBB.isLandingPad()) {
443 OS << (HasAttributes ? ", " : " (");
445 HasAttributes = true;
447 if (MBB.getAlignment()) {
448 OS << (HasAttributes ? ", " : " (");
449 OS << "align " << MBB.getAlignment();
450 HasAttributes = true;
456 bool HasLineAttributes = false;
457 // Print the successors
458 if (!MBB.succ_empty()) {
459 OS.indent(2) << "successors: ";
460 for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
461 if (I != MBB.succ_begin())
463 printMBBReference(**I);
464 if (MBB.hasSuccessorWeights())
465 OS << '(' << MBB.getSuccWeight(I) << ')';
468 HasLineAttributes = true;
471 // Print the live in registers.
472 const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
473 assert(TRI && "Expected target register info");
474 if (!MBB.livein_empty()) {
475 OS.indent(2) << "liveins: ";
476 for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
477 if (I != MBB.livein_begin())
479 printReg(*I, OS, TRI);
482 HasLineAttributes = true;
485 if (HasLineAttributes)
487 bool IsInBundle = false;
488 for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
489 const MachineInstr &MI = *I;
490 if (IsInBundle && !MI.isInsideBundle()) {
491 OS.indent(2) << "}\n";
494 OS.indent(IsInBundle ? 4 : 2);
496 if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
503 OS.indent(2) << "}\n";
506 /// Return true when an instruction has tied register that can't be determined
507 /// by the instruction's descriptor.
508 static bool hasComplexRegisterTies(const MachineInstr &MI) {
509 const MCInstrDesc &MCID = MI.getDesc();
510 for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
511 const auto &Operand = MI.getOperand(I);
512 if (!Operand.isReg() || Operand.isDef())
513 // Ignore the defined registers as MCID marks only the uses as tied.
515 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
516 int TiedIdx = Operand.isTied() ? int(MI.findTiedOperandIdx(I)) : -1;
517 if (ExpectedTiedIdx != TiedIdx)
523 void MIPrinter::print(const MachineInstr &MI) {
524 const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
525 const auto *TRI = SubTarget.getRegisterInfo();
526 assert(TRI && "Expected target register info");
527 const auto *TII = SubTarget.getInstrInfo();
528 assert(TII && "Expected target instruction info");
529 if (MI.isCFIInstruction())
530 assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
532 bool ShouldPrintRegisterTies = hasComplexRegisterTies(MI);
533 unsigned I = 0, E = MI.getNumOperands();
534 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
535 !MI.getOperand(I).isImplicit();
539 print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies, /*IsDef=*/true);
544 if (MI.getFlag(MachineInstr::FrameSetup))
545 OS << "frame-setup ";
546 OS << TII->getName(MI.getOpcode());
550 bool NeedComma = false;
554 print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies);
558 if (MI.getDebugLoc()) {
561 OS << " debug-location ";
562 MI.getDebugLoc()->printAsOperand(OS, MST);
565 if (!MI.memoperands_empty()) {
567 bool NeedComma = false;
568 for (const auto *Op : MI.memoperands()) {
577 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
578 OS << "%bb." << MBB.getNumber();
579 if (const auto *BB = MBB.getBasicBlock()) {
581 OS << '.' << BB->getName();
585 static void printIRSlotNumber(raw_ostream &OS, int Slot) {
592 void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
595 printLLVMNameWithoutPrefix(OS, BB.getName());
598 const Function *F = BB.getParent();
600 if (F == MST.getCurrentFunction()) {
601 Slot = MST.getLocalSlot(&BB);
603 ModuleSlotTracker CustomMST(F->getParent(),
604 /*ShouldInitializeAllMetadata=*/false);
605 CustomMST.incorporateFunction(*F);
606 Slot = CustomMST.getLocalSlot(&BB);
608 printIRSlotNumber(OS, Slot);
611 void MIPrinter::printIRValueReference(const Value &V) {
612 if (isa<GlobalValue>(V)) {
613 V.printAsOperand(OS, /*PrintType=*/false, MST);
618 printLLVMNameWithoutPrefix(OS, V.getName());
621 if (isa<Constant>(V)) {
622 // Machine memory operands can load/store to/from constant value pointers.
623 // TODO: Serialize the constant values.
624 OS << "<unserializable ir value>";
627 printIRSlotNumber(OS, MST.getLocalSlot(&V));
630 void MIPrinter::printStackObjectReference(int FrameIndex) {
631 auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
632 assert(ObjectInfo != StackObjectOperandMapping.end() &&
633 "Invalid frame index");
634 const FrameIndexOperand &Operand = ObjectInfo->second;
635 if (Operand.IsFixed) {
636 OS << "%fixed-stack." << Operand.ID;
639 OS << "%stack." << Operand.ID;
640 if (!Operand.Name.empty())
641 OS << '.' << Operand.Name;
644 void MIPrinter::printOffset(int64_t Offset) {
648 OS << " - " << -Offset;
651 OS << " + " << Offset;
654 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
655 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
656 for (const auto &I : Flags) {
664 void MIPrinter::printTargetFlags(const MachineOperand &Op) {
665 if (!Op.getTargetFlags())
668 Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo();
669 assert(TII && "expected instruction info");
670 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
671 OS << "target-flags(";
672 const bool HasDirectFlags = Flags.first;
673 const bool HasBitmaskFlags = Flags.second;
674 if (!HasDirectFlags && !HasBitmaskFlags) {
678 if (HasDirectFlags) {
679 if (const auto *Name = getTargetFlagName(TII, Flags.first))
682 OS << "<unknown target flag>";
684 if (!HasBitmaskFlags) {
688 bool IsCommaNeeded = HasDirectFlags;
689 unsigned BitMask = Flags.second;
690 auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
691 for (const auto &Mask : BitMasks) {
692 // Check if the flag's bitmask has the bits of the current mask set.
693 if ((BitMask & Mask.first) == Mask.first) {
696 IsCommaNeeded = true;
698 // Clear the bits which were serialized from the flag's bitmask.
699 BitMask &= ~(Mask.first);
703 // When the resulting flag's bitmask isn't zero, we know that we didn't
704 // serialize all of the bit flags.
707 OS << "<unknown bitmask target flag>";
712 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
713 const auto *TII = MF.getSubtarget().getInstrInfo();
714 assert(TII && "expected instruction info");
715 auto Indices = TII->getSerializableTargetIndices();
716 for (const auto &I : Indices) {
717 if (I.first == Index) {
724 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
725 unsigned I, bool ShouldPrintRegisterTies, bool IsDef) {
726 printTargetFlags(Op);
727 switch (Op.getType()) {
728 case MachineOperand::MO_Register:
730 OS << (Op.isDef() ? "implicit-def " : "implicit ");
731 else if (!IsDef && Op.isDef())
732 // Print the 'def' flag only when the operand is defined after '='.
734 if (Op.isInternalRead())
742 if (Op.isEarlyClobber())
743 OS << "early-clobber ";
746 printReg(Op.getReg(), OS, TRI);
747 // Print the sub register.
748 if (Op.getSubReg() != 0)
749 OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
750 if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
751 OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")";
753 case MachineOperand::MO_Immediate:
756 case MachineOperand::MO_CImmediate:
757 Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
759 case MachineOperand::MO_FPImmediate:
760 Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
762 case MachineOperand::MO_MachineBasicBlock:
763 printMBBReference(*Op.getMBB());
765 case MachineOperand::MO_FrameIndex:
766 printStackObjectReference(Op.getIndex());
768 case MachineOperand::MO_ConstantPoolIndex:
769 OS << "%const." << Op.getIndex();
770 printOffset(Op.getOffset());
772 case MachineOperand::MO_TargetIndex: {
773 OS << "target-index(";
774 if (const auto *Name = getTargetIndexName(
775 *Op.getParent()->getParent()->getParent(), Op.getIndex()))
780 printOffset(Op.getOffset());
783 case MachineOperand::MO_JumpTableIndex:
784 OS << "%jump-table." << Op.getIndex();
786 case MachineOperand::MO_ExternalSymbol:
788 printLLVMNameWithoutPrefix(OS, Op.getSymbolName());
789 printOffset(Op.getOffset());
791 case MachineOperand::MO_GlobalAddress:
792 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
793 printOffset(Op.getOffset());
795 case MachineOperand::MO_BlockAddress:
796 OS << "blockaddress(";
797 Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
800 printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
802 printOffset(Op.getOffset());
804 case MachineOperand::MO_RegisterMask: {
805 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
806 if (RegMaskInfo != RegisterMaskIds.end())
807 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
809 llvm_unreachable("Can't print this machine register mask yet.");
812 case MachineOperand::MO_RegisterLiveOut: {
813 const uint32_t *RegMask = Op.getRegLiveOut();
815 bool IsCommaNeeded = false;
816 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
817 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
820 printReg(Reg, OS, TRI);
821 IsCommaNeeded = true;
827 case MachineOperand::MO_Metadata:
828 Op.getMetadata()->printAsOperand(OS, MST);
830 case MachineOperand::MO_MCSymbol:
831 OS << "<mcsymbol " << *Op.getMCSymbol() << ">";
833 case MachineOperand::MO_CFIIndex: {
834 const auto &MMI = Op.getParent()->getParent()->getParent()->getMMI();
835 print(MMI.getFrameInstructions()[Op.getCFIIndex()], TRI);
841 void MIPrinter::print(const MachineMemOperand &Op) {
843 // TODO: Print operand's target specific flags.
846 if (Op.isNonTemporal())
847 OS << "non-temporal ";
848 if (Op.isInvariant())
853 assert(Op.isStore() && "Non load machine operand must be a store");
856 OS << Op.getSize() << (Op.isLoad() ? " from " : " into ");
857 if (const Value *Val = Op.getValue()) {
858 printIRValueReference(*Val);
860 const PseudoSourceValue *PVal = Op.getPseudoValue();
861 assert(PVal && "Expected a pseudo source value");
862 switch (PVal->kind()) {
863 case PseudoSourceValue::Stack:
866 case PseudoSourceValue::GOT:
869 case PseudoSourceValue::JumpTable:
872 case PseudoSourceValue::ConstantPool:
873 OS << "constant-pool";
875 case PseudoSourceValue::FixedStack:
876 printStackObjectReference(
877 cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex());
879 case PseudoSourceValue::GlobalValueCallEntry:
881 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
882 OS, /*PrintType=*/false, MST);
884 case PseudoSourceValue::ExternalSymbolCallEntry:
885 OS << "call-entry $";
886 printLLVMNameWithoutPrefix(
887 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
891 printOffset(Op.getOffset());
892 if (Op.getBaseAlignment() != Op.getSize())
893 OS << ", align " << Op.getBaseAlignment();
894 auto AAInfo = Op.getAAInfo();
897 AAInfo.TBAA->printAsOperand(OS, MST);
900 OS << ", !alias.scope ";
901 AAInfo.Scope->printAsOperand(OS, MST);
903 if (AAInfo.NoAlias) {
905 AAInfo.NoAlias->printAsOperand(OS, MST);
907 if (Op.getRanges()) {
909 Op.getRanges()->printAsOperand(OS, MST);
914 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
915 const TargetRegisterInfo *TRI) {
916 int Reg = TRI->getLLVMRegNum(DwarfReg, true);
921 printReg(Reg, OS, TRI);
924 void MIPrinter::print(const MCCFIInstruction &CFI,
925 const TargetRegisterInfo *TRI) {
926 switch (CFI.getOperation()) {
927 case MCCFIInstruction::OpSameValue:
928 OS << ".cfi_same_value ";
931 printCFIRegister(CFI.getRegister(), OS, TRI);
933 case MCCFIInstruction::OpOffset:
934 OS << ".cfi_offset ";
937 printCFIRegister(CFI.getRegister(), OS, TRI);
938 OS << ", " << CFI.getOffset();
940 case MCCFIInstruction::OpDefCfaRegister:
941 OS << ".cfi_def_cfa_register ";
944 printCFIRegister(CFI.getRegister(), OS, TRI);
946 case MCCFIInstruction::OpDefCfaOffset:
947 OS << ".cfi_def_cfa_offset ";
950 OS << CFI.getOffset();
952 case MCCFIInstruction::OpDefCfa:
953 OS << ".cfi_def_cfa ";
956 printCFIRegister(CFI.getRegister(), OS, TRI);
957 OS << ", " << CFI.getOffset();
960 // TODO: Print the other CFI Operations.
961 OS << "<unserializable cfi operation>";
966 void llvm::printMIR(raw_ostream &OS, const Module &M) {
967 yaml::Output Out(OS);
968 Out << const_cast<Module &>(M);
971 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
972 MIRPrinter Printer(OS);