1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/MIRYamlMapping.h"
21 #include "llvm/IR/BasicBlock.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/IR/ModuleSlotTracker.h"
24 #include "llvm/Support/MemoryBuffer.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Support/YAMLTraits.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
34 /// This class prints out the machine functions using the MIR serialization
38 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
41 MIRPrinter(raw_ostream &OS) : OS(OS) {}
43 void print(const MachineFunction &MF);
45 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo);
46 void convert(yaml::MachineFrameInfo &YamlMFI, const MachineFrameInfo &MFI);
47 void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
48 const MachineBasicBlock &MBB);
51 void initRegisterMaskIds(const MachineFunction &MF);
54 /// This class prints out the machine instructions using the MIR serialization
58 ModuleSlotTracker &MST;
59 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
62 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
63 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds)
64 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds) {}
66 void print(const MachineInstr &MI);
67 void printMBBReference(const MachineBasicBlock &MBB);
68 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
71 } // end anonymous namespace
76 /// This struct serializes the LLVM IR module.
77 template <> struct BlockScalarTraits<Module> {
78 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
79 Mod.print(OS, nullptr);
81 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
82 llvm_unreachable("LLVM Module is supposed to be parsed separately");
87 } // end namespace yaml
88 } // end namespace llvm
90 void MIRPrinter::print(const MachineFunction &MF) {
91 initRegisterMaskIds(MF);
93 yaml::MachineFunction YamlMF;
94 YamlMF.Name = MF.getName();
95 YamlMF.Alignment = MF.getAlignment();
96 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
97 YamlMF.HasInlineAsm = MF.hasInlineAsm();
98 convert(YamlMF, MF.getRegInfo());
99 convert(YamlMF.FrameInfo, *MF.getFrameInfo());
102 ModuleSlotTracker MST(MF.getFunction()->getParent());
103 for (const auto &MBB : MF) {
104 // TODO: Allow printing of non sequentially numbered MBBs.
105 // This is currently needed as the basic block references get their index
106 // from MBB.getNumber(), thus it should be sequential so that the parser can
107 // map back to the correct MBBs when parsing the output.
108 assert(MBB.getNumber() == I++ &&
109 "Can't print MBBs that aren't sequentially numbered");
111 yaml::MachineBasicBlock YamlMBB;
112 convert(MST, YamlMBB, MBB);
113 YamlMF.BasicBlocks.push_back(YamlMBB);
115 yaml::Output Out(OS);
119 void MIRPrinter::convert(yaml::MachineFunction &MF,
120 const MachineRegisterInfo &RegInfo) {
121 MF.IsSSA = RegInfo.isSSA();
122 MF.TracksRegLiveness = RegInfo.tracksLiveness();
123 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
126 void MIRPrinter::convert(yaml::MachineFrameInfo &YamlMFI,
127 const MachineFrameInfo &MFI) {
128 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
129 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
130 YamlMFI.HasStackMap = MFI.hasStackMap();
131 YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
132 YamlMFI.StackSize = MFI.getStackSize();
133 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
134 YamlMFI.MaxAlignment = MFI.getMaxAlignment();
135 YamlMFI.AdjustsStack = MFI.adjustsStack();
136 YamlMFI.HasCalls = MFI.hasCalls();
137 YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
138 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
139 YamlMFI.HasVAStart = MFI.hasVAStart();
140 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
143 void MIRPrinter::convert(ModuleSlotTracker &MST,
144 yaml::MachineBasicBlock &YamlMBB,
145 const MachineBasicBlock &MBB) {
146 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
147 YamlMBB.ID = (unsigned)MBB.getNumber();
148 // TODO: Serialize unnamed BB references.
149 if (const auto *BB = MBB.getBasicBlock())
150 YamlMBB.Name.Value = BB->hasName() ? BB->getName() : "<unnamed bb>";
152 YamlMBB.Name.Value = "";
153 YamlMBB.Alignment = MBB.getAlignment();
154 YamlMBB.AddressTaken = MBB.hasAddressTaken();
155 YamlMBB.IsLandingPad = MBB.isLandingPad();
156 for (const auto *SuccMBB : MBB.successors()) {
158 raw_string_ostream StrOS(Str);
159 MIPrinter(StrOS, MST, RegisterMaskIds).printMBBReference(*SuccMBB);
160 YamlMBB.Successors.push_back(StrOS.str());
163 // Print the machine instructions.
164 YamlMBB.Instructions.reserve(MBB.size());
166 for (const auto &MI : MBB) {
167 raw_string_ostream StrOS(Str);
168 MIPrinter(StrOS, MST, RegisterMaskIds).print(MI);
169 YamlMBB.Instructions.push_back(StrOS.str());
174 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
175 const auto *TRI = MF.getSubtarget().getRegisterInfo();
177 for (const uint32_t *Mask : TRI->getRegMasks())
178 RegisterMaskIds.insert(std::make_pair(Mask, I++));
181 void MIPrinter::print(const MachineInstr &MI) {
182 const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
183 const auto *TRI = SubTarget.getRegisterInfo();
184 assert(TRI && "Expected target register info");
185 const auto *TII = SubTarget.getInstrInfo();
186 assert(TII && "Expected target instruction info");
188 unsigned I = 0, E = MI.getNumOperands();
189 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
190 !MI.getOperand(I).isImplicit();
194 print(MI.getOperand(I), TRI);
199 OS << TII->getName(MI.getOpcode());
200 // TODO: Print the instruction flags, machine mem operands.
204 bool NeedComma = false;
208 print(MI.getOperand(I), TRI);
213 static void printReg(unsigned Reg, raw_ostream &OS,
214 const TargetRegisterInfo *TRI) {
215 // TODO: Print Stack Slots.
216 // TODO: Print virtual registers.
219 else if (Reg < TRI->getNumRegs())
220 OS << '%' << StringRef(TRI->getName(Reg)).lower();
222 llvm_unreachable("Can't print this kind of register yet");
225 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
226 OS << "%bb." << MBB.getNumber();
227 if (const auto *BB = MBB.getBasicBlock()) {
229 OS << '.' << BB->getName();
233 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
234 switch (Op.getType()) {
235 case MachineOperand::MO_Register:
236 // TODO: Print the other register flags.
238 OS << (Op.isDef() ? "implicit-def " : "implicit ");
245 printReg(Op.getReg(), OS, TRI);
246 // TODO: Print sub register.
248 case MachineOperand::MO_Immediate:
251 case MachineOperand::MO_MachineBasicBlock:
252 printMBBReference(*Op.getMBB());
254 case MachineOperand::MO_GlobalAddress:
255 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
256 // TODO: Print offset and target flags.
258 case MachineOperand::MO_RegisterMask: {
259 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
260 if (RegMaskInfo != RegisterMaskIds.end())
261 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
263 llvm_unreachable("Can't print this machine register mask yet.");
267 // TODO: Print the other machine operands.
268 llvm_unreachable("Can't print this machine operand at the moment");
272 void llvm::printMIR(raw_ostream &OS, const Module &M) {
273 yaml::Output Out(OS);
274 Out << const_cast<Module &>(M);
277 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
278 MIRPrinter Printer(OS);