1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/MIRYamlMapping.h"
21 #include "llvm/IR/BasicBlock.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/IR/ModuleSlotTracker.h"
24 #include "llvm/Support/MemoryBuffer.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Support/YAMLTraits.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
34 /// This class prints out the machine functions using the MIR serialization
38 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
41 MIRPrinter(raw_ostream &OS) : OS(OS) {}
43 void print(const MachineFunction &MF);
45 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
46 const TargetRegisterInfo *TRI);
47 void convert(yaml::MachineFrameInfo &YamlMFI, const MachineFrameInfo &MFI);
48 void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
49 const MachineBasicBlock &MBB);
50 void convertStackObjects(yaml::MachineFunction &MF,
51 const MachineFrameInfo &MFI);
54 void initRegisterMaskIds(const MachineFunction &MF);
57 /// This class prints out the machine instructions using the MIR serialization
61 ModuleSlotTracker &MST;
62 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
65 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
66 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds)
67 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds) {}
69 void print(const MachineInstr &MI);
70 void printMBBReference(const MachineBasicBlock &MBB);
71 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
74 } // end anonymous namespace
79 /// This struct serializes the LLVM IR module.
80 template <> struct BlockScalarTraits<Module> {
81 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
82 Mod.print(OS, nullptr);
84 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
85 llvm_unreachable("LLVM Module is supposed to be parsed separately");
90 } // end namespace yaml
91 } // end namespace llvm
93 void MIRPrinter::print(const MachineFunction &MF) {
94 initRegisterMaskIds(MF);
96 yaml::MachineFunction YamlMF;
97 YamlMF.Name = MF.getName();
98 YamlMF.Alignment = MF.getAlignment();
99 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
100 YamlMF.HasInlineAsm = MF.hasInlineAsm();
101 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
102 convert(YamlMF.FrameInfo, *MF.getFrameInfo());
103 convertStackObjects(YamlMF, *MF.getFrameInfo());
106 ModuleSlotTracker MST(MF.getFunction()->getParent());
107 for (const auto &MBB : MF) {
108 // TODO: Allow printing of non sequentially numbered MBBs.
109 // This is currently needed as the basic block references get their index
110 // from MBB.getNumber(), thus it should be sequential so that the parser can
111 // map back to the correct MBBs when parsing the output.
112 assert(MBB.getNumber() == I++ &&
113 "Can't print MBBs that aren't sequentially numbered");
115 yaml::MachineBasicBlock YamlMBB;
116 convert(MST, YamlMBB, MBB);
117 YamlMF.BasicBlocks.push_back(YamlMBB);
119 yaml::Output Out(OS);
123 void MIRPrinter::convert(yaml::MachineFunction &MF,
124 const MachineRegisterInfo &RegInfo,
125 const TargetRegisterInfo *TRI) {
126 MF.IsSSA = RegInfo.isSSA();
127 MF.TracksRegLiveness = RegInfo.tracksLiveness();
128 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
130 // Print the virtual register definitions.
131 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
132 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
133 yaml::VirtualRegisterDefinition VReg;
136 StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
137 MF.VirtualRegisters.push_back(VReg);
141 void MIRPrinter::convert(yaml::MachineFrameInfo &YamlMFI,
142 const MachineFrameInfo &MFI) {
143 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
144 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
145 YamlMFI.HasStackMap = MFI.hasStackMap();
146 YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
147 YamlMFI.StackSize = MFI.getStackSize();
148 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
149 YamlMFI.MaxAlignment = MFI.getMaxAlignment();
150 YamlMFI.AdjustsStack = MFI.adjustsStack();
151 YamlMFI.HasCalls = MFI.hasCalls();
152 YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
153 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
154 YamlMFI.HasVAStart = MFI.hasVAStart();
155 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
158 void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
159 const MachineFrameInfo &MFI) {
161 for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
162 if (MFI.isDeadObjectIndex(I))
165 yaml::MachineStackObject YamlObject;
166 YamlObject.ID = ID++;
167 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
168 ? yaml::MachineStackObject::SpillSlot
169 : yaml::MachineStackObject::DefaultType;
170 YamlObject.Offset = MFI.getObjectOffset(I);
171 YamlObject.Size = MFI.getObjectSize(I);
172 YamlObject.Alignment = MFI.getObjectAlignment(I);
174 MF.StackObjects.push_back(YamlObject);
175 // TODO: Store the mapping between object IDs and object indices to print
176 // the stack object references correctly.
180 void MIRPrinter::convert(ModuleSlotTracker &MST,
181 yaml::MachineBasicBlock &YamlMBB,
182 const MachineBasicBlock &MBB) {
183 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
184 YamlMBB.ID = (unsigned)MBB.getNumber();
185 // TODO: Serialize unnamed BB references.
186 if (const auto *BB = MBB.getBasicBlock())
187 YamlMBB.Name.Value = BB->hasName() ? BB->getName() : "<unnamed bb>";
189 YamlMBB.Name.Value = "";
190 YamlMBB.Alignment = MBB.getAlignment();
191 YamlMBB.AddressTaken = MBB.hasAddressTaken();
192 YamlMBB.IsLandingPad = MBB.isLandingPad();
193 for (const auto *SuccMBB : MBB.successors()) {
195 raw_string_ostream StrOS(Str);
196 MIPrinter(StrOS, MST, RegisterMaskIds).printMBBReference(*SuccMBB);
197 YamlMBB.Successors.push_back(StrOS.str());
200 // Print the machine instructions.
201 YamlMBB.Instructions.reserve(MBB.size());
203 for (const auto &MI : MBB) {
204 raw_string_ostream StrOS(Str);
205 MIPrinter(StrOS, MST, RegisterMaskIds).print(MI);
206 YamlMBB.Instructions.push_back(StrOS.str());
211 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
212 const auto *TRI = MF.getSubtarget().getRegisterInfo();
214 for (const uint32_t *Mask : TRI->getRegMasks())
215 RegisterMaskIds.insert(std::make_pair(Mask, I++));
218 void MIPrinter::print(const MachineInstr &MI) {
219 const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
220 const auto *TRI = SubTarget.getRegisterInfo();
221 assert(TRI && "Expected target register info");
222 const auto *TII = SubTarget.getInstrInfo();
223 assert(TII && "Expected target instruction info");
225 unsigned I = 0, E = MI.getNumOperands();
226 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
227 !MI.getOperand(I).isImplicit();
231 print(MI.getOperand(I), TRI);
236 OS << TII->getName(MI.getOpcode());
237 // TODO: Print the instruction flags, machine mem operands.
241 bool NeedComma = false;
245 print(MI.getOperand(I), TRI);
250 static void printReg(unsigned Reg, raw_ostream &OS,
251 const TargetRegisterInfo *TRI) {
252 // TODO: Print Stack Slots.
253 // TODO: Print virtual registers.
256 else if (Reg < TRI->getNumRegs())
257 OS << '%' << StringRef(TRI->getName(Reg)).lower();
259 llvm_unreachable("Can't print this kind of register yet");
262 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
263 OS << "%bb." << MBB.getNumber();
264 if (const auto *BB = MBB.getBasicBlock()) {
266 OS << '.' << BB->getName();
270 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
271 switch (Op.getType()) {
272 case MachineOperand::MO_Register:
273 // TODO: Print the other register flags.
275 OS << (Op.isDef() ? "implicit-def " : "implicit ");
282 printReg(Op.getReg(), OS, TRI);
283 // TODO: Print sub register.
285 case MachineOperand::MO_Immediate:
288 case MachineOperand::MO_MachineBasicBlock:
289 printMBBReference(*Op.getMBB());
291 case MachineOperand::MO_GlobalAddress:
292 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
293 // TODO: Print offset and target flags.
295 case MachineOperand::MO_RegisterMask: {
296 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
297 if (RegMaskInfo != RegisterMaskIds.end())
298 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
300 llvm_unreachable("Can't print this machine register mask yet.");
304 // TODO: Print the other machine operands.
305 llvm_unreachable("Can't print this machine operand at the moment");
309 void llvm::printMIR(raw_ostream &OS, const Module &M) {
310 yaml::Output Out(OS);
311 Out << const_cast<Module &>(M);
314 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
315 MIRPrinter Printer(OS);