1 //===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Collect the sequence of machine instructions for a basic block.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineBasicBlock.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallString.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "llvm/CodeGen/LiveVariables.h"
19 #include "llvm/CodeGen/MachineDominators.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SlotIndexes.h"
25 #include "llvm/IR/BasicBlock.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/ModuleSlotTracker.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Target/TargetSubtargetInfo.h"
39 #define DEBUG_TYPE "codegen"
41 MachineBasicBlock::MachineBasicBlock(MachineFunction &mf, const BasicBlock *bb)
42 : BB(bb), Number(-1), xParent(&mf), Alignment(0), IsLandingPad(false),
43 AddressTaken(false), CachedMCSymbol(nullptr) {
47 MachineBasicBlock::~MachineBasicBlock() {
50 /// getSymbol - Return the MCSymbol for this basic block.
52 MCSymbol *MachineBasicBlock::getSymbol() const {
53 if (!CachedMCSymbol) {
54 const MachineFunction *MF = getParent();
55 MCContext &Ctx = MF->getContext();
56 const char *Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
57 CachedMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB" +
58 Twine(MF->getFunctionNumber()) +
59 "_" + Twine(getNumber()));
62 return CachedMCSymbol;
66 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) {
71 /// addNodeToList (MBB) - When an MBB is added to an MF, we need to update the
72 /// parent pointer of the MBB, the MBB numbering, and any instructions in the
73 /// MBB to be on the right operand list for registers.
75 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
76 /// gets the next available unique MBB number. If it is removed from a
77 /// MachineFunction, it goes back to being #-1.
78 void ilist_traits<MachineBasicBlock>::addNodeToList(MachineBasicBlock *N) {
79 MachineFunction &MF = *N->getParent();
80 N->Number = MF.addToMBBNumbering(N);
82 // Make sure the instructions have their operands in the reginfo lists.
83 MachineRegisterInfo &RegInfo = MF.getRegInfo();
84 for (MachineBasicBlock::instr_iterator
85 I = N->instr_begin(), E = N->instr_end(); I != E; ++I)
86 I->AddRegOperandsToUseLists(RegInfo);
89 void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock *N) {
90 N->getParent()->removeFromMBBNumbering(N->Number);
95 /// addNodeToList (MI) - When we add an instruction to a basic block
96 /// list, we update its parent pointer and add its operands from reg use/def
97 /// lists if appropriate.
98 void ilist_traits<MachineInstr>::addNodeToList(MachineInstr *N) {
99 assert(!N->getParent() && "machine instruction already in a basic block");
100 N->setParent(Parent);
102 // Add the instruction's register operands to their corresponding
104 MachineFunction *MF = Parent->getParent();
105 N->AddRegOperandsToUseLists(MF->getRegInfo());
108 /// removeNodeFromList (MI) - When we remove an instruction from a basic block
109 /// list, we update its parent pointer and remove its operands from reg use/def
110 /// lists if appropriate.
111 void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr *N) {
112 assert(N->getParent() && "machine instruction not in a basic block");
114 // Remove from the use/def lists.
115 if (MachineFunction *MF = N->getParent()->getParent())
116 N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
118 N->setParent(nullptr);
121 /// transferNodesFromList (MI) - When moving a range of instructions from one
122 /// MBB list to another, we need to update the parent pointers and the use/def
124 void ilist_traits<MachineInstr>::
125 transferNodesFromList(ilist_traits<MachineInstr> &fromList,
126 ilist_iterator<MachineInstr> first,
127 ilist_iterator<MachineInstr> last) {
128 assert(Parent->getParent() == fromList.Parent->getParent() &&
129 "MachineInstr parent mismatch!");
131 // Splice within the same MBB -> no change.
132 if (Parent == fromList.Parent) return;
134 // If splicing between two blocks within the same function, just update the
136 for (; first != last; ++first)
137 first->setParent(Parent);
140 void ilist_traits<MachineInstr>::deleteNode(MachineInstr* MI) {
141 assert(!MI->getParent() && "MI is still in a block!");
142 Parent->getParent()->DeleteMachineInstr(MI);
145 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() {
146 instr_iterator I = instr_begin(), E = instr_end();
147 while (I != E && I->isPHI())
149 assert((I == E || !I->isInsideBundle()) &&
150 "First non-phi MI cannot be inside a bundle!");
154 MachineBasicBlock::iterator
155 MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) {
157 while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue()))
159 // FIXME: This needs to change if we wish to bundle labels / dbg_values
160 // inside the bundle.
161 assert((I == E || !I->isInsideBundle()) &&
162 "First non-phi / non-label instruction is inside a bundle!");
166 MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
167 iterator B = begin(), E = end(), I = E;
168 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
170 while (I != E && !I->isTerminator())
175 MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() {
176 instr_iterator B = instr_begin(), E = instr_end(), I = E;
177 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
179 while (I != E && !I->isTerminator())
184 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonDebugInstr() {
185 // Skip over begin-of-block dbg_value instructions.
186 iterator I = begin(), E = end();
187 while (I != E && I->isDebugValue())
192 MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() {
193 // Skip over end-of-block dbg_value instructions.
194 instr_iterator B = instr_begin(), I = instr_end();
197 // Return instruction that starts a bundle.
198 if (I->isDebugValue() || I->isInsideBundle())
202 // The block is all debug values.
206 const MachineBasicBlock *MachineBasicBlock::getLandingPadSuccessor() const {
207 // A block with a landing pad successor only has one other successor.
210 for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
211 if ((*I)->isLandingPad())
216 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
217 void MachineBasicBlock::dump() const {
222 StringRef MachineBasicBlock::getName() const {
223 if (const BasicBlock *LBB = getBasicBlock())
224 return LBB->getName();
229 /// Return a hopefully unique identifier for this block.
230 std::string MachineBasicBlock::getFullName() const {
233 Name = (getParent()->getName() + ":").str();
235 Name += getBasicBlock()->getName();
237 Name += ("BB" + Twine(getNumber())).str();
241 void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const {
242 const MachineFunction *MF = getParent();
244 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
248 const Function *F = MF->getFunction();
249 const Module *M = F ? F->getParent() : nullptr;
250 ModuleSlotTracker MST(M);
251 print(OS, MST, Indexes);
254 void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
255 SlotIndexes *Indexes) const {
256 const MachineFunction *MF = getParent();
258 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
264 OS << Indexes->getMBBStartIdx(this) << '\t';
266 OS << "BB#" << getNumber() << ": ";
268 const char *Comma = "";
269 if (const BasicBlock *LBB = getBasicBlock()) {
270 OS << Comma << "derived from LLVM BB ";
271 LBB->printAsOperand(OS, /*PrintType=*/false, MST);
274 if (isLandingPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; }
275 if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; }
277 OS << Comma << "Align " << Alignment << " (" << (1u << Alignment)
282 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
283 if (!livein_empty()) {
284 if (Indexes) OS << '\t';
286 for (livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
287 OS << ' ' << PrintReg(*I, TRI);
290 // Print the preds of this block according to the CFG.
292 if (Indexes) OS << '\t';
293 OS << " Predecessors according to CFG:";
294 for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
295 OS << " BB#" << (*PI)->getNumber();
299 for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) {
301 if (Indexes->hasIndex(I))
302 OS << Indexes->getInstructionIndex(I);
306 if (I->isInsideBundle())
311 // Print the successors of this block according to the CFG.
313 if (Indexes) OS << '\t';
314 OS << " Successors according to CFG:";
315 for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) {
316 OS << " BB#" << (*SI)->getNumber();
317 if (!Weights.empty())
318 OS << '(' << *getWeightIterator(SI) << ')';
324 void MachineBasicBlock::printAsOperand(raw_ostream &OS, bool /*PrintType*/) const {
325 OS << "BB#" << getNumber();
328 void MachineBasicBlock::removeLiveIn(unsigned Reg) {
329 std::vector<unsigned>::iterator I =
330 std::find(LiveIns.begin(), LiveIns.end(), Reg);
331 if (I != LiveIns.end())
335 bool MachineBasicBlock::isLiveIn(unsigned Reg) const {
336 livein_iterator I = std::find(livein_begin(), livein_end(), Reg);
337 return I != livein_end();
341 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) {
342 assert(getParent() && "MBB must be inserted in function");
343 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg");
344 assert(RC && "Register class is required");
345 assert((isLandingPad() || this == &getParent()->front()) &&
346 "Only the entry block and landing pads can have physreg live ins");
348 bool LiveIn = isLiveIn(PhysReg);
349 iterator I = SkipPHIsAndLabels(begin()), E = end();
350 MachineRegisterInfo &MRI = getParent()->getRegInfo();
351 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
353 // Look for an existing copy.
355 for (;I != E && I->isCopy(); ++I)
356 if (I->getOperand(1).getReg() == PhysReg) {
357 unsigned VirtReg = I->getOperand(0).getReg();
358 if (!MRI.constrainRegClass(VirtReg, RC))
359 llvm_unreachable("Incompatible live-in register class.");
363 // No luck, create a virtual register.
364 unsigned VirtReg = MRI.createVirtualRegister(RC);
365 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
366 .addReg(PhysReg, RegState::Kill);
372 void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
373 getParent()->splice(NewAfter, this);
376 void MachineBasicBlock::moveAfter(MachineBasicBlock *NewBefore) {
377 MachineFunction::iterator BBI = NewBefore;
378 getParent()->splice(++BBI, this);
381 void MachineBasicBlock::updateTerminator() {
382 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
383 // A block with no successors has no concerns with fall-through edges.
384 if (this->succ_empty()) return;
386 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
387 SmallVector<MachineOperand, 4> Cond;
388 DebugLoc dl; // FIXME: this is nowhere
389 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
391 assert(!B && "UpdateTerminators requires analyzable predecessors!");
394 // The block has an unconditional branch. If its successor is now
395 // its layout successor, delete the branch.
396 if (isLayoutSuccessor(TBB))
397 TII->RemoveBranch(*this);
399 // The block has an unconditional fallthrough. If its successor is not
400 // its layout successor, insert a branch. First we have to locate the
401 // only non-landing-pad successor, as that is the fallthrough block.
402 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
403 if ((*SI)->isLandingPad())
405 assert(!TBB && "Found more than one non-landing-pad successor!");
409 // If there is no non-landing-pad successor, the block has no
410 // fall-through edges to be concerned with.
414 // Finally update the unconditional successor to be reached via a branch
415 // if it would not be reached by fallthrough.
416 if (!isLayoutSuccessor(TBB))
417 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
421 // The block has a non-fallthrough conditional branch. If one of its
422 // successors is its layout successor, rewrite it to a fallthrough
423 // conditional branch.
424 if (isLayoutSuccessor(TBB)) {
425 if (TII->ReverseBranchCondition(Cond))
427 TII->RemoveBranch(*this);
428 TII->InsertBranch(*this, FBB, nullptr, Cond, dl);
429 } else if (isLayoutSuccessor(FBB)) {
430 TII->RemoveBranch(*this);
431 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
434 // Walk through the successors and find the successor which is not
435 // a landing pad and is not the conditional branch destination (in TBB)
436 // as the fallthrough successor.
437 MachineBasicBlock *FallthroughBB = nullptr;
438 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
439 if ((*SI)->isLandingPad() || *SI == TBB)
441 assert(!FallthroughBB && "Found more than one fallthrough successor.");
444 if (!FallthroughBB && canFallThrough()) {
445 // We fallthrough to the same basic block as the conditional jump
446 // targets. Remove the conditional jump, leaving unconditional
448 // FIXME: This does not seem like a reasonable pattern to support, but it
449 // has been seen in the wild coming out of degenerate ARM test cases.
450 TII->RemoveBranch(*this);
452 // Finally update the unconditional successor to be reached via a branch
453 // if it would not be reached by fallthrough.
454 if (!isLayoutSuccessor(TBB))
455 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
459 // The block has a fallthrough conditional branch.
460 if (isLayoutSuccessor(TBB)) {
461 if (TII->ReverseBranchCondition(Cond)) {
462 // We can't reverse the condition, add an unconditional branch.
464 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl);
467 TII->RemoveBranch(*this);
468 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl);
469 } else if (!isLayoutSuccessor(FallthroughBB)) {
470 TII->RemoveBranch(*this);
471 TII->InsertBranch(*this, TBB, FallthroughBB, Cond, dl);
477 void MachineBasicBlock::addSuccessor(MachineBasicBlock *succ, uint32_t weight) {
479 // If we see non-zero value for the first time it means we actually use Weight
480 // list, so we fill all Weights with 0's.
481 if (weight != 0 && Weights.empty())
482 Weights.resize(Successors.size());
484 if (weight != 0 || !Weights.empty())
485 Weights.push_back(weight);
487 Successors.push_back(succ);
488 succ->addPredecessor(this);
491 void MachineBasicBlock::removeSuccessor(MachineBasicBlock *succ) {
492 succ->removePredecessor(this);
493 succ_iterator I = std::find(Successors.begin(), Successors.end(), succ);
494 assert(I != Successors.end() && "Not a current successor!");
496 // If Weight list is empty it means we don't use it (disabled optimization).
497 if (!Weights.empty()) {
498 weight_iterator WI = getWeightIterator(I);
505 MachineBasicBlock::succ_iterator
506 MachineBasicBlock::removeSuccessor(succ_iterator I) {
507 assert(I != Successors.end() && "Not a current successor!");
509 // If Weight list is empty it means we don't use it (disabled optimization).
510 if (!Weights.empty()) {
511 weight_iterator WI = getWeightIterator(I);
515 (*I)->removePredecessor(this);
516 return Successors.erase(I);
519 void MachineBasicBlock::replaceSuccessor(MachineBasicBlock *Old,
520 MachineBasicBlock *New) {
524 succ_iterator E = succ_end();
525 succ_iterator NewI = E;
526 succ_iterator OldI = E;
527 for (succ_iterator I = succ_begin(); I != E; ++I) {
539 assert(OldI != E && "Old is not a successor of this block");
540 Old->removePredecessor(this);
542 // If New isn't already a successor, let it take Old's place.
544 New->addPredecessor(this);
549 // New is already a successor.
550 // Update its weight instead of adding a duplicate edge.
551 if (!Weights.empty()) {
552 weight_iterator OldWI = getWeightIterator(OldI);
553 *getWeightIterator(NewI) += *OldWI;
554 Weights.erase(OldWI);
556 Successors.erase(OldI);
559 void MachineBasicBlock::addPredecessor(MachineBasicBlock *pred) {
560 Predecessors.push_back(pred);
563 void MachineBasicBlock::removePredecessor(MachineBasicBlock *pred) {
564 pred_iterator I = std::find(Predecessors.begin(), Predecessors.end(), pred);
565 assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
566 Predecessors.erase(I);
569 void MachineBasicBlock::transferSuccessors(MachineBasicBlock *fromMBB) {
573 while (!fromMBB->succ_empty()) {
574 MachineBasicBlock *Succ = *fromMBB->succ_begin();
577 // If Weight list is empty it means we don't use it (disabled optimization).
578 if (!fromMBB->Weights.empty())
579 Weight = *fromMBB->Weights.begin();
581 addSuccessor(Succ, Weight);
582 fromMBB->removeSuccessor(Succ);
587 MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB) {
591 while (!fromMBB->succ_empty()) {
592 MachineBasicBlock *Succ = *fromMBB->succ_begin();
594 if (!fromMBB->Weights.empty())
595 Weight = *fromMBB->Weights.begin();
596 addSuccessor(Succ, Weight);
597 fromMBB->removeSuccessor(Succ);
599 // Fix up any PHI nodes in the successor.
600 for (MachineBasicBlock::instr_iterator MI = Succ->instr_begin(),
601 ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI)
602 for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
603 MachineOperand &MO = MI->getOperand(i);
604 if (MO.getMBB() == fromMBB)
610 bool MachineBasicBlock::isPredecessor(const MachineBasicBlock *MBB) const {
611 return std::find(pred_begin(), pred_end(), MBB) != pred_end();
614 bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const {
615 return std::find(succ_begin(), succ_end(), MBB) != succ_end();
618 bool MachineBasicBlock::isLayoutSuccessor(const MachineBasicBlock *MBB) const {
619 MachineFunction::const_iterator I(this);
620 return std::next(I) == MachineFunction::const_iterator(MBB);
623 bool MachineBasicBlock::canFallThrough() {
624 MachineFunction::iterator Fallthrough = this;
626 // If FallthroughBlock is off the end of the function, it can't fall through.
627 if (Fallthrough == getParent()->end())
630 // If FallthroughBlock isn't a successor, no fallthrough is possible.
631 if (!isSuccessor(Fallthrough))
634 // Analyze the branches, if any, at the end of the block.
635 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
636 SmallVector<MachineOperand, 4> Cond;
637 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
638 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) {
639 // If we couldn't analyze the branch, examine the last instruction.
640 // If the block doesn't end in a known control barrier, assume fallthrough
641 // is possible. The isPredicated check is needed because this code can be
642 // called during IfConversion, where an instruction which is normally a
643 // Barrier is predicated and thus no longer an actual control barrier.
644 return empty() || !back().isBarrier() || TII->isPredicated(&back());
647 // If there is no branch, control always falls through.
648 if (!TBB) return true;
650 // If there is some explicit branch to the fallthrough block, it can obviously
651 // reach, even though the branch should get folded to fall through implicitly.
652 if (MachineFunction::iterator(TBB) == Fallthrough ||
653 MachineFunction::iterator(FBB) == Fallthrough)
656 // If it's an unconditional branch to some block not the fall through, it
657 // doesn't fall through.
658 if (Cond.empty()) return false;
660 // Otherwise, if it is conditional and has no explicit false block, it falls
662 return FBB == nullptr;
666 MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) {
667 // Splitting the critical edge to a landing pad block is non-trivial. Don't do
668 // it in this generic function.
669 if (Succ->isLandingPad())
672 MachineFunction *MF = getParent();
673 DebugLoc dl; // FIXME: this is nowhere
675 // Performance might be harmed on HW that implements branching using exec mask
676 // where both sides of the branches are always executed.
677 if (MF->getTarget().requiresStructuredCFG())
680 // We may need to update this's terminator, but we can't do that if
681 // AnalyzeBranch fails. If this uses a jump table, we won't touch it.
682 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
683 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
684 SmallVector<MachineOperand, 4> Cond;
685 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond))
688 // Avoid bugpoint weirdness: A block may end with a conditional branch but
689 // jumps to the same MBB is either case. We have duplicate CFG edges in that
690 // case that we can't handle. Since this never happens in properly optimized
691 // code, just skip those edges.
692 if (TBB && TBB == FBB) {
693 DEBUG(dbgs() << "Won't split critical edge after degenerate BB#"
694 << getNumber() << '\n');
698 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
699 MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
700 DEBUG(dbgs() << "Splitting critical edge:"
701 " BB#" << getNumber()
702 << " -- BB#" << NMBB->getNumber()
703 << " -- BB#" << Succ->getNumber() << '\n');
705 LiveIntervals *LIS = P->getAnalysisIfAvailable<LiveIntervals>();
706 SlotIndexes *Indexes = P->getAnalysisIfAvailable<SlotIndexes>();
708 LIS->insertMBBInMaps(NMBB);
710 Indexes->insertMBBInMaps(NMBB);
712 // On some targets like Mips, branches may kill virtual registers. Make sure
713 // that LiveVariables is properly updated after updateTerminator replaces the
715 LiveVariables *LV = P->getAnalysisIfAvailable<LiveVariables>();
717 // Collect a list of virtual registers killed by the terminators.
718 SmallVector<unsigned, 4> KilledRegs;
720 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
722 MachineInstr *MI = I;
723 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
724 OE = MI->operands_end(); OI != OE; ++OI) {
725 if (!OI->isReg() || OI->getReg() == 0 ||
726 !OI->isUse() || !OI->isKill() || OI->isUndef())
728 unsigned Reg = OI->getReg();
729 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
730 LV->getVarInfo(Reg).removeKill(MI)) {
731 KilledRegs.push_back(Reg);
732 DEBUG(dbgs() << "Removing terminator kill: " << *MI);
733 OI->setIsKill(false);
738 SmallVector<unsigned, 4> UsedRegs;
740 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
742 MachineInstr *MI = I;
744 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
745 OE = MI->operands_end(); OI != OE; ++OI) {
746 if (!OI->isReg() || OI->getReg() == 0)
749 unsigned Reg = OI->getReg();
750 if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end())
751 UsedRegs.push_back(Reg);
756 ReplaceUsesOfBlockWith(Succ, NMBB);
758 // If updateTerminator() removes instructions, we need to remove them from
760 SmallVector<MachineInstr*, 4> Terminators;
762 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
764 Terminators.push_back(I);
770 SmallVector<MachineInstr*, 4> NewTerminators;
771 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
773 NewTerminators.push_back(I);
775 for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(),
776 E = Terminators.end(); I != E; ++I) {
777 if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) ==
778 NewTerminators.end())
779 Indexes->removeMachineInstrFromMaps(*I);
783 // Insert unconditional "jump Succ" instruction in NMBB if necessary.
784 NMBB->addSuccessor(Succ);
785 if (!NMBB->isLayoutSuccessor(Succ)) {
787 MF->getSubtarget().getInstrInfo()->InsertBranch(*NMBB, Succ, nullptr, Cond,
791 for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end();
793 // Some instructions may have been moved to NMBB by updateTerminator(),
794 // so we first remove any instruction that already has an index.
795 if (Indexes->hasIndex(I))
796 Indexes->removeMachineInstrFromMaps(I);
797 Indexes->insertMachineInstrInMaps(I);
802 // Fix PHI nodes in Succ so they refer to NMBB instead of this
803 for (MachineBasicBlock::instr_iterator
804 i = Succ->instr_begin(),e = Succ->instr_end();
805 i != e && i->isPHI(); ++i)
806 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
807 if (i->getOperand(ni+1).getMBB() == this)
808 i->getOperand(ni+1).setMBB(NMBB);
810 // Inherit live-ins from the successor
811 for (MachineBasicBlock::livein_iterator I = Succ->livein_begin(),
812 E = Succ->livein_end(); I != E; ++I)
815 // Update LiveVariables.
816 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
818 // Restore kills of virtual registers that were killed by the terminators.
819 while (!KilledRegs.empty()) {
820 unsigned Reg = KilledRegs.pop_back_val();
821 for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
822 if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false))
824 if (TargetRegisterInfo::isVirtualRegister(Reg))
825 LV->getVarInfo(Reg).Kills.push_back(I);
826 DEBUG(dbgs() << "Restored terminator kill: " << *I);
830 // Update relevant live-through information.
831 LV->addNewBlock(NMBB, this, Succ);
835 // After splitting the edge and updating SlotIndexes, live intervals may be
836 // in one of two situations, depending on whether this block was the last in
837 // the function. If the original block was the last in the function, all live
838 // intervals will end prior to the beginning of the new split block. If the
839 // original block was not at the end of the function, all live intervals will
840 // extend to the end of the new split block.
843 std::next(MachineFunction::iterator(NMBB)) == getParent()->end();
845 SlotIndex StartIndex = Indexes->getMBBEndIdx(this);
846 SlotIndex PrevIndex = StartIndex.getPrevSlot();
847 SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);
849 // Find the registers used from NMBB in PHIs in Succ.
850 SmallSet<unsigned, 8> PHISrcRegs;
851 for (MachineBasicBlock::instr_iterator
852 I = Succ->instr_begin(), E = Succ->instr_end();
853 I != E && I->isPHI(); ++I) {
854 for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
855 if (I->getOperand(ni+1).getMBB() == NMBB) {
856 MachineOperand &MO = I->getOperand(ni);
857 unsigned Reg = MO.getReg();
858 PHISrcRegs.insert(Reg);
862 LiveInterval &LI = LIS->getInterval(Reg);
863 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
864 assert(VNI && "PHI sources should be live out of their predecessors.");
865 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
870 MachineRegisterInfo *MRI = &getParent()->getRegInfo();
871 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
872 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
873 if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg))
876 LiveInterval &LI = LIS->getInterval(Reg);
877 if (!LI.liveAt(PrevIndex))
880 bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ));
881 if (isLiveOut && isLastMBB) {
882 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
883 assert(VNI && "LiveInterval should have VNInfo where it is live.");
884 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
885 } else if (!isLiveOut && !isLastMBB) {
886 LI.removeSegment(StartIndex, EndIndex);
890 // Update all intervals for registers whose uses may have been modified by
891 // updateTerminator().
892 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs);
895 if (MachineDominatorTree *MDT =
896 P->getAnalysisIfAvailable<MachineDominatorTree>())
897 MDT->recordSplitCriticalEdge(this, Succ, NMBB);
899 if (MachineLoopInfo *MLI = P->getAnalysisIfAvailable<MachineLoopInfo>())
900 if (MachineLoop *TIL = MLI->getLoopFor(this)) {
901 // If one or the other blocks were not in a loop, the new block is not
902 // either, and thus LI doesn't need to be updated.
903 if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) {
904 if (TIL == DestLoop) {
905 // Both in the same loop, the NMBB joins loop.
906 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
907 } else if (TIL->contains(DestLoop)) {
908 // Edge from an outer loop to an inner loop. Add to the outer loop.
909 TIL->addBasicBlockToLoop(NMBB, MLI->getBase());
910 } else if (DestLoop->contains(TIL)) {
911 // Edge from an inner loop to an outer loop. Add to the outer loop.
912 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
914 // Edge from two loops with no containment relation. Because these
915 // are natural loops, we know that the destination block must be the
916 // header of its loop (adding a branch into a loop elsewhere would
917 // create an irreducible loop).
918 assert(DestLoop->getHeader() == Succ &&
919 "Should not create irreducible loops!");
920 if (MachineLoop *P = DestLoop->getParentLoop())
921 P->addBasicBlockToLoop(NMBB, MLI->getBase());
929 /// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
930 /// neighboring instructions so the bundle won't be broken by removing MI.
931 static void unbundleSingleMI(MachineInstr *MI) {
932 // Removing the first instruction in a bundle.
933 if (MI->isBundledWithSucc() && !MI->isBundledWithPred())
934 MI->unbundleFromSucc();
935 // Removing the last instruction in a bundle.
936 if (MI->isBundledWithPred() && !MI->isBundledWithSucc())
937 MI->unbundleFromPred();
938 // If MI is not bundled, or if it is internal to a bundle, the neighbor flags
942 MachineBasicBlock::instr_iterator
943 MachineBasicBlock::erase(MachineBasicBlock::instr_iterator I) {
945 return Insts.erase(I);
948 MachineInstr *MachineBasicBlock::remove_instr(MachineInstr *MI) {
949 unbundleSingleMI(MI);
950 MI->clearFlag(MachineInstr::BundledPred);
951 MI->clearFlag(MachineInstr::BundledSucc);
952 return Insts.remove(MI);
955 MachineBasicBlock::instr_iterator
956 MachineBasicBlock::insert(instr_iterator I, MachineInstr *MI) {
957 assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() &&
958 "Cannot insert instruction with bundle flags");
959 // Set the bundle flags when inserting inside a bundle.
960 if (I != instr_end() && I->isBundledWithPred()) {
961 MI->setFlag(MachineInstr::BundledPred);
962 MI->setFlag(MachineInstr::BundledSucc);
964 return Insts.insert(I, MI);
967 /// removeFromParent - This method unlinks 'this' from the containing function,
968 /// and returns it, but does not delete it.
969 MachineBasicBlock *MachineBasicBlock::removeFromParent() {
970 assert(getParent() && "Not embedded in a function!");
971 getParent()->remove(this);
976 /// eraseFromParent - This method unlinks 'this' from the containing function,
978 void MachineBasicBlock::eraseFromParent() {
979 assert(getParent() && "Not embedded in a function!");
980 getParent()->erase(this);
984 /// ReplaceUsesOfBlockWith - Given a machine basic block that branched to
985 /// 'Old', change the code and CFG so that it branches to 'New' instead.
986 void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
987 MachineBasicBlock *New) {
988 assert(Old != New && "Cannot replace self with self!");
990 MachineBasicBlock::instr_iterator I = instr_end();
991 while (I != instr_begin()) {
993 if (!I->isTerminator()) break;
995 // Scan the operands of this machine instruction, replacing any uses of Old
997 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
998 if (I->getOperand(i).isMBB() &&
999 I->getOperand(i).getMBB() == Old)
1000 I->getOperand(i).setMBB(New);
1003 // Update the successor information.
1004 replaceSuccessor(Old, New);
1007 /// CorrectExtraCFGEdges - Various pieces of code can cause excess edges in the
1008 /// CFG to be inserted. If we have proven that MBB can only branch to DestA and
1009 /// DestB, remove any other MBB successors from the CFG. DestA and DestB can be
1012 /// Besides DestA and DestB, retain other edges leading to LandingPads
1013 /// (currently there can be only one; we don't check or require that here).
1014 /// Note it is possible that DestA and/or DestB are LandingPads.
1015 bool MachineBasicBlock::CorrectExtraCFGEdges(MachineBasicBlock *DestA,
1016 MachineBasicBlock *DestB,
1018 // The values of DestA and DestB frequently come from a call to the
1019 // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial
1020 // values from there.
1022 // 1. If both DestA and DestB are null, then the block ends with no branches
1023 // (it falls through to its successor).
1024 // 2. If DestA is set, DestB is null, and isCond is false, then the block ends
1025 // with only an unconditional branch.
1026 // 3. If DestA is set, DestB is null, and isCond is true, then the block ends
1027 // with a conditional branch that falls through to a successor (DestB).
1028 // 4. If DestA and DestB is set and isCond is true, then the block ends with a
1029 // conditional branch followed by an unconditional branch. DestA is the
1030 // 'true' destination and DestB is the 'false' destination.
1032 bool Changed = false;
1034 MachineFunction::iterator FallThru =
1035 std::next(MachineFunction::iterator(this));
1037 if (!DestA && !DestB) {
1038 // Block falls through to successor.
1041 } else if (DestA && !DestB) {
1043 // Block ends in conditional jump that falls through to successor.
1046 assert(DestA && DestB && isCond &&
1047 "CFG in a bad state. Cannot correct CFG edges");
1050 // Remove superfluous edges. I.e., those which aren't destinations of this
1051 // basic block, duplicate edges, or landing pads.
1052 SmallPtrSet<const MachineBasicBlock*, 8> SeenMBBs;
1053 MachineBasicBlock::succ_iterator SI = succ_begin();
1054 while (SI != succ_end()) {
1055 const MachineBasicBlock *MBB = *SI;
1056 if (!SeenMBBs.insert(MBB).second ||
1057 (MBB != DestA && MBB != DestB && !MBB->isLandingPad())) {
1058 // This is a superfluous edge, remove it.
1059 SI = removeSuccessor(SI);
1069 /// findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping
1070 /// any DBG_VALUE instructions. Return UnknownLoc if there is none.
1072 MachineBasicBlock::findDebugLoc(instr_iterator MBBI) {
1074 instr_iterator E = instr_end();
1078 // Skip debug declarations, we don't want a DebugLoc from them.
1079 while (MBBI != E && MBBI->isDebugValue())
1082 DL = MBBI->getDebugLoc();
1086 /// getSuccWeight - Return weight of the edge from this block to MBB.
1088 uint32_t MachineBasicBlock::getSuccWeight(const_succ_iterator Succ) const {
1089 if (Weights.empty())
1092 return *getWeightIterator(Succ);
1095 /// Set successor weight of a given iterator.
1096 void MachineBasicBlock::setSuccWeight(succ_iterator I, uint32_t weight) {
1097 if (Weights.empty())
1099 *getWeightIterator(I) = weight;
1102 /// getWeightIterator - Return wight iterator corresonding to the I successor
1104 MachineBasicBlock::weight_iterator MachineBasicBlock::
1105 getWeightIterator(MachineBasicBlock::succ_iterator I) {
1106 assert(Weights.size() == Successors.size() && "Async weight list!");
1107 size_t index = std::distance(Successors.begin(), I);
1108 assert(index < Weights.size() && "Not a current successor!");
1109 return Weights.begin() + index;
1112 /// getWeightIterator - Return wight iterator corresonding to the I successor
1114 MachineBasicBlock::const_weight_iterator MachineBasicBlock::
1115 getWeightIterator(MachineBasicBlock::const_succ_iterator I) const {
1116 assert(Weights.size() == Successors.size() && "Async weight list!");
1117 const size_t index = std::distance(Successors.begin(), I);
1118 assert(index < Weights.size() && "Not a current successor!");
1119 return Weights.begin() + index;
1122 /// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
1123 /// as of just before "MI".
1125 /// Search is localised to a neighborhood of
1126 /// Neighborhood instructions before (searching for defs or kills) and N
1127 /// instructions after (searching just for defs) MI.
1128 MachineBasicBlock::LivenessQueryResult
1129 MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
1130 unsigned Reg, const_iterator Before,
1131 unsigned Neighborhood) const {
1132 unsigned N = Neighborhood;
1134 // Start by searching backwards from Before, looking for kills, reads or defs.
1135 const_iterator I(Before);
1136 // If this is the first insn in the block, don't search backwards.
1141 MachineOperandIteratorBase::PhysRegInfo Analysis =
1142 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1144 if (Analysis.Defines)
1145 // Outputs happen after inputs so they take precedence if both are
1147 return Analysis.DefinesDead ? LQR_Dead : LQR_Live;
1149 if (Analysis.Kills || Analysis.Clobbers)
1150 // Register killed, so isn't live.
1153 else if (Analysis.ReadsOverlap)
1154 // Defined or read without a previous kill - live.
1155 return Analysis.Reads ? LQR_Live : LQR_OverlappingLive;
1157 } while (I != begin() && --N > 0);
1160 // Did we get to the start of the block?
1162 // If so, the register's state is definitely defined by the live-in state.
1163 for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true);
1164 RAI.isValid(); ++RAI) {
1166 return (*RAI == Reg) ? LQR_Live : LQR_OverlappingLive;
1174 // Try searching forwards from Before, looking for reads or defs.
1175 I = const_iterator(Before);
1176 // If this is the last insn in the block, don't search forwards.
1178 for (++I; I != end() && N > 0; ++I, --N) {
1179 MachineOperandIteratorBase::PhysRegInfo Analysis =
1180 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1182 if (Analysis.ReadsOverlap)
1183 // Used, therefore must have been live.
1184 return (Analysis.Reads) ?
1185 LQR_Live : LQR_OverlappingLive;
1187 else if (Analysis.Clobbers || Analysis.Defines)
1188 // Defined (but not read) therefore cannot have been live.
1193 // At this point we have no idea of the liveness of the register.