1 //===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Collect the sequence of machine instructions for a basic block.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineBasicBlock.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallString.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "llvm/CodeGen/LiveVariables.h"
19 #include "llvm/CodeGen/MachineDominators.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SlotIndexes.h"
25 #include "llvm/IR/BasicBlock.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/ModuleSlotTracker.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Target/TargetSubtargetInfo.h"
39 #define DEBUG_TYPE "codegen"
41 MachineBasicBlock::MachineBasicBlock(MachineFunction &mf, const BasicBlock *bb)
42 : BB(bb), Number(-1), xParent(&mf) {
46 MachineBasicBlock::~MachineBasicBlock() {
49 /// Return the MCSymbol for this basic block.
50 MCSymbol *MachineBasicBlock::getSymbol() const {
51 if (!CachedMCSymbol) {
52 const MachineFunction *MF = getParent();
53 MCContext &Ctx = MF->getContext();
54 const char *Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
55 CachedMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB" +
56 Twine(MF->getFunctionNumber()) +
57 "_" + Twine(getNumber()));
60 return CachedMCSymbol;
64 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) {
69 /// When an MBB is added to an MF, we need to update the parent pointer of the
70 /// MBB, the MBB numbering, and any instructions in the MBB to be on the right
71 /// operand list for registers.
73 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
74 /// gets the next available unique MBB number. If it is removed from a
75 /// MachineFunction, it goes back to being #-1.
76 void ilist_traits<MachineBasicBlock>::addNodeToList(MachineBasicBlock *N) {
77 MachineFunction &MF = *N->getParent();
78 N->Number = MF.addToMBBNumbering(N);
80 // Make sure the instructions have their operands in the reginfo lists.
81 MachineRegisterInfo &RegInfo = MF.getRegInfo();
82 for (MachineBasicBlock::instr_iterator
83 I = N->instr_begin(), E = N->instr_end(); I != E; ++I)
84 I->AddRegOperandsToUseLists(RegInfo);
87 void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock *N) {
88 N->getParent()->removeFromMBBNumbering(N->Number);
92 /// When we add an instruction to a basic block list, we update its parent
93 /// pointer and add its operands from reg use/def lists if appropriate.
94 void ilist_traits<MachineInstr>::addNodeToList(MachineInstr *N) {
95 assert(!N->getParent() && "machine instruction already in a basic block");
98 // Add the instruction's register operands to their corresponding
100 MachineFunction *MF = Parent->getParent();
101 N->AddRegOperandsToUseLists(MF->getRegInfo());
104 /// When we remove an instruction from a basic block list, we update its parent
105 /// pointer and remove its operands from reg use/def lists if appropriate.
106 void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr *N) {
107 assert(N->getParent() && "machine instruction not in a basic block");
109 // Remove from the use/def lists.
110 if (MachineFunction *MF = N->getParent()->getParent())
111 N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
113 N->setParent(nullptr);
116 /// When moving a range of instructions from one MBB list to another, we need to
117 /// update the parent pointers and the use/def lists.
118 void ilist_traits<MachineInstr>::
119 transferNodesFromList(ilist_traits<MachineInstr> &fromList,
120 ilist_iterator<MachineInstr> first,
121 ilist_iterator<MachineInstr> last) {
122 assert(Parent->getParent() == fromList.Parent->getParent() &&
123 "MachineInstr parent mismatch!");
125 // Splice within the same MBB -> no change.
126 if (Parent == fromList.Parent) return;
128 // If splicing between two blocks within the same function, just update the
130 for (; first != last; ++first)
131 first->setParent(Parent);
134 void ilist_traits<MachineInstr>::deleteNode(MachineInstr* MI) {
135 assert(!MI->getParent() && "MI is still in a block!");
136 Parent->getParent()->DeleteMachineInstr(MI);
139 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() {
140 instr_iterator I = instr_begin(), E = instr_end();
141 while (I != E && I->isPHI())
143 assert((I == E || !I->isInsideBundle()) &&
144 "First non-phi MI cannot be inside a bundle!");
148 MachineBasicBlock::iterator
149 MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) {
151 while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue()))
153 // FIXME: This needs to change if we wish to bundle labels / dbg_values
154 // inside the bundle.
155 assert((I == E || !I->isInsideBundle()) &&
156 "First non-phi / non-label instruction is inside a bundle!");
160 MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
161 iterator B = begin(), E = end(), I = E;
162 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
164 while (I != E && !I->isTerminator())
169 MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() {
170 instr_iterator B = instr_begin(), E = instr_end(), I = E;
171 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
173 while (I != E && !I->isTerminator())
178 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonDebugInstr() {
179 // Skip over begin-of-block dbg_value instructions.
180 iterator I = begin(), E = end();
181 while (I != E && I->isDebugValue())
186 MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() {
187 // Skip over end-of-block dbg_value instructions.
188 instr_iterator B = instr_begin(), I = instr_end();
191 // Return instruction that starts a bundle.
192 if (I->isDebugValue() || I->isInsideBundle())
196 // The block is all debug values.
200 const MachineBasicBlock *MachineBasicBlock::getLandingPadSuccessor() const {
201 // A block with a landing pad successor only has one other successor.
204 for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
210 bool MachineBasicBlock::hasEHPadSuccessor() const {
211 for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
217 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
218 void MachineBasicBlock::dump() const {
223 StringRef MachineBasicBlock::getName() const {
224 if (const BasicBlock *LBB = getBasicBlock())
225 return LBB->getName();
230 /// Return a hopefully unique identifier for this block.
231 std::string MachineBasicBlock::getFullName() const {
234 Name = (getParent()->getName() + ":").str();
236 Name += getBasicBlock()->getName();
238 Name += ("BB" + Twine(getNumber())).str();
242 void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const {
243 const MachineFunction *MF = getParent();
245 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
249 const Function *F = MF->getFunction();
250 const Module *M = F ? F->getParent() : nullptr;
251 ModuleSlotTracker MST(M);
252 print(OS, MST, Indexes);
255 void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
256 SlotIndexes *Indexes) const {
257 const MachineFunction *MF = getParent();
259 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
265 OS << Indexes->getMBBStartIdx(this) << '\t';
267 OS << "BB#" << getNumber() << ": ";
269 const char *Comma = "";
270 if (const BasicBlock *LBB = getBasicBlock()) {
271 OS << Comma << "derived from LLVM BB ";
272 LBB->printAsOperand(OS, /*PrintType=*/false, MST);
275 if (isEHPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; }
276 if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; }
278 OS << Comma << "Align " << Alignment << " (" << (1u << Alignment)
283 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
284 if (!livein_empty()) {
285 if (Indexes) OS << '\t';
287 for (const auto &LI : make_range(livein_begin(), livein_end())) {
288 OS << ' ' << PrintReg(LI.PhysReg, TRI);
289 if (LI.LaneMask != ~0u)
290 OS << ':' << PrintLaneMask(LI.LaneMask);
294 // Print the preds of this block according to the CFG.
296 if (Indexes) OS << '\t';
297 OS << " Predecessors according to CFG:";
298 for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
299 OS << " BB#" << (*PI)->getNumber();
303 for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) {
305 if (Indexes->hasIndex(I))
306 OS << Indexes->getInstructionIndex(I);
310 if (I->isInsideBundle())
315 // Print the successors of this block according to the CFG.
317 if (Indexes) OS << '\t';
318 OS << " Successors according to CFG:";
319 for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) {
320 OS << " BB#" << (*SI)->getNumber();
321 if (!Weights.empty())
322 OS << '(' << *getWeightIterator(SI) << ')';
328 void MachineBasicBlock::printAsOperand(raw_ostream &OS,
329 bool /*PrintType*/) const {
330 OS << "BB#" << getNumber();
333 void MachineBasicBlock::removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) {
334 LiveInVector::iterator I = std::find_if(
335 LiveIns.begin(), LiveIns.end(),
336 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
337 if (I == LiveIns.end())
340 I->LaneMask &= ~LaneMask;
341 if (I->LaneMask == 0)
345 bool MachineBasicBlock::isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) const {
346 livein_iterator I = std::find_if(
347 LiveIns.begin(), LiveIns.end(),
348 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
349 return I != livein_end() && (I->LaneMask & LaneMask) != 0;
352 void MachineBasicBlock::sortUniqueLiveIns() {
353 std::sort(LiveIns.begin(), LiveIns.end(),
354 [](const RegisterMaskPair &LI0, const RegisterMaskPair &LI1) {
355 return LI0.PhysReg < LI1.PhysReg;
357 // Liveins are sorted by physreg now we can merge their lanemasks.
358 LiveInVector::const_iterator I = LiveIns.begin();
359 LiveInVector::const_iterator J;
360 LiveInVector::iterator Out = LiveIns.begin();
361 for (; I != LiveIns.end(); ++Out, I = J) {
362 unsigned PhysReg = I->PhysReg;
363 LaneBitmask LaneMask = I->LaneMask;
364 for (J = std::next(I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J)
365 LaneMask |= J->LaneMask;
366 Out->PhysReg = PhysReg;
367 Out->LaneMask = LaneMask;
369 LiveIns.erase(Out, LiveIns.end());
373 MachineBasicBlock::addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC) {
374 assert(getParent() && "MBB must be inserted in function");
375 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg");
376 assert(RC && "Register class is required");
377 assert((isEHPad() || this == &getParent()->front()) &&
378 "Only the entry block and landing pads can have physreg live ins");
380 bool LiveIn = isLiveIn(PhysReg);
381 iterator I = SkipPHIsAndLabels(begin()), E = end();
382 MachineRegisterInfo &MRI = getParent()->getRegInfo();
383 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
385 // Look for an existing copy.
387 for (;I != E && I->isCopy(); ++I)
388 if (I->getOperand(1).getReg() == PhysReg) {
389 unsigned VirtReg = I->getOperand(0).getReg();
390 if (!MRI.constrainRegClass(VirtReg, RC))
391 llvm_unreachable("Incompatible live-in register class.");
395 // No luck, create a virtual register.
396 unsigned VirtReg = MRI.createVirtualRegister(RC);
397 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
398 .addReg(PhysReg, RegState::Kill);
404 void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
405 getParent()->splice(NewAfter, this);
408 void MachineBasicBlock::moveAfter(MachineBasicBlock *NewBefore) {
409 MachineFunction::iterator BBI = NewBefore;
410 getParent()->splice(++BBI, this);
413 void MachineBasicBlock::updateTerminator() {
414 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
415 // A block with no successors has no concerns with fall-through edges.
416 if (this->succ_empty()) return;
418 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
419 SmallVector<MachineOperand, 4> Cond;
420 DebugLoc dl; // FIXME: this is nowhere
421 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
423 assert(!B && "UpdateTerminators requires analyzable predecessors!");
426 // The block has an unconditional branch. If its successor is now
427 // its layout successor, delete the branch.
428 if (isLayoutSuccessor(TBB))
429 TII->RemoveBranch(*this);
431 // The block has an unconditional fallthrough. If its successor is not
432 // its layout successor, insert a branch. First we have to locate the
433 // only non-landing-pad successor, as that is the fallthrough block.
434 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
435 if ((*SI)->isEHPad())
437 assert(!TBB && "Found more than one non-landing-pad successor!");
441 // If there is no non-landing-pad successor, the block has no
442 // fall-through edges to be concerned with.
446 // Finally update the unconditional successor to be reached via a branch
447 // if it would not be reached by fallthrough.
448 if (!isLayoutSuccessor(TBB))
449 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
453 // The block has a non-fallthrough conditional branch. If one of its
454 // successors is its layout successor, rewrite it to a fallthrough
455 // conditional branch.
456 if (isLayoutSuccessor(TBB)) {
457 if (TII->ReverseBranchCondition(Cond))
459 TII->RemoveBranch(*this);
460 TII->InsertBranch(*this, FBB, nullptr, Cond, dl);
461 } else if (isLayoutSuccessor(FBB)) {
462 TII->RemoveBranch(*this);
463 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
466 // Walk through the successors and find the successor which is not
467 // a landing pad and is not the conditional branch destination (in TBB)
468 // as the fallthrough successor.
469 MachineBasicBlock *FallthroughBB = nullptr;
470 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
471 if ((*SI)->isEHPad() || *SI == TBB)
473 assert(!FallthroughBB && "Found more than one fallthrough successor.");
476 if (!FallthroughBB && canFallThrough()) {
477 // We fallthrough to the same basic block as the conditional jump
478 // targets. Remove the conditional jump, leaving unconditional
480 // FIXME: This does not seem like a reasonable pattern to support, but
481 // it has been seen in the wild coming out of degenerate ARM test cases.
482 TII->RemoveBranch(*this);
484 // Finally update the unconditional successor to be reached via a branch
485 // if it would not be reached by fallthrough.
486 if (!isLayoutSuccessor(TBB))
487 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
491 // The block has a fallthrough conditional branch.
492 if (isLayoutSuccessor(TBB)) {
493 if (TII->ReverseBranchCondition(Cond)) {
494 // We can't reverse the condition, add an unconditional branch.
496 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl);
499 TII->RemoveBranch(*this);
500 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl);
501 } else if (!isLayoutSuccessor(FallthroughBB)) {
502 TII->RemoveBranch(*this);
503 TII->InsertBranch(*this, TBB, FallthroughBB, Cond, dl);
509 void MachineBasicBlock::addSuccessor(MachineBasicBlock *succ, uint32_t weight) {
511 // If we see non-zero value for the first time it means we actually use Weight
512 // list, so we fill all Weights with 0's.
513 if (weight != 0 && Weights.empty())
514 Weights.resize(Successors.size());
516 if (weight != 0 || !Weights.empty())
517 Weights.push_back(weight);
519 Successors.push_back(succ);
520 succ->addPredecessor(this);
523 void MachineBasicBlock::removeSuccessor(MachineBasicBlock *succ) {
524 succ->removePredecessor(this);
525 succ_iterator I = std::find(Successors.begin(), Successors.end(), succ);
526 assert(I != Successors.end() && "Not a current successor!");
528 // If Weight list is empty it means we don't use it (disabled optimization).
529 if (!Weights.empty()) {
530 weight_iterator WI = getWeightIterator(I);
537 MachineBasicBlock::succ_iterator
538 MachineBasicBlock::removeSuccessor(succ_iterator I) {
539 assert(I != Successors.end() && "Not a current successor!");
541 // If Weight list is empty it means we don't use it (disabled optimization).
542 if (!Weights.empty()) {
543 weight_iterator WI = getWeightIterator(I);
547 (*I)->removePredecessor(this);
548 return Successors.erase(I);
551 void MachineBasicBlock::replaceSuccessor(MachineBasicBlock *Old,
552 MachineBasicBlock *New) {
556 succ_iterator E = succ_end();
557 succ_iterator NewI = E;
558 succ_iterator OldI = E;
559 for (succ_iterator I = succ_begin(); I != E; ++I) {
571 assert(OldI != E && "Old is not a successor of this block");
572 Old->removePredecessor(this);
574 // If New isn't already a successor, let it take Old's place.
576 New->addPredecessor(this);
581 // New is already a successor.
582 // Update its weight instead of adding a duplicate edge.
583 if (!Weights.empty()) {
584 weight_iterator OldWI = getWeightIterator(OldI);
585 *getWeightIterator(NewI) += *OldWI;
586 Weights.erase(OldWI);
588 Successors.erase(OldI);
591 void MachineBasicBlock::addPredecessor(MachineBasicBlock *pred) {
592 Predecessors.push_back(pred);
595 void MachineBasicBlock::removePredecessor(MachineBasicBlock *pred) {
596 pred_iterator I = std::find(Predecessors.begin(), Predecessors.end(), pred);
597 assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
598 Predecessors.erase(I);
601 void MachineBasicBlock::transferSuccessors(MachineBasicBlock *fromMBB) {
605 while (!fromMBB->succ_empty()) {
606 MachineBasicBlock *Succ = *fromMBB->succ_begin();
609 // If Weight list is empty it means we don't use it (disabled optimization).
610 if (!fromMBB->Weights.empty())
611 Weight = *fromMBB->Weights.begin();
613 addSuccessor(Succ, Weight);
614 fromMBB->removeSuccessor(Succ);
619 MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB) {
623 while (!fromMBB->succ_empty()) {
624 MachineBasicBlock *Succ = *fromMBB->succ_begin();
626 if (!fromMBB->Weights.empty())
627 Weight = *fromMBB->Weights.begin();
628 addSuccessor(Succ, Weight);
629 fromMBB->removeSuccessor(Succ);
631 // Fix up any PHI nodes in the successor.
632 for (MachineBasicBlock::instr_iterator MI = Succ->instr_begin(),
633 ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI)
634 for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
635 MachineOperand &MO = MI->getOperand(i);
636 if (MO.getMBB() == fromMBB)
642 bool MachineBasicBlock::isPredecessor(const MachineBasicBlock *MBB) const {
643 return std::find(pred_begin(), pred_end(), MBB) != pred_end();
646 bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const {
647 return std::find(succ_begin(), succ_end(), MBB) != succ_end();
650 bool MachineBasicBlock::isLayoutSuccessor(const MachineBasicBlock *MBB) const {
651 MachineFunction::const_iterator I(this);
652 return std::next(I) == MachineFunction::const_iterator(MBB);
655 bool MachineBasicBlock::canFallThrough() {
656 MachineFunction::iterator Fallthrough = this;
658 // If FallthroughBlock is off the end of the function, it can't fall through.
659 if (Fallthrough == getParent()->end())
662 // If FallthroughBlock isn't a successor, no fallthrough is possible.
663 if (!isSuccessor(Fallthrough))
666 // Analyze the branches, if any, at the end of the block.
667 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
668 SmallVector<MachineOperand, 4> Cond;
669 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
670 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) {
671 // If we couldn't analyze the branch, examine the last instruction.
672 // If the block doesn't end in a known control barrier, assume fallthrough
673 // is possible. The isPredicated check is needed because this code can be
674 // called during IfConversion, where an instruction which is normally a
675 // Barrier is predicated and thus no longer an actual control barrier.
676 return empty() || !back().isBarrier() || TII->isPredicated(&back());
679 // If there is no branch, control always falls through.
680 if (!TBB) return true;
682 // If there is some explicit branch to the fallthrough block, it can obviously
683 // reach, even though the branch should get folded to fall through implicitly.
684 if (MachineFunction::iterator(TBB) == Fallthrough ||
685 MachineFunction::iterator(FBB) == Fallthrough)
688 // If it's an unconditional branch to some block not the fall through, it
689 // doesn't fall through.
690 if (Cond.empty()) return false;
692 // Otherwise, if it is conditional and has no explicit false block, it falls
694 return FBB == nullptr;
698 MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) {
699 // Splitting the critical edge to a landing pad block is non-trivial. Don't do
700 // it in this generic function.
704 MachineFunction *MF = getParent();
705 DebugLoc dl; // FIXME: this is nowhere
707 // Performance might be harmed on HW that implements branching using exec mask
708 // where both sides of the branches are always executed.
709 if (MF->getTarget().requiresStructuredCFG())
712 // We may need to update this's terminator, but we can't do that if
713 // AnalyzeBranch fails. If this uses a jump table, we won't touch it.
714 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
715 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
716 SmallVector<MachineOperand, 4> Cond;
717 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond))
720 // Avoid bugpoint weirdness: A block may end with a conditional branch but
721 // jumps to the same MBB is either case. We have duplicate CFG edges in that
722 // case that we can't handle. Since this never happens in properly optimized
723 // code, just skip those edges.
724 if (TBB && TBB == FBB) {
725 DEBUG(dbgs() << "Won't split critical edge after degenerate BB#"
726 << getNumber() << '\n');
730 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
731 MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
732 DEBUG(dbgs() << "Splitting critical edge:"
733 " BB#" << getNumber()
734 << " -- BB#" << NMBB->getNumber()
735 << " -- BB#" << Succ->getNumber() << '\n');
737 LiveIntervals *LIS = P->getAnalysisIfAvailable<LiveIntervals>();
738 SlotIndexes *Indexes = P->getAnalysisIfAvailable<SlotIndexes>();
740 LIS->insertMBBInMaps(NMBB);
742 Indexes->insertMBBInMaps(NMBB);
744 // On some targets like Mips, branches may kill virtual registers. Make sure
745 // that LiveVariables is properly updated after updateTerminator replaces the
747 LiveVariables *LV = P->getAnalysisIfAvailable<LiveVariables>();
749 // Collect a list of virtual registers killed by the terminators.
750 SmallVector<unsigned, 4> KilledRegs;
752 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
754 MachineInstr *MI = I;
755 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
756 OE = MI->operands_end(); OI != OE; ++OI) {
757 if (!OI->isReg() || OI->getReg() == 0 ||
758 !OI->isUse() || !OI->isKill() || OI->isUndef())
760 unsigned Reg = OI->getReg();
761 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
762 LV->getVarInfo(Reg).removeKill(MI)) {
763 KilledRegs.push_back(Reg);
764 DEBUG(dbgs() << "Removing terminator kill: " << *MI);
765 OI->setIsKill(false);
770 SmallVector<unsigned, 4> UsedRegs;
772 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
774 MachineInstr *MI = I;
776 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
777 OE = MI->operands_end(); OI != OE; ++OI) {
778 if (!OI->isReg() || OI->getReg() == 0)
781 unsigned Reg = OI->getReg();
782 if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end())
783 UsedRegs.push_back(Reg);
788 ReplaceUsesOfBlockWith(Succ, NMBB);
790 // If updateTerminator() removes instructions, we need to remove them from
792 SmallVector<MachineInstr*, 4> Terminators;
794 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
796 Terminators.push_back(I);
802 SmallVector<MachineInstr*, 4> NewTerminators;
803 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
805 NewTerminators.push_back(I);
807 for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(),
808 E = Terminators.end(); I != E; ++I) {
809 if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) ==
810 NewTerminators.end())
811 Indexes->removeMachineInstrFromMaps(*I);
815 // Insert unconditional "jump Succ" instruction in NMBB if necessary.
816 NMBB->addSuccessor(Succ);
817 if (!NMBB->isLayoutSuccessor(Succ)) {
819 TII->InsertBranch(*NMBB, Succ, nullptr, Cond, dl);
822 for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end();
824 // Some instructions may have been moved to NMBB by updateTerminator(),
825 // so we first remove any instruction that already has an index.
826 if (Indexes->hasIndex(I))
827 Indexes->removeMachineInstrFromMaps(I);
828 Indexes->insertMachineInstrInMaps(I);
833 // Fix PHI nodes in Succ so they refer to NMBB instead of this
834 for (MachineBasicBlock::instr_iterator
835 i = Succ->instr_begin(),e = Succ->instr_end();
836 i != e && i->isPHI(); ++i)
837 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
838 if (i->getOperand(ni+1).getMBB() == this)
839 i->getOperand(ni+1).setMBB(NMBB);
841 // Inherit live-ins from the successor
842 for (const auto &LI : Succ->liveins())
845 // Update LiveVariables.
846 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
848 // Restore kills of virtual registers that were killed by the terminators.
849 while (!KilledRegs.empty()) {
850 unsigned Reg = KilledRegs.pop_back_val();
851 for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
852 if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false))
854 if (TargetRegisterInfo::isVirtualRegister(Reg))
855 LV->getVarInfo(Reg).Kills.push_back(I);
856 DEBUG(dbgs() << "Restored terminator kill: " << *I);
860 // Update relevant live-through information.
861 LV->addNewBlock(NMBB, this, Succ);
865 // After splitting the edge and updating SlotIndexes, live intervals may be
866 // in one of two situations, depending on whether this block was the last in
867 // the function. If the original block was the last in the function, all
868 // live intervals will end prior to the beginning of the new split block. If
869 // the original block was not at the end of the function, all live intervals
870 // will extend to the end of the new split block.
873 std::next(MachineFunction::iterator(NMBB)) == getParent()->end();
875 SlotIndex StartIndex = Indexes->getMBBEndIdx(this);
876 SlotIndex PrevIndex = StartIndex.getPrevSlot();
877 SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);
879 // Find the registers used from NMBB in PHIs in Succ.
880 SmallSet<unsigned, 8> PHISrcRegs;
881 for (MachineBasicBlock::instr_iterator
882 I = Succ->instr_begin(), E = Succ->instr_end();
883 I != E && I->isPHI(); ++I) {
884 for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
885 if (I->getOperand(ni+1).getMBB() == NMBB) {
886 MachineOperand &MO = I->getOperand(ni);
887 unsigned Reg = MO.getReg();
888 PHISrcRegs.insert(Reg);
892 LiveInterval &LI = LIS->getInterval(Reg);
893 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
895 "PHI sources should be live out of their predecessors.");
896 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
901 MachineRegisterInfo *MRI = &getParent()->getRegInfo();
902 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
903 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
904 if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg))
907 LiveInterval &LI = LIS->getInterval(Reg);
908 if (!LI.liveAt(PrevIndex))
911 bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ));
912 if (isLiveOut && isLastMBB) {
913 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
914 assert(VNI && "LiveInterval should have VNInfo where it is live.");
915 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
916 } else if (!isLiveOut && !isLastMBB) {
917 LI.removeSegment(StartIndex, EndIndex);
921 // Update all intervals for registers whose uses may have been modified by
922 // updateTerminator().
923 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs);
926 if (MachineDominatorTree *MDT =
927 P->getAnalysisIfAvailable<MachineDominatorTree>())
928 MDT->recordSplitCriticalEdge(this, Succ, NMBB);
930 if (MachineLoopInfo *MLI = P->getAnalysisIfAvailable<MachineLoopInfo>())
931 if (MachineLoop *TIL = MLI->getLoopFor(this)) {
932 // If one or the other blocks were not in a loop, the new block is not
933 // either, and thus LI doesn't need to be updated.
934 if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) {
935 if (TIL == DestLoop) {
936 // Both in the same loop, the NMBB joins loop.
937 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
938 } else if (TIL->contains(DestLoop)) {
939 // Edge from an outer loop to an inner loop. Add to the outer loop.
940 TIL->addBasicBlockToLoop(NMBB, MLI->getBase());
941 } else if (DestLoop->contains(TIL)) {
942 // Edge from an inner loop to an outer loop. Add to the outer loop.
943 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
945 // Edge from two loops with no containment relation. Because these
946 // are natural loops, we know that the destination block must be the
947 // header of its loop (adding a branch into a loop elsewhere would
948 // create an irreducible loop).
949 assert(DestLoop->getHeader() == Succ &&
950 "Should not create irreducible loops!");
951 if (MachineLoop *P = DestLoop->getParentLoop())
952 P->addBasicBlockToLoop(NMBB, MLI->getBase());
960 /// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
961 /// neighboring instructions so the bundle won't be broken by removing MI.
962 static void unbundleSingleMI(MachineInstr *MI) {
963 // Removing the first instruction in a bundle.
964 if (MI->isBundledWithSucc() && !MI->isBundledWithPred())
965 MI->unbundleFromSucc();
966 // Removing the last instruction in a bundle.
967 if (MI->isBundledWithPred() && !MI->isBundledWithSucc())
968 MI->unbundleFromPred();
969 // If MI is not bundled, or if it is internal to a bundle, the neighbor flags
973 MachineBasicBlock::instr_iterator
974 MachineBasicBlock::erase(MachineBasicBlock::instr_iterator I) {
976 return Insts.erase(I);
979 MachineInstr *MachineBasicBlock::remove_instr(MachineInstr *MI) {
980 unbundleSingleMI(MI);
981 MI->clearFlag(MachineInstr::BundledPred);
982 MI->clearFlag(MachineInstr::BundledSucc);
983 return Insts.remove(MI);
986 MachineBasicBlock::instr_iterator
987 MachineBasicBlock::insert(instr_iterator I, MachineInstr *MI) {
988 assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() &&
989 "Cannot insert instruction with bundle flags");
990 // Set the bundle flags when inserting inside a bundle.
991 if (I != instr_end() && I->isBundledWithPred()) {
992 MI->setFlag(MachineInstr::BundledPred);
993 MI->setFlag(MachineInstr::BundledSucc);
995 return Insts.insert(I, MI);
998 /// This method unlinks 'this' from the containing function, and returns it, but
999 /// does not delete it.
1000 MachineBasicBlock *MachineBasicBlock::removeFromParent() {
1001 assert(getParent() && "Not embedded in a function!");
1002 getParent()->remove(this);
1006 /// This method unlinks 'this' from the containing function, and deletes it.
1007 void MachineBasicBlock::eraseFromParent() {
1008 assert(getParent() && "Not embedded in a function!");
1009 getParent()->erase(this);
1012 /// Given a machine basic block that branched to 'Old', change the code and CFG
1013 /// so that it branches to 'New' instead.
1014 void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
1015 MachineBasicBlock *New) {
1016 assert(Old != New && "Cannot replace self with self!");
1018 MachineBasicBlock::instr_iterator I = instr_end();
1019 while (I != instr_begin()) {
1021 if (!I->isTerminator()) break;
1023 // Scan the operands of this machine instruction, replacing any uses of Old
1025 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1026 if (I->getOperand(i).isMBB() &&
1027 I->getOperand(i).getMBB() == Old)
1028 I->getOperand(i).setMBB(New);
1031 // Update the successor information.
1032 replaceSuccessor(Old, New);
1035 /// Various pieces of code can cause excess edges in the CFG to be inserted. If
1036 /// we have proven that MBB can only branch to DestA and DestB, remove any other
1037 /// MBB successors from the CFG. DestA and DestB can be null.
1039 /// Besides DestA and DestB, retain other edges leading to LandingPads
1040 /// (currently there can be only one; we don't check or require that here).
1041 /// Note it is possible that DestA and/or DestB are LandingPads.
1042 bool MachineBasicBlock::CorrectExtraCFGEdges(MachineBasicBlock *DestA,
1043 MachineBasicBlock *DestB,
1045 // The values of DestA and DestB frequently come from a call to the
1046 // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial
1047 // values from there.
1049 // 1. If both DestA and DestB are null, then the block ends with no branches
1050 // (it falls through to its successor).
1051 // 2. If DestA is set, DestB is null, and isCond is false, then the block ends
1052 // with only an unconditional branch.
1053 // 3. If DestA is set, DestB is null, and isCond is true, then the block ends
1054 // with a conditional branch that falls through to a successor (DestB).
1055 // 4. If DestA and DestB is set and isCond is true, then the block ends with a
1056 // conditional branch followed by an unconditional branch. DestA is the
1057 // 'true' destination and DestB is the 'false' destination.
1059 bool Changed = false;
1061 MachineFunction::iterator FallThru =
1062 std::next(MachineFunction::iterator(this));
1064 if (!DestA && !DestB) {
1065 // Block falls through to successor.
1068 } else if (DestA && !DestB) {
1070 // Block ends in conditional jump that falls through to successor.
1073 assert(DestA && DestB && isCond &&
1074 "CFG in a bad state. Cannot correct CFG edges");
1077 // Remove superfluous edges. I.e., those which aren't destinations of this
1078 // basic block, duplicate edges, or landing pads.
1079 SmallPtrSet<const MachineBasicBlock*, 8> SeenMBBs;
1080 MachineBasicBlock::succ_iterator SI = succ_begin();
1081 while (SI != succ_end()) {
1082 const MachineBasicBlock *MBB = *SI;
1083 if (!SeenMBBs.insert(MBB).second ||
1084 (MBB != DestA && MBB != DestB && !MBB->isEHPad())) {
1085 // This is a superfluous edge, remove it.
1086 SI = removeSuccessor(SI);
1096 /// Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE
1097 /// instructions. Return UnknownLoc if there is none.
1099 MachineBasicBlock::findDebugLoc(instr_iterator MBBI) {
1101 instr_iterator E = instr_end();
1105 // Skip debug declarations, we don't want a DebugLoc from them.
1106 while (MBBI != E && MBBI->isDebugValue())
1109 DL = MBBI->getDebugLoc();
1113 /// Return weight of the edge from this block to MBB.
1114 uint32_t MachineBasicBlock::getSuccWeight(const_succ_iterator Succ) const {
1115 if (Weights.empty())
1118 return *getWeightIterator(Succ);
1121 /// Set successor weight of a given iterator.
1122 void MachineBasicBlock::setSuccWeight(succ_iterator I, uint32_t weight) {
1123 if (Weights.empty())
1125 *getWeightIterator(I) = weight;
1128 /// Return wight iterator corresonding to the I successor iterator.
1129 MachineBasicBlock::weight_iterator MachineBasicBlock::
1130 getWeightIterator(MachineBasicBlock::succ_iterator I) {
1131 assert(Weights.size() == Successors.size() && "Async weight list!");
1132 size_t index = std::distance(Successors.begin(), I);
1133 assert(index < Weights.size() && "Not a current successor!");
1134 return Weights.begin() + index;
1137 /// Return wight iterator corresonding to the I successor iterator.
1138 MachineBasicBlock::const_weight_iterator MachineBasicBlock::
1139 getWeightIterator(MachineBasicBlock::const_succ_iterator I) const {
1140 assert(Weights.size() == Successors.size() && "Async weight list!");
1141 const size_t index = std::distance(Successors.begin(), I);
1142 assert(index < Weights.size() && "Not a current successor!");
1143 return Weights.begin() + index;
1146 /// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
1147 /// as of just before "MI".
1149 /// Search is localised to a neighborhood of
1150 /// Neighborhood instructions before (searching for defs or kills) and N
1151 /// instructions after (searching just for defs) MI.
1152 MachineBasicBlock::LivenessQueryResult
1153 MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
1154 unsigned Reg, const_iterator Before,
1155 unsigned Neighborhood) const {
1156 unsigned N = Neighborhood;
1158 // Start by searching backwards from Before, looking for kills, reads or defs.
1159 const_iterator I(Before);
1160 // If this is the first insn in the block, don't search backwards.
1165 MachineOperandIteratorBase::PhysRegInfo Analysis =
1166 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1168 if (Analysis.Defines)
1169 // Outputs happen after inputs so they take precedence if both are
1171 return Analysis.DefinesDead ? LQR_Dead : LQR_Live;
1173 if (Analysis.Kills || Analysis.Clobbers)
1174 // Register killed, so isn't live.
1177 else if (Analysis.ReadsOverlap)
1178 // Defined or read without a previous kill - live.
1179 return Analysis.Reads ? LQR_Live : LQR_OverlappingLive;
1181 } while (I != begin() && --N > 0);
1184 // Did we get to the start of the block?
1186 // If so, the register's state is definitely defined by the live-in state.
1187 for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true);
1188 RAI.isValid(); ++RAI) {
1190 return (*RAI == Reg) ? LQR_Live : LQR_OverlappingLive;
1198 // Try searching forwards from Before, looking for reads or defs.
1199 I = const_iterator(Before);
1200 // If this is the last insn in the block, don't search forwards.
1202 for (++I; I != end() && N > 0; ++I, --N) {
1203 MachineOperandIteratorBase::PhysRegInfo Analysis =
1204 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1206 if (Analysis.ReadsOverlap)
1207 // Used, therefore must have been live.
1208 return (Analysis.Reads) ?
1209 LQR_Live : LQR_OverlappingLive;
1211 else if (Analysis.Clobbers || Analysis.Defines)
1212 // Defined (but not read) therefore cannot have been live.
1217 // At this point we have no idea of the liveness of the register.