1 //===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Collect the sequence of machine instructions for a basic block.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineBasicBlock.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallString.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "llvm/CodeGen/LiveVariables.h"
19 #include "llvm/CodeGen/MachineDominators.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SlotIndexes.h"
25 #include "llvm/IR/BasicBlock.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/ModuleSlotTracker.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/Support/DataTypes.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetRegisterInfo.h"
36 #include "llvm/Target/TargetSubtargetInfo.h"
40 #define DEBUG_TYPE "codegen"
42 MachineBasicBlock::MachineBasicBlock(MachineFunction &MF, const BasicBlock *B)
43 : BB(B), Number(-1), xParent(&MF) {
47 MachineBasicBlock::~MachineBasicBlock() {
50 /// Return the MCSymbol for this basic block.
51 MCSymbol *MachineBasicBlock::getSymbol() const {
52 if (!CachedMCSymbol) {
53 const MachineFunction *MF = getParent();
54 MCContext &Ctx = MF->getContext();
55 const char *Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
56 assert(getNumber() >= 0 && "cannot get label for unreachable MBB");
57 CachedMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB" +
58 Twine(MF->getFunctionNumber()) +
59 "_" + Twine(getNumber()));
62 return CachedMCSymbol;
66 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) {
71 /// When an MBB is added to an MF, we need to update the parent pointer of the
72 /// MBB, the MBB numbering, and any instructions in the MBB to be on the right
73 /// operand list for registers.
75 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
76 /// gets the next available unique MBB number. If it is removed from a
77 /// MachineFunction, it goes back to being #-1.
78 void ilist_traits<MachineBasicBlock>::addNodeToList(MachineBasicBlock *N) {
79 MachineFunction &MF = *N->getParent();
80 N->Number = MF.addToMBBNumbering(N);
82 // Make sure the instructions have their operands in the reginfo lists.
83 MachineRegisterInfo &RegInfo = MF.getRegInfo();
84 for (MachineBasicBlock::instr_iterator
85 I = N->instr_begin(), E = N->instr_end(); I != E; ++I)
86 I->AddRegOperandsToUseLists(RegInfo);
89 void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock *N) {
90 N->getParent()->removeFromMBBNumbering(N->Number);
94 /// When we add an instruction to a basic block list, we update its parent
95 /// pointer and add its operands from reg use/def lists if appropriate.
96 void ilist_traits<MachineInstr>::addNodeToList(MachineInstr *N) {
97 assert(!N->getParent() && "machine instruction already in a basic block");
100 // Add the instruction's register operands to their corresponding
102 MachineFunction *MF = Parent->getParent();
103 N->AddRegOperandsToUseLists(MF->getRegInfo());
106 /// When we remove an instruction from a basic block list, we update its parent
107 /// pointer and remove its operands from reg use/def lists if appropriate.
108 void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr *N) {
109 assert(N->getParent() && "machine instruction not in a basic block");
111 // Remove from the use/def lists.
112 if (MachineFunction *MF = N->getParent()->getParent())
113 N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
115 N->setParent(nullptr);
118 /// When moving a range of instructions from one MBB list to another, we need to
119 /// update the parent pointers and the use/def lists.
120 void ilist_traits<MachineInstr>::
121 transferNodesFromList(ilist_traits<MachineInstr> &FromList,
122 ilist_iterator<MachineInstr> First,
123 ilist_iterator<MachineInstr> Last) {
124 assert(Parent->getParent() == FromList.Parent->getParent() &&
125 "MachineInstr parent mismatch!");
127 // Splice within the same MBB -> no change.
128 if (Parent == FromList.Parent) return;
130 // If splicing between two blocks within the same function, just update the
132 for (; First != Last; ++First)
133 First->setParent(Parent);
136 void ilist_traits<MachineInstr>::deleteNode(MachineInstr* MI) {
137 assert(!MI->getParent() && "MI is still in a block!");
138 Parent->getParent()->DeleteMachineInstr(MI);
141 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() {
142 instr_iterator I = instr_begin(), E = instr_end();
143 while (I != E && I->isPHI())
145 assert((I == E || !I->isInsideBundle()) &&
146 "First non-phi MI cannot be inside a bundle!");
150 MachineBasicBlock::iterator
151 MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) {
153 while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue()))
155 // FIXME: This needs to change if we wish to bundle labels / dbg_values
156 // inside the bundle.
157 assert((I == E || !I->isInsideBundle()) &&
158 "First non-phi / non-label instruction is inside a bundle!");
162 MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
163 iterator B = begin(), E = end(), I = E;
164 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
166 while (I != E && !I->isTerminator())
171 MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() {
172 instr_iterator B = instr_begin(), E = instr_end(), I = E;
173 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
175 while (I != E && !I->isTerminator())
180 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonDebugInstr() {
181 // Skip over begin-of-block dbg_value instructions.
182 iterator I = begin(), E = end();
183 while (I != E && I->isDebugValue())
188 MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() {
189 // Skip over end-of-block dbg_value instructions.
190 instr_iterator B = instr_begin(), I = instr_end();
193 // Return instruction that starts a bundle.
194 if (I->isDebugValue() || I->isInsideBundle())
198 // The block is all debug values.
202 const MachineBasicBlock *MachineBasicBlock::getLandingPadSuccessor() const {
203 // A block with a landing pad successor only has one other successor.
206 for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
212 bool MachineBasicBlock::hasEHPadSuccessor() const {
213 for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
219 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
220 void MachineBasicBlock::dump() const {
225 StringRef MachineBasicBlock::getName() const {
226 if (const BasicBlock *LBB = getBasicBlock())
227 return LBB->getName();
232 /// Return a hopefully unique identifier for this block.
233 std::string MachineBasicBlock::getFullName() const {
236 Name = (getParent()->getName() + ":").str();
238 Name += getBasicBlock()->getName();
240 Name += ("BB" + Twine(getNumber())).str();
244 void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const {
245 const MachineFunction *MF = getParent();
247 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
251 const Function *F = MF->getFunction();
252 const Module *M = F ? F->getParent() : nullptr;
253 ModuleSlotTracker MST(M);
254 print(OS, MST, Indexes);
257 void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
258 SlotIndexes *Indexes) const {
259 const MachineFunction *MF = getParent();
261 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
267 OS << Indexes->getMBBStartIdx(this) << '\t';
269 OS << "BB#" << getNumber() << ": ";
271 const char *Comma = "";
272 if (const BasicBlock *LBB = getBasicBlock()) {
273 OS << Comma << "derived from LLVM BB ";
274 LBB->printAsOperand(OS, /*PrintType=*/false, MST);
277 if (isEHPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; }
278 if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; }
280 OS << Comma << "Align " << Alignment << " (" << (1u << Alignment)
285 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
286 if (!livein_empty()) {
287 if (Indexes) OS << '\t';
289 for (const auto &LI : make_range(livein_begin(), livein_end())) {
290 OS << ' ' << PrintReg(LI.PhysReg, TRI);
291 if (LI.LaneMask != ~0u)
292 OS << ':' << PrintLaneMask(LI.LaneMask);
296 // Print the preds of this block according to the CFG.
298 if (Indexes) OS << '\t';
299 OS << " Predecessors according to CFG:";
300 for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
301 OS << " BB#" << (*PI)->getNumber();
305 for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) {
307 if (Indexes->hasIndex(&*I))
308 OS << Indexes->getInstructionIndex(&*I);
312 if (I->isInsideBundle())
317 // Print the successors of this block according to the CFG.
319 if (Indexes) OS << '\t';
320 OS << " Successors according to CFG:";
321 for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) {
322 OS << " BB#" << (*SI)->getNumber();
324 OS << '(' << *getProbabilityIterator(SI) << ')';
330 void MachineBasicBlock::printAsOperand(raw_ostream &OS,
331 bool /*PrintType*/) const {
332 OS << "BB#" << getNumber();
335 void MachineBasicBlock::removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) {
336 LiveInVector::iterator I = std::find_if(
337 LiveIns.begin(), LiveIns.end(),
338 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
339 if (I == LiveIns.end())
342 I->LaneMask &= ~LaneMask;
343 if (I->LaneMask == 0)
347 bool MachineBasicBlock::isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) const {
348 livein_iterator I = std::find_if(
349 LiveIns.begin(), LiveIns.end(),
350 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
351 return I != livein_end() && (I->LaneMask & LaneMask) != 0;
354 void MachineBasicBlock::sortUniqueLiveIns() {
355 std::sort(LiveIns.begin(), LiveIns.end(),
356 [](const RegisterMaskPair &LI0, const RegisterMaskPair &LI1) {
357 return LI0.PhysReg < LI1.PhysReg;
359 // Liveins are sorted by physreg now we can merge their lanemasks.
360 LiveInVector::const_iterator I = LiveIns.begin();
361 LiveInVector::const_iterator J;
362 LiveInVector::iterator Out = LiveIns.begin();
363 for (; I != LiveIns.end(); ++Out, I = J) {
364 unsigned PhysReg = I->PhysReg;
365 LaneBitmask LaneMask = I->LaneMask;
366 for (J = std::next(I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J)
367 LaneMask |= J->LaneMask;
368 Out->PhysReg = PhysReg;
369 Out->LaneMask = LaneMask;
371 LiveIns.erase(Out, LiveIns.end());
375 MachineBasicBlock::addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC) {
376 assert(getParent() && "MBB must be inserted in function");
377 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg");
378 assert(RC && "Register class is required");
379 assert((isEHPad() || this == &getParent()->front()) &&
380 "Only the entry block and landing pads can have physreg live ins");
382 bool LiveIn = isLiveIn(PhysReg);
383 iterator I = SkipPHIsAndLabels(begin()), E = end();
384 MachineRegisterInfo &MRI = getParent()->getRegInfo();
385 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
387 // Look for an existing copy.
389 for (;I != E && I->isCopy(); ++I)
390 if (I->getOperand(1).getReg() == PhysReg) {
391 unsigned VirtReg = I->getOperand(0).getReg();
392 if (!MRI.constrainRegClass(VirtReg, RC))
393 llvm_unreachable("Incompatible live-in register class.");
397 // No luck, create a virtual register.
398 unsigned VirtReg = MRI.createVirtualRegister(RC);
399 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
400 .addReg(PhysReg, RegState::Kill);
406 void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
407 getParent()->splice(NewAfter->getIterator(), getIterator());
410 void MachineBasicBlock::moveAfter(MachineBasicBlock *NewBefore) {
411 getParent()->splice(++NewBefore->getIterator(), getIterator());
414 void MachineBasicBlock::updateTerminator() {
415 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
416 // A block with no successors has no concerns with fall-through edges.
417 if (this->succ_empty()) return;
419 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
420 SmallVector<MachineOperand, 4> Cond;
421 DebugLoc DL; // FIXME: this is nowhere
422 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
424 assert(!B && "UpdateTerminators requires analyzable predecessors!");
427 // The block has an unconditional branch. If its successor is now
428 // its layout successor, delete the branch.
429 if (isLayoutSuccessor(TBB))
430 TII->RemoveBranch(*this);
432 // The block has an unconditional fallthrough. If its successor is not
433 // its layout successor, insert a branch. First we have to locate the
434 // only non-landing-pad successor, as that is the fallthrough block.
435 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
436 if ((*SI)->isEHPad())
438 assert(!TBB && "Found more than one non-landing-pad successor!");
442 // If there is no non-landing-pad successor, the block has no
443 // fall-through edges to be concerned with.
447 // Finally update the unconditional successor to be reached via a branch
448 // if it would not be reached by fallthrough.
449 if (!isLayoutSuccessor(TBB))
450 TII->InsertBranch(*this, TBB, nullptr, Cond, DL);
454 // The block has a non-fallthrough conditional branch. If one of its
455 // successors is its layout successor, rewrite it to a fallthrough
456 // conditional branch.
457 if (isLayoutSuccessor(TBB)) {
458 if (TII->ReverseBranchCondition(Cond))
460 TII->RemoveBranch(*this);
461 TII->InsertBranch(*this, FBB, nullptr, Cond, DL);
462 } else if (isLayoutSuccessor(FBB)) {
463 TII->RemoveBranch(*this);
464 TII->InsertBranch(*this, TBB, nullptr, Cond, DL);
467 // Walk through the successors and find the successor which is not
468 // a landing pad and is not the conditional branch destination (in TBB)
469 // as the fallthrough successor.
470 MachineBasicBlock *FallthroughBB = nullptr;
471 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
472 if ((*SI)->isEHPad() || *SI == TBB)
474 assert(!FallthroughBB && "Found more than one fallthrough successor.");
477 if (!FallthroughBB && canFallThrough()) {
478 // We fallthrough to the same basic block as the conditional jump
479 // targets. Remove the conditional jump, leaving unconditional
481 // FIXME: This does not seem like a reasonable pattern to support, but
482 // it has been seen in the wild coming out of degenerate ARM test cases.
483 TII->RemoveBranch(*this);
485 // Finally update the unconditional successor to be reached via a branch
486 // if it would not be reached by fallthrough.
487 if (!isLayoutSuccessor(TBB))
488 TII->InsertBranch(*this, TBB, nullptr, Cond, DL);
492 // The block has a fallthrough conditional branch.
493 if (isLayoutSuccessor(TBB)) {
494 if (TII->ReverseBranchCondition(Cond)) {
495 // We can't reverse the condition, add an unconditional branch.
497 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, DL);
500 TII->RemoveBranch(*this);
501 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, DL);
502 } else if (!isLayoutSuccessor(FallthroughBB)) {
503 TII->RemoveBranch(*this);
504 TII->InsertBranch(*this, TBB, FallthroughBB, Cond, DL);
510 void MachineBasicBlock::validateSuccProbs() const {
513 for (auto Prob : Probs)
514 Sum += Prob.getNumerator();
515 // Due to precision issue, we assume that the sum of probabilities is one if
516 // the difference between the sum of their numerators and the denominator is
517 // no greater than the number of successors.
518 assert((uint64_t)std::abs(Sum - BranchProbability::getDenominator()) <=
520 "The sum of successors's probabilities exceeds one.");
524 void MachineBasicBlock::addSuccessor(MachineBasicBlock *Succ,
525 BranchProbability Prob) {
526 // Probability list is either empty (if successor list isn't empty, this means
527 // disabled optimization) or has the same size as successor list.
528 if (!(Probs.empty() && !Successors.empty()))
529 Probs.push_back(Prob);
530 Successors.push_back(Succ);
531 Succ->addPredecessor(this);
534 void MachineBasicBlock::addSuccessorWithoutProb(MachineBasicBlock *Succ) {
535 // We need to make sure probability list is either empty or has the same size
536 // of successor list. When this function is called, we can safely delete all
537 // probability in the list.
539 Successors.push_back(Succ);
540 Succ->addPredecessor(this);
543 void MachineBasicBlock::removeSuccessor(MachineBasicBlock *Succ,
544 bool NormalizeSuccProbs) {
545 succ_iterator I = std::find(Successors.begin(), Successors.end(), Succ);
546 removeSuccessor(I, NormalizeSuccProbs);
549 MachineBasicBlock::succ_iterator
550 MachineBasicBlock::removeSuccessor(succ_iterator I, bool NormalizeSuccProbs) {
551 assert(I != Successors.end() && "Not a current successor!");
553 // If probability list is empty it means we don't use it (disabled
555 if (!Probs.empty()) {
556 probability_iterator WI = getProbabilityIterator(I);
558 if (NormalizeSuccProbs)
559 normalizeSuccProbs();
562 (*I)->removePredecessor(this);
563 return Successors.erase(I);
566 void MachineBasicBlock::replaceSuccessor(MachineBasicBlock *Old,
567 MachineBasicBlock *New) {
571 succ_iterator E = succ_end();
572 succ_iterator NewI = E;
573 succ_iterator OldI = E;
574 for (succ_iterator I = succ_begin(); I != E; ++I) {
586 assert(OldI != E && "Old is not a successor of this block");
588 // If New isn't already a successor, let it take Old's place.
590 Old->removePredecessor(this);
591 New->addPredecessor(this);
596 // New is already a successor.
597 // Update its probability instead of adding a duplicate edge.
598 if (!Probs.empty()) {
599 auto ProbIter = getProbabilityIterator(NewI);
600 if (!ProbIter->isUnknown())
601 *ProbIter += *getProbabilityIterator(OldI);
603 removeSuccessor(OldI);
606 void MachineBasicBlock::addPredecessor(MachineBasicBlock *Pred) {
607 Predecessors.push_back(Pred);
610 void MachineBasicBlock::removePredecessor(MachineBasicBlock *Pred) {
611 pred_iterator I = std::find(Predecessors.begin(), Predecessors.end(), Pred);
612 assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
613 Predecessors.erase(I);
616 void MachineBasicBlock::transferSuccessors(MachineBasicBlock *FromMBB) {
620 while (!FromMBB->succ_empty()) {
621 MachineBasicBlock *Succ = *FromMBB->succ_begin();
623 // If probability list is empty it means we don't use it (disabled optimization).
624 if (!FromMBB->Probs.empty()) {
625 auto Prob = *FromMBB->Probs.begin();
626 addSuccessor(Succ, Prob);
628 addSuccessorWithoutProb(Succ);
630 FromMBB->removeSuccessor(Succ);
635 MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB) {
639 while (!FromMBB->succ_empty()) {
640 MachineBasicBlock *Succ = *FromMBB->succ_begin();
641 if (!FromMBB->Probs.empty()) {
642 auto Prob = *FromMBB->Probs.begin();
643 addSuccessor(Succ, Prob);
645 addSuccessorWithoutProb(Succ);
646 FromMBB->removeSuccessor(Succ);
648 // Fix up any PHI nodes in the successor.
649 for (MachineBasicBlock::instr_iterator MI = Succ->instr_begin(),
650 ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI)
651 for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
652 MachineOperand &MO = MI->getOperand(i);
653 if (MO.getMBB() == FromMBB)
657 normalizeSuccProbs();
660 bool MachineBasicBlock::isPredecessor(const MachineBasicBlock *MBB) const {
661 return std::find(pred_begin(), pred_end(), MBB) != pred_end();
664 bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const {
665 return std::find(succ_begin(), succ_end(), MBB) != succ_end();
668 bool MachineBasicBlock::isLayoutSuccessor(const MachineBasicBlock *MBB) const {
669 MachineFunction::const_iterator I(this);
670 return std::next(I) == MachineFunction::const_iterator(MBB);
673 bool MachineBasicBlock::canFallThrough() {
674 MachineFunction::iterator Fallthrough = getIterator();
676 // If FallthroughBlock is off the end of the function, it can't fall through.
677 if (Fallthrough == getParent()->end())
680 // If FallthroughBlock isn't a successor, no fallthrough is possible.
681 if (!isSuccessor(&*Fallthrough))
684 // Analyze the branches, if any, at the end of the block.
685 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
686 SmallVector<MachineOperand, 4> Cond;
687 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
688 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) {
689 // If we couldn't analyze the branch, examine the last instruction.
690 // If the block doesn't end in a known control barrier, assume fallthrough
691 // is possible. The isPredicated check is needed because this code can be
692 // called during IfConversion, where an instruction which is normally a
693 // Barrier is predicated and thus no longer an actual control barrier.
694 return empty() || !back().isBarrier() || TII->isPredicated(&back());
697 // If there is no branch, control always falls through.
698 if (!TBB) return true;
700 // If there is some explicit branch to the fallthrough block, it can obviously
701 // reach, even though the branch should get folded to fall through implicitly.
702 if (MachineFunction::iterator(TBB) == Fallthrough ||
703 MachineFunction::iterator(FBB) == Fallthrough)
706 // If it's an unconditional branch to some block not the fall through, it
707 // doesn't fall through.
708 if (Cond.empty()) return false;
710 // Otherwise, if it is conditional and has no explicit false block, it falls
712 return FBB == nullptr;
716 MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) {
717 // Splitting the critical edge to a landing pad block is non-trivial. Don't do
718 // it in this generic function.
722 MachineFunction *MF = getParent();
723 DebugLoc DL; // FIXME: this is nowhere
725 // Performance might be harmed on HW that implements branching using exec mask
726 // where both sides of the branches are always executed.
727 if (MF->getTarget().requiresStructuredCFG())
730 // We may need to update this's terminator, but we can't do that if
731 // AnalyzeBranch fails. If this uses a jump table, we won't touch it.
732 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
733 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
734 SmallVector<MachineOperand, 4> Cond;
735 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond))
738 // Avoid bugpoint weirdness: A block may end with a conditional branch but
739 // jumps to the same MBB is either case. We have duplicate CFG edges in that
740 // case that we can't handle. Since this never happens in properly optimized
741 // code, just skip those edges.
742 if (TBB && TBB == FBB) {
743 DEBUG(dbgs() << "Won't split critical edge after degenerate BB#"
744 << getNumber() << '\n');
748 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
749 MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
750 DEBUG(dbgs() << "Splitting critical edge:"
751 " BB#" << getNumber()
752 << " -- BB#" << NMBB->getNumber()
753 << " -- BB#" << Succ->getNumber() << '\n');
755 LiveIntervals *LIS = P->getAnalysisIfAvailable<LiveIntervals>();
756 SlotIndexes *Indexes = P->getAnalysisIfAvailable<SlotIndexes>();
758 LIS->insertMBBInMaps(NMBB);
760 Indexes->insertMBBInMaps(NMBB);
762 // On some targets like Mips, branches may kill virtual registers. Make sure
763 // that LiveVariables is properly updated after updateTerminator replaces the
765 LiveVariables *LV = P->getAnalysisIfAvailable<LiveVariables>();
767 // Collect a list of virtual registers killed by the terminators.
768 SmallVector<unsigned, 4> KilledRegs;
770 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
772 MachineInstr *MI = &*I;
773 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
774 OE = MI->operands_end(); OI != OE; ++OI) {
775 if (!OI->isReg() || OI->getReg() == 0 ||
776 !OI->isUse() || !OI->isKill() || OI->isUndef())
778 unsigned Reg = OI->getReg();
779 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
780 LV->getVarInfo(Reg).removeKill(MI)) {
781 KilledRegs.push_back(Reg);
782 DEBUG(dbgs() << "Removing terminator kill: " << *MI);
783 OI->setIsKill(false);
788 SmallVector<unsigned, 4> UsedRegs;
790 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
792 MachineInstr *MI = &*I;
794 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
795 OE = MI->operands_end(); OI != OE; ++OI) {
796 if (!OI->isReg() || OI->getReg() == 0)
799 unsigned Reg = OI->getReg();
800 if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end())
801 UsedRegs.push_back(Reg);
806 ReplaceUsesOfBlockWith(Succ, NMBB);
808 // If updateTerminator() removes instructions, we need to remove them from
810 SmallVector<MachineInstr*, 4> Terminators;
812 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
814 Terminators.push_back(&*I);
820 SmallVector<MachineInstr*, 4> NewTerminators;
821 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
823 NewTerminators.push_back(&*I);
825 for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(),
826 E = Terminators.end(); I != E; ++I) {
827 if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) ==
828 NewTerminators.end())
829 Indexes->removeMachineInstrFromMaps(*I);
833 // Insert unconditional "jump Succ" instruction in NMBB if necessary.
834 NMBB->addSuccessor(Succ);
835 if (!NMBB->isLayoutSuccessor(Succ)) {
837 TII->InsertBranch(*NMBB, Succ, nullptr, Cond, DL);
840 for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end();
842 // Some instructions may have been moved to NMBB by updateTerminator(),
843 // so we first remove any instruction that already has an index.
844 if (Indexes->hasIndex(&*I))
845 Indexes->removeMachineInstrFromMaps(&*I);
846 Indexes->insertMachineInstrInMaps(&*I);
851 // Fix PHI nodes in Succ so they refer to NMBB instead of this
852 for (MachineBasicBlock::instr_iterator
853 i = Succ->instr_begin(),e = Succ->instr_end();
854 i != e && i->isPHI(); ++i)
855 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
856 if (i->getOperand(ni+1).getMBB() == this)
857 i->getOperand(ni+1).setMBB(NMBB);
859 // Inherit live-ins from the successor
860 for (const auto &LI : Succ->liveins())
863 // Update LiveVariables.
864 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
866 // Restore kills of virtual registers that were killed by the terminators.
867 while (!KilledRegs.empty()) {
868 unsigned Reg = KilledRegs.pop_back_val();
869 for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
870 if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false))
872 if (TargetRegisterInfo::isVirtualRegister(Reg))
873 LV->getVarInfo(Reg).Kills.push_back(&*I);
874 DEBUG(dbgs() << "Restored terminator kill: " << *I);
878 // Update relevant live-through information.
879 LV->addNewBlock(NMBB, this, Succ);
883 // After splitting the edge and updating SlotIndexes, live intervals may be
884 // in one of two situations, depending on whether this block was the last in
885 // the function. If the original block was the last in the function, all
886 // live intervals will end prior to the beginning of the new split block. If
887 // the original block was not at the end of the function, all live intervals
888 // will extend to the end of the new split block.
891 std::next(MachineFunction::iterator(NMBB)) == getParent()->end();
893 SlotIndex StartIndex = Indexes->getMBBEndIdx(this);
894 SlotIndex PrevIndex = StartIndex.getPrevSlot();
895 SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);
897 // Find the registers used from NMBB in PHIs in Succ.
898 SmallSet<unsigned, 8> PHISrcRegs;
899 for (MachineBasicBlock::instr_iterator
900 I = Succ->instr_begin(), E = Succ->instr_end();
901 I != E && I->isPHI(); ++I) {
902 for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
903 if (I->getOperand(ni+1).getMBB() == NMBB) {
904 MachineOperand &MO = I->getOperand(ni);
905 unsigned Reg = MO.getReg();
906 PHISrcRegs.insert(Reg);
910 LiveInterval &LI = LIS->getInterval(Reg);
911 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
913 "PHI sources should be live out of their predecessors.");
914 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
919 MachineRegisterInfo *MRI = &getParent()->getRegInfo();
920 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
921 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
922 if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg))
925 LiveInterval &LI = LIS->getInterval(Reg);
926 if (!LI.liveAt(PrevIndex))
929 bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ));
930 if (isLiveOut && isLastMBB) {
931 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
932 assert(VNI && "LiveInterval should have VNInfo where it is live.");
933 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
934 } else if (!isLiveOut && !isLastMBB) {
935 LI.removeSegment(StartIndex, EndIndex);
939 // Update all intervals for registers whose uses may have been modified by
940 // updateTerminator().
941 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs);
944 if (MachineDominatorTree *MDT =
945 P->getAnalysisIfAvailable<MachineDominatorTree>())
946 MDT->recordSplitCriticalEdge(this, Succ, NMBB);
948 if (MachineLoopInfo *MLI = P->getAnalysisIfAvailable<MachineLoopInfo>())
949 if (MachineLoop *TIL = MLI->getLoopFor(this)) {
950 // If one or the other blocks were not in a loop, the new block is not
951 // either, and thus LI doesn't need to be updated.
952 if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) {
953 if (TIL == DestLoop) {
954 // Both in the same loop, the NMBB joins loop.
955 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
956 } else if (TIL->contains(DestLoop)) {
957 // Edge from an outer loop to an inner loop. Add to the outer loop.
958 TIL->addBasicBlockToLoop(NMBB, MLI->getBase());
959 } else if (DestLoop->contains(TIL)) {
960 // Edge from an inner loop to an outer loop. Add to the outer loop.
961 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
963 // Edge from two loops with no containment relation. Because these
964 // are natural loops, we know that the destination block must be the
965 // header of its loop (adding a branch into a loop elsewhere would
966 // create an irreducible loop).
967 assert(DestLoop->getHeader() == Succ &&
968 "Should not create irreducible loops!");
969 if (MachineLoop *P = DestLoop->getParentLoop())
970 P->addBasicBlockToLoop(NMBB, MLI->getBase());
978 /// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
979 /// neighboring instructions so the bundle won't be broken by removing MI.
980 static void unbundleSingleMI(MachineInstr *MI) {
981 // Removing the first instruction in a bundle.
982 if (MI->isBundledWithSucc() && !MI->isBundledWithPred())
983 MI->unbundleFromSucc();
984 // Removing the last instruction in a bundle.
985 if (MI->isBundledWithPred() && !MI->isBundledWithSucc())
986 MI->unbundleFromPred();
987 // If MI is not bundled, or if it is internal to a bundle, the neighbor flags
991 MachineBasicBlock::instr_iterator
992 MachineBasicBlock::erase(MachineBasicBlock::instr_iterator I) {
993 unbundleSingleMI(&*I);
994 return Insts.erase(I);
997 MachineInstr *MachineBasicBlock::remove_instr(MachineInstr *MI) {
998 unbundleSingleMI(MI);
999 MI->clearFlag(MachineInstr::BundledPred);
1000 MI->clearFlag(MachineInstr::BundledSucc);
1001 return Insts.remove(MI);
1004 MachineBasicBlock::instr_iterator
1005 MachineBasicBlock::insert(instr_iterator I, MachineInstr *MI) {
1006 assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() &&
1007 "Cannot insert instruction with bundle flags");
1008 // Set the bundle flags when inserting inside a bundle.
1009 if (I != instr_end() && I->isBundledWithPred()) {
1010 MI->setFlag(MachineInstr::BundledPred);
1011 MI->setFlag(MachineInstr::BundledSucc);
1013 return Insts.insert(I, MI);
1016 /// This method unlinks 'this' from the containing function, and returns it, but
1017 /// does not delete it.
1018 MachineBasicBlock *MachineBasicBlock::removeFromParent() {
1019 assert(getParent() && "Not embedded in a function!");
1020 getParent()->remove(this);
1024 /// This method unlinks 'this' from the containing function, and deletes it.
1025 void MachineBasicBlock::eraseFromParent() {
1026 assert(getParent() && "Not embedded in a function!");
1027 getParent()->erase(this);
1030 /// Given a machine basic block that branched to 'Old', change the code and CFG
1031 /// so that it branches to 'New' instead.
1032 void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
1033 MachineBasicBlock *New) {
1034 assert(Old != New && "Cannot replace self with self!");
1036 MachineBasicBlock::instr_iterator I = instr_end();
1037 while (I != instr_begin()) {
1039 if (!I->isTerminator()) break;
1041 // Scan the operands of this machine instruction, replacing any uses of Old
1043 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1044 if (I->getOperand(i).isMBB() &&
1045 I->getOperand(i).getMBB() == Old)
1046 I->getOperand(i).setMBB(New);
1049 // Update the successor information.
1050 replaceSuccessor(Old, New);
1053 /// Various pieces of code can cause excess edges in the CFG to be inserted. If
1054 /// we have proven that MBB can only branch to DestA and DestB, remove any other
1055 /// MBB successors from the CFG. DestA and DestB can be null.
1057 /// Besides DestA and DestB, retain other edges leading to LandingPads
1058 /// (currently there can be only one; we don't check or require that here).
1059 /// Note it is possible that DestA and/or DestB are LandingPads.
1060 bool MachineBasicBlock::CorrectExtraCFGEdges(MachineBasicBlock *DestA,
1061 MachineBasicBlock *DestB,
1063 // The values of DestA and DestB frequently come from a call to the
1064 // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial
1065 // values from there.
1067 // 1. If both DestA and DestB are null, then the block ends with no branches
1068 // (it falls through to its successor).
1069 // 2. If DestA is set, DestB is null, and IsCond is false, then the block ends
1070 // with only an unconditional branch.
1071 // 3. If DestA is set, DestB is null, and IsCond is true, then the block ends
1072 // with a conditional branch that falls through to a successor (DestB).
1073 // 4. If DestA and DestB is set and IsCond is true, then the block ends with a
1074 // conditional branch followed by an unconditional branch. DestA is the
1075 // 'true' destination and DestB is the 'false' destination.
1077 bool Changed = false;
1079 MachineFunction::iterator FallThru = std::next(getIterator());
1081 if (!DestA && !DestB) {
1082 // Block falls through to successor.
1085 } else if (DestA && !DestB) {
1087 // Block ends in conditional jump that falls through to successor.
1090 assert(DestA && DestB && IsCond &&
1091 "CFG in a bad state. Cannot correct CFG edges");
1094 // Remove superfluous edges. I.e., those which aren't destinations of this
1095 // basic block, duplicate edges, or landing pads.
1096 SmallPtrSet<const MachineBasicBlock*, 8> SeenMBBs;
1097 MachineBasicBlock::succ_iterator SI = succ_begin();
1098 while (SI != succ_end()) {
1099 const MachineBasicBlock *MBB = *SI;
1100 if (!SeenMBBs.insert(MBB).second ||
1101 (MBB != DestA && MBB != DestB && !MBB->isEHPad())) {
1102 // This is a superfluous edge, remove it.
1103 SI = removeSuccessor(SI);
1111 normalizeSuccProbs();
1115 /// Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE
1116 /// instructions. Return UnknownLoc if there is none.
1118 MachineBasicBlock::findDebugLoc(instr_iterator MBBI) {
1120 instr_iterator E = instr_end();
1124 // Skip debug declarations, we don't want a DebugLoc from them.
1125 while (MBBI != E && MBBI->isDebugValue())
1128 DL = MBBI->getDebugLoc();
1132 /// Return probability of the edge from this block to MBB.
1134 MachineBasicBlock::getSuccProbability(const_succ_iterator Succ) const {
1136 return BranchProbability(1, succ_size());
1138 const auto &Prob = *getProbabilityIterator(Succ);
1139 if (Prob.isUnknown()) {
1140 // For unknown probabilities, collect the sum of all known ones, and evenly
1141 // ditribute the complemental of the sum to each unknown probability.
1142 unsigned KnownProbNum = 0;
1143 auto Sum = BranchProbability::getZero();
1144 for (auto &P : Probs) {
1145 if (!P.isUnknown()) {
1150 return Sum.getCompl() / (Probs.size() - KnownProbNum);
1155 /// Set successor probability of a given iterator.
1156 void MachineBasicBlock::setSuccProbability(succ_iterator I,
1157 BranchProbability Prob) {
1158 assert(!Prob.isUnknown());
1161 *getProbabilityIterator(I) = Prob;
1164 /// Return probability iterator corresonding to the I successor iterator
1165 MachineBasicBlock::const_probability_iterator
1166 MachineBasicBlock::getProbabilityIterator(
1167 MachineBasicBlock::const_succ_iterator I) const {
1168 assert(Probs.size() == Successors.size() && "Async probability list!");
1169 const size_t index = std::distance(Successors.begin(), I);
1170 assert(index < Probs.size() && "Not a current successor!");
1171 return Probs.begin() + index;
1174 /// Return probability iterator corresonding to the I successor iterator.
1175 MachineBasicBlock::probability_iterator
1176 MachineBasicBlock::getProbabilityIterator(MachineBasicBlock::succ_iterator I) {
1177 assert(Probs.size() == Successors.size() && "Async probability list!");
1178 const size_t index = std::distance(Successors.begin(), I);
1179 assert(index < Probs.size() && "Not a current successor!");
1180 return Probs.begin() + index;
1183 /// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
1184 /// as of just before "MI".
1186 /// Search is localised to a neighborhood of
1187 /// Neighborhood instructions before (searching for defs or kills) and N
1188 /// instructions after (searching just for defs) MI.
1189 MachineBasicBlock::LivenessQueryResult
1190 MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
1191 unsigned Reg, const_iterator Before,
1192 unsigned Neighborhood) const {
1193 unsigned N = Neighborhood;
1195 // Start by searching backwards from Before, looking for kills, reads or defs.
1196 const_iterator I(Before);
1197 // If this is the first insn in the block, don't search backwards.
1202 MachineOperandIteratorBase::PhysRegInfo Info =
1203 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1205 // Defs happen after uses so they take precedence if both are present.
1207 // Register is dead after a dead def of the full register.
1210 // Register is (at least partially) live after a def.
1213 // Register is dead after a full kill or clobber and no def.
1214 if (Info.Killed || Info.Clobbered)
1216 // Register must be live if we read it.
1219 } while (I != begin() && --N > 0);
1222 // Did we get to the start of the block?
1224 // If so, the register's state is definitely defined by the live-in state.
1225 for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true); RAI.isValid();
1235 // Try searching forwards from Before, looking for reads or defs.
1236 I = const_iterator(Before);
1237 // If this is the last insn in the block, don't search forwards.
1239 for (++I; I != end() && N > 0; ++I, --N) {
1240 MachineOperandIteratorBase::PhysRegInfo Info =
1241 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1243 // Register is live when we read it here.
1246 // Register is dead if we can fully overwrite or clobber it here.
1247 if (Info.FullyDefined || Info.Clobbered)
1252 // At this point we have no idea of the liveness of the register.
1257 MachineBasicBlock::getBeginClobberMask(const TargetRegisterInfo *TRI) const {
1258 // EH funclet entry does not preserve any registers.
1259 return isEHFuncletEntry() ? TRI->getNoPreservedMask() : nullptr;
1263 MachineBasicBlock::getEndClobberMask(const TargetRegisterInfo *TRI) const {
1264 // If we see a return block with successors, this must be a funclet return,
1265 // which does not preserve any registers. If there are no successors, we don't
1266 // care what kind of return it is, putting a mask after it is a no-op.
1267 return isReturnBlock() && !succ_empty() ? TRI->getNoPreservedMask() : nullptr;