1 //===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Collect the sequence of machine instructions for a basic block.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineBasicBlock.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallString.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "llvm/CodeGen/LiveVariables.h"
19 #include "llvm/CodeGen/MachineDominators.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SlotIndexes.h"
25 #include "llvm/IR/BasicBlock.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetSubtargetInfo.h"
38 #define DEBUG_TYPE "codegen"
40 MachineBasicBlock::MachineBasicBlock(MachineFunction &mf, const BasicBlock *bb)
41 : BB(bb), Number(-1), xParent(&mf), Alignment(0), IsLandingPad(false),
42 AddressTaken(false), CachedMCSymbol(nullptr) {
46 MachineBasicBlock::~MachineBasicBlock() {
49 /// getSymbol - Return the MCSymbol for this basic block.
51 MCSymbol *MachineBasicBlock::getSymbol() const {
52 if (!CachedMCSymbol) {
53 const MachineFunction *MF = getParent();
54 MCContext &Ctx = MF->getContext();
55 const char *Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
56 CachedMCSymbol = Ctx.GetOrCreateSymbol(Twine(Prefix) + "BB" +
57 Twine(MF->getFunctionNumber()) +
58 "_" + Twine(getNumber()));
61 return CachedMCSymbol;
65 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) {
70 /// addNodeToList (MBB) - When an MBB is added to an MF, we need to update the
71 /// parent pointer of the MBB, the MBB numbering, and any instructions in the
72 /// MBB to be on the right operand list for registers.
74 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
75 /// gets the next available unique MBB number. If it is removed from a
76 /// MachineFunction, it goes back to being #-1.
77 void ilist_traits<MachineBasicBlock>::addNodeToList(MachineBasicBlock *N) {
78 MachineFunction &MF = *N->getParent();
79 N->Number = MF.addToMBBNumbering(N);
81 // Make sure the instructions have their operands in the reginfo lists.
82 MachineRegisterInfo &RegInfo = MF.getRegInfo();
83 for (MachineBasicBlock::instr_iterator
84 I = N->instr_begin(), E = N->instr_end(); I != E; ++I)
85 I->AddRegOperandsToUseLists(RegInfo);
88 void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock *N) {
89 N->getParent()->removeFromMBBNumbering(N->Number);
94 /// addNodeToList (MI) - When we add an instruction to a basic block
95 /// list, we update its parent pointer and add its operands from reg use/def
96 /// lists if appropriate.
97 void ilist_traits<MachineInstr>::addNodeToList(MachineInstr *N) {
98 assert(!N->getParent() && "machine instruction already in a basic block");
101 // Add the instruction's register operands to their corresponding
103 MachineFunction *MF = Parent->getParent();
104 N->AddRegOperandsToUseLists(MF->getRegInfo());
107 /// removeNodeFromList (MI) - When we remove an instruction from a basic block
108 /// list, we update its parent pointer and remove its operands from reg use/def
109 /// lists if appropriate.
110 void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr *N) {
111 assert(N->getParent() && "machine instruction not in a basic block");
113 // Remove from the use/def lists.
114 if (MachineFunction *MF = N->getParent()->getParent())
115 N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
117 N->setParent(nullptr);
120 /// transferNodesFromList (MI) - When moving a range of instructions from one
121 /// MBB list to another, we need to update the parent pointers and the use/def
123 void ilist_traits<MachineInstr>::
124 transferNodesFromList(ilist_traits<MachineInstr> &fromList,
125 ilist_iterator<MachineInstr> first,
126 ilist_iterator<MachineInstr> last) {
127 assert(Parent->getParent() == fromList.Parent->getParent() &&
128 "MachineInstr parent mismatch!");
130 // Splice within the same MBB -> no change.
131 if (Parent == fromList.Parent) return;
133 // If splicing between two blocks within the same function, just update the
135 for (; first != last; ++first)
136 first->setParent(Parent);
139 void ilist_traits<MachineInstr>::deleteNode(MachineInstr* MI) {
140 assert(!MI->getParent() && "MI is still in a block!");
141 Parent->getParent()->DeleteMachineInstr(MI);
144 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() {
145 instr_iterator I = instr_begin(), E = instr_end();
146 while (I != E && I->isPHI())
148 assert((I == E || !I->isInsideBundle()) &&
149 "First non-phi MI cannot be inside a bundle!");
153 MachineBasicBlock::iterator
154 MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) {
156 while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue()))
158 // FIXME: This needs to change if we wish to bundle labels / dbg_values
159 // inside the bundle.
160 assert((I == E || !I->isInsideBundle()) &&
161 "First non-phi / non-label instruction is inside a bundle!");
165 MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
166 iterator B = begin(), E = end(), I = E;
167 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
169 while (I != E && !I->isTerminator())
174 MachineBasicBlock::const_iterator
175 MachineBasicBlock::getFirstTerminator() const {
176 const_iterator B = begin(), E = end(), I = E;
177 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
179 while (I != E && !I->isTerminator())
184 MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() {
185 instr_iterator B = instr_begin(), E = instr_end(), I = E;
186 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
188 while (I != E && !I->isTerminator())
193 MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() {
194 // Skip over end-of-block dbg_value instructions.
195 instr_iterator B = instr_begin(), I = instr_end();
198 // Return instruction that starts a bundle.
199 if (I->isDebugValue() || I->isInsideBundle())
203 // The block is all debug values.
207 MachineBasicBlock::const_iterator
208 MachineBasicBlock::getLastNonDebugInstr() const {
209 // Skip over end-of-block dbg_value instructions.
210 const_instr_iterator B = instr_begin(), I = instr_end();
213 // Return instruction that starts a bundle.
214 if (I->isDebugValue() || I->isInsideBundle())
218 // The block is all debug values.
222 const MachineBasicBlock *MachineBasicBlock::getLandingPadSuccessor() const {
223 // A block with a landing pad successor only has one other successor.
226 for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
227 if ((*I)->isLandingPad())
232 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
233 void MachineBasicBlock::dump() const {
238 StringRef MachineBasicBlock::getName() const {
239 if (const BasicBlock *LBB = getBasicBlock())
240 return LBB->getName();
245 /// Return a hopefully unique identifier for this block.
246 std::string MachineBasicBlock::getFullName() const {
249 Name = (getParent()->getName() + ":").str();
251 Name += getBasicBlock()->getName();
253 Name += (Twine("BB") + Twine(getNumber())).str();
257 void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const {
258 const MachineFunction *MF = getParent();
260 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
266 OS << Indexes->getMBBStartIdx(this) << '\t';
268 OS << "BB#" << getNumber() << ": ";
270 const char *Comma = "";
271 if (const BasicBlock *LBB = getBasicBlock()) {
272 OS << Comma << "derived from LLVM BB ";
273 LBB->printAsOperand(OS, /*PrintType=*/false);
276 if (isLandingPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; }
277 if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; }
279 OS << Comma << "Align " << Alignment << " (" << (1u << Alignment)
284 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
285 if (!livein_empty()) {
286 if (Indexes) OS << '\t';
288 for (livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
289 OS << ' ' << PrintReg(*I, TRI);
292 // Print the preds of this block according to the CFG.
294 if (Indexes) OS << '\t';
295 OS << " Predecessors according to CFG:";
296 for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
297 OS << " BB#" << (*PI)->getNumber();
301 for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) {
303 if (Indexes->hasIndex(I))
304 OS << Indexes->getInstructionIndex(I);
308 if (I->isInsideBundle())
313 // Print the successors of this block according to the CFG.
315 if (Indexes) OS << '\t';
316 OS << " Successors according to CFG:";
317 for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) {
318 OS << " BB#" << (*SI)->getNumber();
319 if (!Weights.empty())
320 OS << '(' << *getWeightIterator(SI) << ')';
326 void MachineBasicBlock::printAsOperand(raw_ostream &OS, bool /*PrintType*/) const {
327 OS << "BB#" << getNumber();
330 void MachineBasicBlock::removeLiveIn(unsigned Reg) {
331 std::vector<unsigned>::iterator I =
332 std::find(LiveIns.begin(), LiveIns.end(), Reg);
333 if (I != LiveIns.end())
337 bool MachineBasicBlock::isLiveIn(unsigned Reg) const {
338 livein_iterator I = std::find(livein_begin(), livein_end(), Reg);
339 return I != livein_end();
343 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) {
344 assert(getParent() && "MBB must be inserted in function");
345 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg");
346 assert(RC && "Register class is required");
347 assert((isLandingPad() || this == &getParent()->front()) &&
348 "Only the entry block and landing pads can have physreg live ins");
350 bool LiveIn = isLiveIn(PhysReg);
351 iterator I = SkipPHIsAndLabels(begin()), E = end();
352 MachineRegisterInfo &MRI = getParent()->getRegInfo();
353 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
355 // Look for an existing copy.
357 for (;I != E && I->isCopy(); ++I)
358 if (I->getOperand(1).getReg() == PhysReg) {
359 unsigned VirtReg = I->getOperand(0).getReg();
360 if (!MRI.constrainRegClass(VirtReg, RC))
361 llvm_unreachable("Incompatible live-in register class.");
365 // No luck, create a virtual register.
366 unsigned VirtReg = MRI.createVirtualRegister(RC);
367 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
368 .addReg(PhysReg, RegState::Kill);
374 void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
375 getParent()->splice(NewAfter, this);
378 void MachineBasicBlock::moveAfter(MachineBasicBlock *NewBefore) {
379 MachineFunction::iterator BBI = NewBefore;
380 getParent()->splice(++BBI, this);
383 void MachineBasicBlock::updateTerminator() {
384 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
385 // A block with no successors has no concerns with fall-through edges.
386 if (this->succ_empty()) return;
388 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
389 SmallVector<MachineOperand, 4> Cond;
390 DebugLoc dl; // FIXME: this is nowhere
391 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
393 assert(!B && "UpdateTerminators requires analyzable predecessors!");
396 // The block has an unconditional branch. If its successor is now
397 // its layout successor, delete the branch.
398 if (isLayoutSuccessor(TBB))
399 TII->RemoveBranch(*this);
401 // The block has an unconditional fallthrough. If its successor is not
402 // its layout successor, insert a branch. First we have to locate the
403 // only non-landing-pad successor, as that is the fallthrough block.
404 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
405 if ((*SI)->isLandingPad())
407 assert(!TBB && "Found more than one non-landing-pad successor!");
411 // If there is no non-landing-pad successor, the block has no
412 // fall-through edges to be concerned with.
416 // Finally update the unconditional successor to be reached via a branch
417 // if it would not be reached by fallthrough.
418 if (!isLayoutSuccessor(TBB))
419 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
423 // The block has a non-fallthrough conditional branch. If one of its
424 // successors is its layout successor, rewrite it to a fallthrough
425 // conditional branch.
426 if (isLayoutSuccessor(TBB)) {
427 if (TII->ReverseBranchCondition(Cond))
429 TII->RemoveBranch(*this);
430 TII->InsertBranch(*this, FBB, nullptr, Cond, dl);
431 } else if (isLayoutSuccessor(FBB)) {
432 TII->RemoveBranch(*this);
433 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
436 // Walk through the successors and find the successor which is not
437 // a landing pad and is not the conditional branch destination (in TBB)
438 // as the fallthrough successor.
439 MachineBasicBlock *FallthroughBB = nullptr;
440 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
441 if ((*SI)->isLandingPad() || *SI == TBB)
443 assert(!FallthroughBB && "Found more than one fallthrough successor.");
446 if (!FallthroughBB && canFallThrough()) {
447 // We fallthrough to the same basic block as the conditional jump
448 // targets. Remove the conditional jump, leaving unconditional
450 // FIXME: This does not seem like a reasonable pattern to support, but it
451 // has been seen in the wild coming out of degenerate ARM test cases.
452 TII->RemoveBranch(*this);
454 // Finally update the unconditional successor to be reached via a branch
455 // if it would not be reached by fallthrough.
456 if (!isLayoutSuccessor(TBB))
457 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
461 // The block has a fallthrough conditional branch.
462 if (isLayoutSuccessor(TBB)) {
463 if (TII->ReverseBranchCondition(Cond)) {
464 // We can't reverse the condition, add an unconditional branch.
466 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl);
469 TII->RemoveBranch(*this);
470 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl);
471 } else if (!isLayoutSuccessor(FallthroughBB)) {
472 TII->RemoveBranch(*this);
473 TII->InsertBranch(*this, TBB, FallthroughBB, Cond, dl);
479 void MachineBasicBlock::addSuccessor(MachineBasicBlock *succ, uint32_t weight) {
481 // If we see non-zero value for the first time it means we actually use Weight
482 // list, so we fill all Weights with 0's.
483 if (weight != 0 && Weights.empty())
484 Weights.resize(Successors.size());
486 if (weight != 0 || !Weights.empty())
487 Weights.push_back(weight);
489 Successors.push_back(succ);
490 succ->addPredecessor(this);
493 void MachineBasicBlock::removeSuccessor(MachineBasicBlock *succ) {
494 succ->removePredecessor(this);
495 succ_iterator I = std::find(Successors.begin(), Successors.end(), succ);
496 assert(I != Successors.end() && "Not a current successor!");
498 // If Weight list is empty it means we don't use it (disabled optimization).
499 if (!Weights.empty()) {
500 weight_iterator WI = getWeightIterator(I);
507 MachineBasicBlock::succ_iterator
508 MachineBasicBlock::removeSuccessor(succ_iterator I) {
509 assert(I != Successors.end() && "Not a current successor!");
511 // If Weight list is empty it means we don't use it (disabled optimization).
512 if (!Weights.empty()) {
513 weight_iterator WI = getWeightIterator(I);
517 (*I)->removePredecessor(this);
518 return Successors.erase(I);
521 void MachineBasicBlock::replaceSuccessor(MachineBasicBlock *Old,
522 MachineBasicBlock *New) {
526 succ_iterator E = succ_end();
527 succ_iterator NewI = E;
528 succ_iterator OldI = E;
529 for (succ_iterator I = succ_begin(); I != E; ++I) {
541 assert(OldI != E && "Old is not a successor of this block");
542 Old->removePredecessor(this);
544 // If New isn't already a successor, let it take Old's place.
546 New->addPredecessor(this);
551 // New is already a successor.
552 // Update its weight instead of adding a duplicate edge.
553 if (!Weights.empty()) {
554 weight_iterator OldWI = getWeightIterator(OldI);
555 *getWeightIterator(NewI) += *OldWI;
556 Weights.erase(OldWI);
558 Successors.erase(OldI);
561 void MachineBasicBlock::addPredecessor(MachineBasicBlock *pred) {
562 Predecessors.push_back(pred);
565 void MachineBasicBlock::removePredecessor(MachineBasicBlock *pred) {
566 pred_iterator I = std::find(Predecessors.begin(), Predecessors.end(), pred);
567 assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
568 Predecessors.erase(I);
571 void MachineBasicBlock::transferSuccessors(MachineBasicBlock *fromMBB) {
575 while (!fromMBB->succ_empty()) {
576 MachineBasicBlock *Succ = *fromMBB->succ_begin();
579 // If Weight list is empty it means we don't use it (disabled optimization).
580 if (!fromMBB->Weights.empty())
581 Weight = *fromMBB->Weights.begin();
583 addSuccessor(Succ, Weight);
584 fromMBB->removeSuccessor(Succ);
589 MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB) {
593 while (!fromMBB->succ_empty()) {
594 MachineBasicBlock *Succ = *fromMBB->succ_begin();
596 if (!fromMBB->Weights.empty())
597 Weight = *fromMBB->Weights.begin();
598 addSuccessor(Succ, Weight);
599 fromMBB->removeSuccessor(Succ);
601 // Fix up any PHI nodes in the successor.
602 for (MachineBasicBlock::instr_iterator MI = Succ->instr_begin(),
603 ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI)
604 for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
605 MachineOperand &MO = MI->getOperand(i);
606 if (MO.getMBB() == fromMBB)
612 bool MachineBasicBlock::isPredecessor(const MachineBasicBlock *MBB) const {
613 return std::find(pred_begin(), pred_end(), MBB) != pred_end();
616 bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const {
617 return std::find(succ_begin(), succ_end(), MBB) != succ_end();
620 bool MachineBasicBlock::isLayoutSuccessor(const MachineBasicBlock *MBB) const {
621 MachineFunction::const_iterator I(this);
622 return std::next(I) == MachineFunction::const_iterator(MBB);
625 bool MachineBasicBlock::canFallThrough() {
626 MachineFunction::iterator Fallthrough = this;
628 // If FallthroughBlock is off the end of the function, it can't fall through.
629 if (Fallthrough == getParent()->end())
632 // If FallthroughBlock isn't a successor, no fallthrough is possible.
633 if (!isSuccessor(Fallthrough))
636 // Analyze the branches, if any, at the end of the block.
637 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
638 SmallVector<MachineOperand, 4> Cond;
639 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
640 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) {
641 // If we couldn't analyze the branch, examine the last instruction.
642 // If the block doesn't end in a known control barrier, assume fallthrough
643 // is possible. The isPredicated check is needed because this code can be
644 // called during IfConversion, where an instruction which is normally a
645 // Barrier is predicated and thus no longer an actual control barrier.
646 return empty() || !back().isBarrier() || TII->isPredicated(&back());
649 // If there is no branch, control always falls through.
650 if (!TBB) return true;
652 // If there is some explicit branch to the fallthrough block, it can obviously
653 // reach, even though the branch should get folded to fall through implicitly.
654 if (MachineFunction::iterator(TBB) == Fallthrough ||
655 MachineFunction::iterator(FBB) == Fallthrough)
658 // If it's an unconditional branch to some block not the fall through, it
659 // doesn't fall through.
660 if (Cond.empty()) return false;
662 // Otherwise, if it is conditional and has no explicit false block, it falls
664 return FBB == nullptr;
668 MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) {
669 // Splitting the critical edge to a landing pad block is non-trivial. Don't do
670 // it in this generic function.
671 if (Succ->isLandingPad())
674 MachineFunction *MF = getParent();
675 DebugLoc dl; // FIXME: this is nowhere
677 // Performance might be harmed on HW that implements branching using exec mask
678 // where both sides of the branches are always executed.
679 if (MF->getTarget().requiresStructuredCFG())
682 // We may need to update this's terminator, but we can't do that if
683 // AnalyzeBranch fails. If this uses a jump table, we won't touch it.
684 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
685 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
686 SmallVector<MachineOperand, 4> Cond;
687 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond))
690 // Avoid bugpoint weirdness: A block may end with a conditional branch but
691 // jumps to the same MBB is either case. We have duplicate CFG edges in that
692 // case that we can't handle. Since this never happens in properly optimized
693 // code, just skip those edges.
694 if (TBB && TBB == FBB) {
695 DEBUG(dbgs() << "Won't split critical edge after degenerate BB#"
696 << getNumber() << '\n');
700 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
701 MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
702 DEBUG(dbgs() << "Splitting critical edge:"
703 " BB#" << getNumber()
704 << " -- BB#" << NMBB->getNumber()
705 << " -- BB#" << Succ->getNumber() << '\n');
707 LiveIntervals *LIS = P->getAnalysisIfAvailable<LiveIntervals>();
708 SlotIndexes *Indexes = P->getAnalysisIfAvailable<SlotIndexes>();
710 LIS->insertMBBInMaps(NMBB);
712 Indexes->insertMBBInMaps(NMBB);
714 // On some targets like Mips, branches may kill virtual registers. Make sure
715 // that LiveVariables is properly updated after updateTerminator replaces the
717 LiveVariables *LV = P->getAnalysisIfAvailable<LiveVariables>();
719 // Collect a list of virtual registers killed by the terminators.
720 SmallVector<unsigned, 4> KilledRegs;
722 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
724 MachineInstr *MI = I;
725 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
726 OE = MI->operands_end(); OI != OE; ++OI) {
727 if (!OI->isReg() || OI->getReg() == 0 ||
728 !OI->isUse() || !OI->isKill() || OI->isUndef())
730 unsigned Reg = OI->getReg();
731 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
732 LV->getVarInfo(Reg).removeKill(MI)) {
733 KilledRegs.push_back(Reg);
734 DEBUG(dbgs() << "Removing terminator kill: " << *MI);
735 OI->setIsKill(false);
740 SmallVector<unsigned, 4> UsedRegs;
742 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
744 MachineInstr *MI = I;
746 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
747 OE = MI->operands_end(); OI != OE; ++OI) {
748 if (!OI->isReg() || OI->getReg() == 0)
751 unsigned Reg = OI->getReg();
752 if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end())
753 UsedRegs.push_back(Reg);
758 ReplaceUsesOfBlockWith(Succ, NMBB);
760 // If updateTerminator() removes instructions, we need to remove them from
762 SmallVector<MachineInstr*, 4> Terminators;
764 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
766 Terminators.push_back(I);
772 SmallVector<MachineInstr*, 4> NewTerminators;
773 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
775 NewTerminators.push_back(I);
777 for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(),
778 E = Terminators.end(); I != E; ++I) {
779 if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) ==
780 NewTerminators.end())
781 Indexes->removeMachineInstrFromMaps(*I);
785 // Insert unconditional "jump Succ" instruction in NMBB if necessary.
786 NMBB->addSuccessor(Succ);
787 if (!NMBB->isLayoutSuccessor(Succ)) {
789 MF->getSubtarget().getInstrInfo()->InsertBranch(*NMBB, Succ, nullptr, Cond,
793 for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end();
795 // Some instructions may have been moved to NMBB by updateTerminator(),
796 // so we first remove any instruction that already has an index.
797 if (Indexes->hasIndex(I))
798 Indexes->removeMachineInstrFromMaps(I);
799 Indexes->insertMachineInstrInMaps(I);
804 // Fix PHI nodes in Succ so they refer to NMBB instead of this
805 for (MachineBasicBlock::instr_iterator
806 i = Succ->instr_begin(),e = Succ->instr_end();
807 i != e && i->isPHI(); ++i)
808 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
809 if (i->getOperand(ni+1).getMBB() == this)
810 i->getOperand(ni+1).setMBB(NMBB);
812 // Inherit live-ins from the successor
813 for (MachineBasicBlock::livein_iterator I = Succ->livein_begin(),
814 E = Succ->livein_end(); I != E; ++I)
817 // Update LiveVariables.
818 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
820 // Restore kills of virtual registers that were killed by the terminators.
821 while (!KilledRegs.empty()) {
822 unsigned Reg = KilledRegs.pop_back_val();
823 for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
824 if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false))
826 if (TargetRegisterInfo::isVirtualRegister(Reg))
827 LV->getVarInfo(Reg).Kills.push_back(I);
828 DEBUG(dbgs() << "Restored terminator kill: " << *I);
832 // Update relevant live-through information.
833 LV->addNewBlock(NMBB, this, Succ);
837 // After splitting the edge and updating SlotIndexes, live intervals may be
838 // in one of two situations, depending on whether this block was the last in
839 // the function. If the original block was the last in the function, all live
840 // intervals will end prior to the beginning of the new split block. If the
841 // original block was not at the end of the function, all live intervals will
842 // extend to the end of the new split block.
845 std::next(MachineFunction::iterator(NMBB)) == getParent()->end();
847 SlotIndex StartIndex = Indexes->getMBBEndIdx(this);
848 SlotIndex PrevIndex = StartIndex.getPrevSlot();
849 SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);
851 // Find the registers used from NMBB in PHIs in Succ.
852 SmallSet<unsigned, 8> PHISrcRegs;
853 for (MachineBasicBlock::instr_iterator
854 I = Succ->instr_begin(), E = Succ->instr_end();
855 I != E && I->isPHI(); ++I) {
856 for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
857 if (I->getOperand(ni+1).getMBB() == NMBB) {
858 MachineOperand &MO = I->getOperand(ni);
859 unsigned Reg = MO.getReg();
860 PHISrcRegs.insert(Reg);
864 LiveInterval &LI = LIS->getInterval(Reg);
865 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
866 assert(VNI && "PHI sources should be live out of their predecessors.");
867 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
872 MachineRegisterInfo *MRI = &getParent()->getRegInfo();
873 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
874 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
875 if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg))
878 LiveInterval &LI = LIS->getInterval(Reg);
879 if (!LI.liveAt(PrevIndex))
882 bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ));
883 if (isLiveOut && isLastMBB) {
884 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
885 assert(VNI && "LiveInterval should have VNInfo where it is live.");
886 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
887 } else if (!isLiveOut && !isLastMBB) {
888 LI.removeSegment(StartIndex, EndIndex);
892 // Update all intervals for registers whose uses may have been modified by
893 // updateTerminator().
894 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs);
897 if (MachineDominatorTree *MDT =
898 P->getAnalysisIfAvailable<MachineDominatorTree>())
899 MDT->recordSplitCriticalEdge(this, Succ, NMBB);
901 if (MachineLoopInfo *MLI = P->getAnalysisIfAvailable<MachineLoopInfo>())
902 if (MachineLoop *TIL = MLI->getLoopFor(this)) {
903 // If one or the other blocks were not in a loop, the new block is not
904 // either, and thus LI doesn't need to be updated.
905 if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) {
906 if (TIL == DestLoop) {
907 // Both in the same loop, the NMBB joins loop.
908 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
909 } else if (TIL->contains(DestLoop)) {
910 // Edge from an outer loop to an inner loop. Add to the outer loop.
911 TIL->addBasicBlockToLoop(NMBB, MLI->getBase());
912 } else if (DestLoop->contains(TIL)) {
913 // Edge from an inner loop to an outer loop. Add to the outer loop.
914 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
916 // Edge from two loops with no containment relation. Because these
917 // are natural loops, we know that the destination block must be the
918 // header of its loop (adding a branch into a loop elsewhere would
919 // create an irreducible loop).
920 assert(DestLoop->getHeader() == Succ &&
921 "Should not create irreducible loops!");
922 if (MachineLoop *P = DestLoop->getParentLoop())
923 P->addBasicBlockToLoop(NMBB, MLI->getBase());
931 /// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
932 /// neighboring instructions so the bundle won't be broken by removing MI.
933 static void unbundleSingleMI(MachineInstr *MI) {
934 // Removing the first instruction in a bundle.
935 if (MI->isBundledWithSucc() && !MI->isBundledWithPred())
936 MI->unbundleFromSucc();
937 // Removing the last instruction in a bundle.
938 if (MI->isBundledWithPred() && !MI->isBundledWithSucc())
939 MI->unbundleFromPred();
940 // If MI is not bundled, or if it is internal to a bundle, the neighbor flags
944 MachineBasicBlock::instr_iterator
945 MachineBasicBlock::erase(MachineBasicBlock::instr_iterator I) {
947 return Insts.erase(I);
950 MachineInstr *MachineBasicBlock::remove_instr(MachineInstr *MI) {
951 unbundleSingleMI(MI);
952 MI->clearFlag(MachineInstr::BundledPred);
953 MI->clearFlag(MachineInstr::BundledSucc);
954 return Insts.remove(MI);
957 MachineBasicBlock::instr_iterator
958 MachineBasicBlock::insert(instr_iterator I, MachineInstr *MI) {
959 assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() &&
960 "Cannot insert instruction with bundle flags");
961 // Set the bundle flags when inserting inside a bundle.
962 if (I != instr_end() && I->isBundledWithPred()) {
963 MI->setFlag(MachineInstr::BundledPred);
964 MI->setFlag(MachineInstr::BundledSucc);
966 return Insts.insert(I, MI);
969 /// removeFromParent - This method unlinks 'this' from the containing function,
970 /// and returns it, but does not delete it.
971 MachineBasicBlock *MachineBasicBlock::removeFromParent() {
972 assert(getParent() && "Not embedded in a function!");
973 getParent()->remove(this);
978 /// eraseFromParent - This method unlinks 'this' from the containing function,
980 void MachineBasicBlock::eraseFromParent() {
981 assert(getParent() && "Not embedded in a function!");
982 getParent()->erase(this);
986 /// ReplaceUsesOfBlockWith - Given a machine basic block that branched to
987 /// 'Old', change the code and CFG so that it branches to 'New' instead.
988 void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
989 MachineBasicBlock *New) {
990 assert(Old != New && "Cannot replace self with self!");
992 MachineBasicBlock::instr_iterator I = instr_end();
993 while (I != instr_begin()) {
995 if (!I->isTerminator()) break;
997 // Scan the operands of this machine instruction, replacing any uses of Old
999 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1000 if (I->getOperand(i).isMBB() &&
1001 I->getOperand(i).getMBB() == Old)
1002 I->getOperand(i).setMBB(New);
1005 // Update the successor information.
1006 replaceSuccessor(Old, New);
1009 /// CorrectExtraCFGEdges - Various pieces of code can cause excess edges in the
1010 /// CFG to be inserted. If we have proven that MBB can only branch to DestA and
1011 /// DestB, remove any other MBB successors from the CFG. DestA and DestB can be
1014 /// Besides DestA and DestB, retain other edges leading to LandingPads
1015 /// (currently there can be only one; we don't check or require that here).
1016 /// Note it is possible that DestA and/or DestB are LandingPads.
1017 bool MachineBasicBlock::CorrectExtraCFGEdges(MachineBasicBlock *DestA,
1018 MachineBasicBlock *DestB,
1020 // The values of DestA and DestB frequently come from a call to the
1021 // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial
1022 // values from there.
1024 // 1. If both DestA and DestB are null, then the block ends with no branches
1025 // (it falls through to its successor).
1026 // 2. If DestA is set, DestB is null, and isCond is false, then the block ends
1027 // with only an unconditional branch.
1028 // 3. If DestA is set, DestB is null, and isCond is true, then the block ends
1029 // with a conditional branch that falls through to a successor (DestB).
1030 // 4. If DestA and DestB is set and isCond is true, then the block ends with a
1031 // conditional branch followed by an unconditional branch. DestA is the
1032 // 'true' destination and DestB is the 'false' destination.
1034 bool Changed = false;
1036 MachineFunction::iterator FallThru =
1037 std::next(MachineFunction::iterator(this));
1039 if (!DestA && !DestB) {
1040 // Block falls through to successor.
1043 } else if (DestA && !DestB) {
1045 // Block ends in conditional jump that falls through to successor.
1048 assert(DestA && DestB && isCond &&
1049 "CFG in a bad state. Cannot correct CFG edges");
1052 // Remove superfluous edges. I.e., those which aren't destinations of this
1053 // basic block, duplicate edges, or landing pads.
1054 SmallPtrSet<const MachineBasicBlock*, 8> SeenMBBs;
1055 MachineBasicBlock::succ_iterator SI = succ_begin();
1056 while (SI != succ_end()) {
1057 const MachineBasicBlock *MBB = *SI;
1058 if (!SeenMBBs.insert(MBB).second ||
1059 (MBB != DestA && MBB != DestB && !MBB->isLandingPad())) {
1060 // This is a superfluous edge, remove it.
1061 SI = removeSuccessor(SI);
1071 /// findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping
1072 /// any DBG_VALUE instructions. Return UnknownLoc if there is none.
1074 MachineBasicBlock::findDebugLoc(instr_iterator MBBI) {
1076 instr_iterator E = instr_end();
1080 // Skip debug declarations, we don't want a DebugLoc from them.
1081 while (MBBI != E && MBBI->isDebugValue())
1084 DL = MBBI->getDebugLoc();
1088 /// getSuccWeight - Return weight of the edge from this block to MBB.
1090 uint32_t MachineBasicBlock::getSuccWeight(const_succ_iterator Succ) const {
1091 if (Weights.empty())
1094 return *getWeightIterator(Succ);
1097 /// Set successor weight of a given iterator.
1098 void MachineBasicBlock::setSuccWeight(succ_iterator I, uint32_t weight) {
1099 if (Weights.empty())
1101 *getWeightIterator(I) = weight;
1104 /// getWeightIterator - Return wight iterator corresonding to the I successor
1106 MachineBasicBlock::weight_iterator MachineBasicBlock::
1107 getWeightIterator(MachineBasicBlock::succ_iterator I) {
1108 assert(Weights.size() == Successors.size() && "Async weight list!");
1109 size_t index = std::distance(Successors.begin(), I);
1110 assert(index < Weights.size() && "Not a current successor!");
1111 return Weights.begin() + index;
1114 /// getWeightIterator - Return wight iterator corresonding to the I successor
1116 MachineBasicBlock::const_weight_iterator MachineBasicBlock::
1117 getWeightIterator(MachineBasicBlock::const_succ_iterator I) const {
1118 assert(Weights.size() == Successors.size() && "Async weight list!");
1119 const size_t index = std::distance(Successors.begin(), I);
1120 assert(index < Weights.size() && "Not a current successor!");
1121 return Weights.begin() + index;
1124 /// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
1125 /// as of just before "MI".
1127 /// Search is localised to a neighborhood of
1128 /// Neighborhood instructions before (searching for defs or kills) and N
1129 /// instructions after (searching just for defs) MI.
1130 MachineBasicBlock::LivenessQueryResult
1131 MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
1132 unsigned Reg, MachineInstr *MI,
1133 unsigned Neighborhood) {
1134 unsigned N = Neighborhood;
1135 MachineBasicBlock *MBB = MI->getParent();
1137 // Start by searching backwards from MI, looking for kills, reads or defs.
1139 MachineBasicBlock::iterator I(MI);
1140 // If this is the first insn in the block, don't search backwards.
1141 if (I != MBB->begin()) {
1145 MachineOperandIteratorBase::PhysRegInfo Analysis =
1146 MIOperands(I).analyzePhysReg(Reg, TRI);
1148 if (Analysis.Defines)
1149 // Outputs happen after inputs so they take precedence if both are
1151 return Analysis.DefinesDead ? LQR_Dead : LQR_Live;
1153 if (Analysis.Kills || Analysis.Clobbers)
1154 // Register killed, so isn't live.
1157 else if (Analysis.ReadsOverlap)
1158 // Defined or read without a previous kill - live.
1159 return Analysis.Reads ? LQR_Live : LQR_OverlappingLive;
1161 } while (I != MBB->begin() && --N > 0);
1164 // Did we get to the start of the block?
1165 if (I == MBB->begin()) {
1166 // If so, the register's state is definitely defined by the live-in state.
1167 for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true);
1168 RAI.isValid(); ++RAI) {
1169 if (MBB->isLiveIn(*RAI))
1170 return (*RAI == Reg) ? LQR_Live : LQR_OverlappingLive;
1178 // Try searching forwards from MI, looking for reads or defs.
1179 I = MachineBasicBlock::iterator(MI);
1180 // If this is the last insn in the block, don't search forwards.
1181 if (I != MBB->end()) {
1182 for (++I; I != MBB->end() && N > 0; ++I, --N) {
1183 MachineOperandIteratorBase::PhysRegInfo Analysis =
1184 MIOperands(I).analyzePhysReg(Reg, TRI);
1186 if (Analysis.ReadsOverlap)
1187 // Used, therefore must have been live.
1188 return (Analysis.Reads) ?
1189 LQR_Live : LQR_OverlappingLive;
1191 else if (Analysis.Clobbers || Analysis.Defines)
1192 // Defined (but not read) therefore cannot have been live.
1197 // At this point we have no idea of the liveness of the register.