1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "machine-cse"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/MachineDominators.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/ScopedHashTable.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
32 STATISTIC(NumCoalesces, "Number of copies coalesced");
33 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
34 STATISTIC(NumPhysCSEs,
35 "Number of physreg referencing common subexpr eliminated");
38 class MachineCSE : public MachineFunctionPass {
39 const TargetInstrInfo *TII;
40 const TargetRegisterInfo *TRI;
42 MachineDominatorTree *DT;
43 MachineRegisterInfo *MRI;
45 static char ID; // Pass identification
46 MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(5), CurrVN(0) {
47 initializeMachineCSEPass(*PassRegistry::getPassRegistry());
50 virtual bool runOnMachineFunction(MachineFunction &MF);
52 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
54 MachineFunctionPass::getAnalysisUsage(AU);
55 AU.addRequired<AliasAnalysis>();
56 AU.addPreservedID(MachineLoopInfoID);
57 AU.addRequired<MachineDominatorTree>();
58 AU.addPreserved<MachineDominatorTree>();
61 virtual void releaseMemory() {
67 const unsigned LookAheadLimit;
68 typedef ScopedHashTableScope<MachineInstr*, unsigned,
69 MachineInstrExpressionTrait> ScopeType;
70 DenseMap<MachineBasicBlock*, ScopeType*> ScopeMap;
71 ScopedHashTable<MachineInstr*, unsigned, MachineInstrExpressionTrait> VNT;
72 SmallVector<MachineInstr*, 64> Exps;
75 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
76 bool isPhysDefTriviallyDead(unsigned Reg,
77 MachineBasicBlock::const_iterator I,
78 MachineBasicBlock::const_iterator E) const ;
79 bool hasLivePhysRegDefUses(const MachineInstr *MI,
80 const MachineBasicBlock *MBB,
81 SmallSet<unsigned,8> &PhysRefs) const;
82 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
83 SmallSet<unsigned,8> &PhysRefs) const;
84 bool isCSECandidate(MachineInstr *MI);
85 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
86 MachineInstr *CSMI, MachineInstr *MI);
87 void EnterScope(MachineBasicBlock *MBB);
88 void ExitScope(MachineBasicBlock *MBB);
89 bool ProcessBlock(MachineBasicBlock *MBB);
90 void ExitScopeIfDone(MachineDomTreeNode *Node,
91 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
92 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap);
93 bool PerformCSE(MachineDomTreeNode *Node);
95 } // end anonymous namespace
97 char MachineCSE::ID = 0;
98 INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
99 "Machine Common Subexpression Elimination", false, false)
100 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
101 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
102 INITIALIZE_PASS_END(MachineCSE, "machine-cse",
103 "Machine Common Subexpression Elimination", false, false)
105 FunctionPass *llvm::createMachineCSEPass() { return new MachineCSE(); }
107 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
108 MachineBasicBlock *MBB) {
109 bool Changed = false;
110 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
111 MachineOperand &MO = MI->getOperand(i);
112 if (!MO.isReg() || !MO.isUse())
114 unsigned Reg = MO.getReg();
115 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
117 if (!MRI->hasOneNonDBGUse(Reg))
118 // Only coalesce single use copies. This ensure the copy will be
121 MachineInstr *DefMI = MRI->getVRegDef(Reg);
122 if (DefMI->getParent() != MBB)
124 if (!DefMI->isCopy())
126 unsigned SrcReg = DefMI->getOperand(1).getReg();
127 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
129 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
131 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg)))
133 DEBUG(dbgs() << "Coalescing: " << *DefMI);
134 DEBUG(dbgs() << "*** to: " << *MI);
136 MRI->clearKillFlags(SrcReg);
137 DefMI->eraseFromParent();
146 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
147 MachineBasicBlock::const_iterator I,
148 MachineBasicBlock::const_iterator E) const {
149 unsigned LookAheadLeft = LookAheadLimit;
150 while (LookAheadLeft) {
151 // Skip over dbg_value's.
152 while (I != E && I->isDebugValue())
156 // Reached end of block, register is obviously dead.
159 bool SeenDef = false;
160 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
161 const MachineOperand &MO = I->getOperand(i);
162 if (!MO.isReg() || !MO.getReg())
164 if (!TRI->regsOverlap(MO.getReg(), Reg))
172 // See a def of Reg (or an alias) before encountering any use, it's
182 /// hasLivePhysRegDefUses - Return true if the specified instruction read/write
183 /// physical registers (except for dead defs of physical registers). It also
184 /// returns the physical register def by reference if it's the only one and the
185 /// instruction does not uses a physical register.
186 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
187 const MachineBasicBlock *MBB,
188 SmallSet<unsigned,8> &PhysRefs) const {
189 MachineBasicBlock::const_iterator I = MI; I = llvm::next(I);
190 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
191 const MachineOperand &MO = MI->getOperand(i);
194 unsigned Reg = MO.getReg();
197 if (TargetRegisterInfo::isVirtualRegister(Reg))
199 // If the def is dead, it's ok. But the def may not marked "dead". That's
200 // common since this pass is run before livevariables. We can scan
201 // forward a few instructions and check if it is obviously dead.
203 (MO.isDead() || isPhysDefTriviallyDead(Reg, I, MBB->end())))
205 PhysRefs.insert(Reg);
206 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
207 PhysRefs.insert(*Alias);
210 return !PhysRefs.empty();
213 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
214 SmallSet<unsigned,8> &PhysRefs) const {
215 // For now conservatively returns false if the common subexpression is
216 // not in the same basic block as the given instruction.
217 MachineBasicBlock *MBB = MI->getParent();
218 if (CSMI->getParent() != MBB)
220 MachineBasicBlock::const_iterator I = CSMI; I = llvm::next(I);
221 MachineBasicBlock::const_iterator E = MI;
222 unsigned LookAheadLeft = LookAheadLimit;
223 while (LookAheadLeft) {
224 // Skip over dbg_value's.
225 while (I != E && I->isDebugValue())
231 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
232 const MachineOperand &MO = I->getOperand(i);
233 if (!MO.isReg() || !MO.isDef())
235 unsigned MOReg = MO.getReg();
236 if (TargetRegisterInfo::isVirtualRegister(MOReg))
238 if (PhysRefs.count(MOReg))
249 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
250 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
251 MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
255 if (MI->isCopyLike())
258 // Ignore stuff that we obviously can't move.
259 const TargetInstrDesc &TID = MI->getDesc();
260 if (TID.mayStore() || TID.isCall() || TID.isTerminator() ||
261 TID.hasUnmodeledSideEffects())
265 // Okay, this instruction does a load. As a refinement, we allow the target
266 // to decide whether the loaded value is actually a constant. If so, we can
267 // actually use it as a load.
268 if (!MI->isInvariantLoad(AA))
269 // FIXME: we should be able to hoist loads with no other side effects if
270 // there are no other instructions which can change memory in this loop.
271 // This is a trivial form of alias analysis.
277 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
278 /// common expression that defines Reg.
279 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
280 MachineInstr *CSMI, MachineInstr *MI) {
281 // FIXME: Heuristics that works around the lack the live range splitting.
283 // Heuristics #1: Don't cse "cheap" computating if the def is not local or in an
284 // immediate predecessor. We don't want to increase register pressure and end up
285 // causing other computation to be spilled.
286 if (MI->getDesc().isAsCheapAsAMove()) {
287 MachineBasicBlock *CSBB = CSMI->getParent();
288 MachineBasicBlock *BB = MI->getParent();
290 find(CSBB->succ_begin(), CSBB->succ_end(), BB) == CSBB->succ_end())
294 // Heuristics #2: If the expression doesn't not use a vr and the only use
295 // of the redundant computation are copies, do not cse.
296 bool HasVRegUse = false;
297 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
298 const MachineOperand &MO = MI->getOperand(i);
299 if (MO.isReg() && MO.isUse() && MO.getReg() &&
300 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
306 bool HasNonCopyUse = false;
307 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
308 E = MRI->use_nodbg_end(); I != E; ++I) {
309 MachineInstr *Use = &*I;
311 if (!Use->isCopyLike()) {
312 HasNonCopyUse = true;
320 // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
321 // it unless the defined value is already used in the BB of the new use.
323 SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
324 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg),
325 E = MRI->use_nodbg_end(); I != E; ++I) {
326 MachineInstr *Use = &*I;
327 HasPHI |= Use->isPHI();
328 CSBBs.insert(Use->getParent());
333 return CSBBs.count(MI->getParent());
336 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
337 DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
338 ScopeType *Scope = new ScopeType(VNT);
339 ScopeMap[MBB] = Scope;
342 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
343 DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
344 DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
345 assert(SI != ScopeMap.end());
350 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
351 bool Changed = false;
353 SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
354 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
355 MachineInstr *MI = &*I;
358 if (!isCSECandidate(MI))
361 bool FoundCSE = VNT.count(MI);
363 // Look for trivial copy coalescing opportunities.
364 if (PerformTrivialCoalescing(MI, MBB)) {
365 // After coalescing MI itself may become a copy.
366 if (MI->isCopyLike())
368 FoundCSE = VNT.count(MI);
371 // FIXME: commute commutable instructions?
373 // If the instruction defines physical registers and the values *may* be
374 // used, then it's not safe to replace it with a common subexpression.
375 // It's also not safe if the instruction uses physical registers.
376 SmallSet<unsigned,8> PhysRefs;
377 if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs)) {
380 // ... Unless the CS is local and it also defines the physical register
381 // which is not clobbered in between and the physical register uses
382 // were not clobbered.
383 unsigned CSVN = VNT.lookup(MI);
384 MachineInstr *CSMI = Exps[CSVN];
385 if (PhysRegDefsReach(CSMI, MI, PhysRefs))
390 VNT.insert(MI, CurrVN++);
395 // Found a common subexpression, eliminate it.
396 unsigned CSVN = VNT.lookup(MI);
397 MachineInstr *CSMI = Exps[CSVN];
398 DEBUG(dbgs() << "Examining: " << *MI);
399 DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
401 // Check if it's profitable to perform this CSE.
403 unsigned NumDefs = MI->getDesc().getNumDefs();
404 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
405 MachineOperand &MO = MI->getOperand(i);
406 if (!MO.isReg() || !MO.isDef())
408 unsigned OldReg = MO.getReg();
409 unsigned NewReg = CSMI->getOperand(i).getReg();
410 if (OldReg == NewReg)
412 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
413 TargetRegisterInfo::isVirtualRegister(NewReg) &&
414 "Do not CSE physical register defs!");
415 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
419 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
423 // Actually perform the elimination.
425 for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
426 MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
427 MRI->clearKillFlags(CSEPairs[i].second);
429 MI->eraseFromParent();
431 if (!PhysRefs.empty())
434 DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
435 VNT.insert(MI, CurrVN++);
444 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
445 /// dominator tree node if its a leaf or all of its children are done. Walk
446 /// up the dominator tree to destroy ancestors which are now done.
448 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
449 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
450 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap) {
451 if (OpenChildren[Node])
455 ExitScope(Node->getBlock());
457 // Now traverse upwards to pop ancestors whose offsprings are all done.
458 while (MachineDomTreeNode *Parent = ParentMap[Node]) {
459 unsigned Left = --OpenChildren[Parent];
462 ExitScope(Parent->getBlock());
467 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
468 SmallVector<MachineDomTreeNode*, 32> Scopes;
469 SmallVector<MachineDomTreeNode*, 8> WorkList;
470 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> ParentMap;
471 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
475 // Perform a DFS walk to determine the order of visit.
476 WorkList.push_back(Node);
478 Node = WorkList.pop_back_val();
479 Scopes.push_back(Node);
480 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
481 unsigned NumChildren = Children.size();
482 OpenChildren[Node] = NumChildren;
483 for (unsigned i = 0; i != NumChildren; ++i) {
484 MachineDomTreeNode *Child = Children[i];
485 ParentMap[Child] = Node;
486 WorkList.push_back(Child);
488 } while (!WorkList.empty());
491 bool Changed = false;
492 for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
493 MachineDomTreeNode *Node = Scopes[i];
494 MachineBasicBlock *MBB = Node->getBlock();
496 Changed |= ProcessBlock(MBB);
497 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
498 ExitScopeIfDone(Node, OpenChildren, ParentMap);
504 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
505 TII = MF.getTarget().getInstrInfo();
506 TRI = MF.getTarget().getRegisterInfo();
507 MRI = &MF.getRegInfo();
508 AA = &getAnalysis<AliasAnalysis>();
509 DT = &getAnalysis<MachineDominatorTree>();
510 return PerformCSE(DT->getRootNode());