1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "machine-cse"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/MachineDominators.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/ScopedHashTable.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/RecyclingAllocator.h"
31 STATISTIC(NumCoalesces, "Number of copies coalesced");
32 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
33 STATISTIC(NumPhysCSEs,
34 "Number of physreg referencing common subexpr eliminated");
35 STATISTIC(NumCrossBBCSEs,
36 "Number of cross-MBB physreg referencing CS eliminated");
37 STATISTIC(NumCommutes, "Number of copies coalesced after commuting");
40 class MachineCSE : public MachineFunctionPass {
41 const TargetInstrInfo *TII;
42 const TargetRegisterInfo *TRI;
44 MachineDominatorTree *DT;
45 MachineRegisterInfo *MRI;
47 static char ID; // Pass identification
48 MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(5), CurrVN(0) {
49 initializeMachineCSEPass(*PassRegistry::getPassRegistry());
52 virtual bool runOnMachineFunction(MachineFunction &MF);
54 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
56 MachineFunctionPass::getAnalysisUsage(AU);
57 AU.addRequired<AliasAnalysis>();
58 AU.addPreservedID(MachineLoopInfoID);
59 AU.addRequired<MachineDominatorTree>();
60 AU.addPreserved<MachineDominatorTree>();
63 virtual void releaseMemory() {
69 const unsigned LookAheadLimit;
70 typedef RecyclingAllocator<BumpPtrAllocator,
71 ScopedHashTableVal<MachineInstr*, unsigned> > AllocatorTy;
72 typedef ScopedHashTable<MachineInstr*, unsigned,
73 MachineInstrExpressionTrait, AllocatorTy> ScopedHTType;
74 typedef ScopedHTType::ScopeTy ScopeType;
75 DenseMap<MachineBasicBlock*, ScopeType*> ScopeMap;
77 SmallVector<MachineInstr*, 64> Exps;
80 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
81 bool isPhysDefTriviallyDead(unsigned Reg,
82 MachineBasicBlock::const_iterator I,
83 MachineBasicBlock::const_iterator E) const;
84 bool hasLivePhysRegDefUses(const MachineInstr *MI,
85 const MachineBasicBlock *MBB,
86 SmallSet<unsigned,8> &PhysRefs,
87 SmallVector<unsigned,2> &PhysDefs) const;
88 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
89 SmallSet<unsigned,8> &PhysRefs,
90 SmallVector<unsigned,2> &PhysDefs,
91 bool &NonLocal) const;
92 bool isCSECandidate(MachineInstr *MI);
93 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
94 MachineInstr *CSMI, MachineInstr *MI);
95 void EnterScope(MachineBasicBlock *MBB);
96 void ExitScope(MachineBasicBlock *MBB);
97 bool ProcessBlock(MachineBasicBlock *MBB);
98 void ExitScopeIfDone(MachineDomTreeNode *Node,
99 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren);
100 bool PerformCSE(MachineDomTreeNode *Node);
102 } // end anonymous namespace
104 char MachineCSE::ID = 0;
105 char &llvm::MachineCSEID = MachineCSE::ID;
106 INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
107 "Machine Common Subexpression Elimination", false, false)
108 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
109 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
110 INITIALIZE_PASS_END(MachineCSE, "machine-cse",
111 "Machine Common Subexpression Elimination", false, false)
113 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
114 MachineBasicBlock *MBB) {
115 bool Changed = false;
116 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
117 MachineOperand &MO = MI->getOperand(i);
118 if (!MO.isReg() || !MO.isUse())
120 unsigned Reg = MO.getReg();
121 if (!TargetRegisterInfo::isVirtualRegister(Reg))
123 if (!MRI->hasOneNonDBGUse(Reg))
124 // Only coalesce single use copies. This ensure the copy will be
127 MachineInstr *DefMI = MRI->getVRegDef(Reg);
128 if (DefMI->getParent() != MBB)
130 if (!DefMI->isCopy())
132 unsigned SrcReg = DefMI->getOperand(1).getReg();
133 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
135 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
137 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg)))
139 DEBUG(dbgs() << "Coalescing: " << *DefMI);
140 DEBUG(dbgs() << "*** to: " << *MI);
142 MRI->clearKillFlags(SrcReg);
143 DefMI->eraseFromParent();
152 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
153 MachineBasicBlock::const_iterator I,
154 MachineBasicBlock::const_iterator E) const {
155 unsigned LookAheadLeft = LookAheadLimit;
156 while (LookAheadLeft) {
157 // Skip over dbg_value's.
158 while (I != E && I->isDebugValue())
162 // Reached end of block, register is obviously dead.
165 bool SeenDef = false;
166 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
167 const MachineOperand &MO = I->getOperand(i);
168 if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
170 if (!MO.isReg() || !MO.getReg())
172 if (!TRI->regsOverlap(MO.getReg(), Reg))
180 // See a def of Reg (or an alias) before encountering any use, it's
190 /// hasLivePhysRegDefUses - Return true if the specified instruction read/write
191 /// physical registers (except for dead defs of physical registers). It also
192 /// returns the physical register def by reference if it's the only one and the
193 /// instruction does not uses a physical register.
194 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
195 const MachineBasicBlock *MBB,
196 SmallSet<unsigned,8> &PhysRefs,
197 SmallVector<unsigned,2> &PhysDefs) const{
198 MachineBasicBlock::const_iterator I = MI; I = llvm::next(I);
199 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
200 const MachineOperand &MO = MI->getOperand(i);
203 unsigned Reg = MO.getReg();
206 if (TargetRegisterInfo::isVirtualRegister(Reg))
208 // If the def is dead, it's ok. But the def may not marked "dead". That's
209 // common since this pass is run before livevariables. We can scan
210 // forward a few instructions and check if it is obviously dead.
212 (MO.isDead() || isPhysDefTriviallyDead(Reg, I, MBB->end())))
214 // Reading constant physregs is ok.
215 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
216 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
217 PhysRefs.insert(*AI);
219 PhysDefs.push_back(Reg);
222 return !PhysRefs.empty();
225 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
226 SmallSet<unsigned,8> &PhysRefs,
227 SmallVector<unsigned,2> &PhysDefs,
228 bool &NonLocal) const {
229 // For now conservatively returns false if the common subexpression is
230 // not in the same basic block as the given instruction. The only exception
231 // is if the common subexpression is in the sole predecessor block.
232 const MachineBasicBlock *MBB = MI->getParent();
233 const MachineBasicBlock *CSMBB = CSMI->getParent();
235 bool CrossMBB = false;
237 if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
240 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
241 if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i]))
242 // Avoid extending live range of physical registers if they are
243 //allocatable or reserved.
248 MachineBasicBlock::const_iterator I = CSMI; I = llvm::next(I);
249 MachineBasicBlock::const_iterator E = MI;
250 MachineBasicBlock::const_iterator EE = CSMBB->end();
251 unsigned LookAheadLeft = LookAheadLimit;
252 while (LookAheadLeft) {
253 // Skip over dbg_value's.
254 while (I != E && I != EE && I->isDebugValue())
258 assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
270 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
271 const MachineOperand &MO = I->getOperand(i);
272 // RegMasks go on instructions like calls that clobber lots of physregs.
273 // Don't attempt to CSE across such an instruction.
276 if (!MO.isReg() || !MO.isDef())
278 unsigned MOReg = MO.getReg();
279 if (TargetRegisterInfo::isVirtualRegister(MOReg))
281 if (PhysRefs.count(MOReg))
292 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
293 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
294 MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
298 if (MI->isCopyLike())
301 // Ignore stuff that we obviously can't move.
302 if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
303 MI->hasUnmodeledSideEffects())
307 // Okay, this instruction does a load. As a refinement, we allow the target
308 // to decide whether the loaded value is actually a constant. If so, we can
309 // actually use it as a load.
310 if (!MI->isInvariantLoad(AA))
311 // FIXME: we should be able to hoist loads with no other side effects if
312 // there are no other instructions which can change memory in this loop.
313 // This is a trivial form of alias analysis.
319 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
320 /// common expression that defines Reg.
321 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
322 MachineInstr *CSMI, MachineInstr *MI) {
323 // FIXME: Heuristics that works around the lack the live range splitting.
325 // If CSReg is used at all uses of Reg, CSE should not increase register
326 // pressure of CSReg.
327 bool MayIncreasePressure = true;
328 if (TargetRegisterInfo::isVirtualRegister(CSReg) &&
329 TargetRegisterInfo::isVirtualRegister(Reg)) {
330 MayIncreasePressure = false;
331 SmallPtrSet<MachineInstr*, 8> CSUses;
332 for (MachineRegisterInfo::use_nodbg_iterator I =MRI->use_nodbg_begin(CSReg),
333 E = MRI->use_nodbg_end(); I != E; ++I) {
334 MachineInstr *Use = &*I;
337 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
338 E = MRI->use_nodbg_end(); I != E; ++I) {
339 MachineInstr *Use = &*I;
340 if (!CSUses.count(Use)) {
341 MayIncreasePressure = true;
346 if (!MayIncreasePressure) return true;
348 // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
349 // an immediate predecessor. We don't want to increase register pressure and
350 // end up causing other computation to be spilled.
351 if (MI->isAsCheapAsAMove()) {
352 MachineBasicBlock *CSBB = CSMI->getParent();
353 MachineBasicBlock *BB = MI->getParent();
354 if (CSBB != BB && !CSBB->isSuccessor(BB))
358 // Heuristics #2: If the expression doesn't not use a vr and the only use
359 // of the redundant computation are copies, do not cse.
360 bool HasVRegUse = false;
361 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
362 const MachineOperand &MO = MI->getOperand(i);
363 if (MO.isReg() && MO.isUse() &&
364 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
370 bool HasNonCopyUse = false;
371 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
372 E = MRI->use_nodbg_end(); I != E; ++I) {
373 MachineInstr *Use = &*I;
375 if (!Use->isCopyLike()) {
376 HasNonCopyUse = true;
384 // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
385 // it unless the defined value is already used in the BB of the new use.
387 SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
388 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg),
389 E = MRI->use_nodbg_end(); I != E; ++I) {
390 MachineInstr *Use = &*I;
391 HasPHI |= Use->isPHI();
392 CSBBs.insert(Use->getParent());
397 return CSBBs.count(MI->getParent());
400 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
401 DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
402 ScopeType *Scope = new ScopeType(VNT);
403 ScopeMap[MBB] = Scope;
406 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
407 DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
408 DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
409 assert(SI != ScopeMap.end());
414 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
415 bool Changed = false;
417 SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
418 SmallVector<unsigned, 2> ImplicitDefsToUpdate;
419 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
420 MachineInstr *MI = &*I;
423 if (!isCSECandidate(MI))
426 bool FoundCSE = VNT.count(MI);
428 // Look for trivial copy coalescing opportunities.
429 if (PerformTrivialCoalescing(MI, MBB)) {
432 // After coalescing MI itself may become a copy.
433 if (MI->isCopyLike())
435 FoundCSE = VNT.count(MI);
439 // Commute commutable instructions.
440 bool Commuted = false;
441 if (!FoundCSE && MI->isCommutable()) {
442 MachineInstr *NewMI = TII->commuteInstruction(MI);
445 FoundCSE = VNT.count(NewMI);
447 // New instruction. It doesn't need to be kept.
448 NewMI->eraseFromParent();
450 } else if (!FoundCSE)
451 // MI was changed but it didn't help, commute it back!
452 (void)TII->commuteInstruction(MI);
456 // If the instruction defines physical registers and the values *may* be
457 // used, then it's not safe to replace it with a common subexpression.
458 // It's also not safe if the instruction uses physical registers.
459 bool CrossMBBPhysDef = false;
460 SmallSet<unsigned, 8> PhysRefs;
461 SmallVector<unsigned, 2> PhysDefs;
462 if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs, PhysDefs)) {
465 // ... Unless the CS is local or is in the sole predecessor block
466 // and it also defines the physical register which is not clobbered
467 // in between and the physical register uses were not clobbered.
468 unsigned CSVN = VNT.lookup(MI);
469 MachineInstr *CSMI = Exps[CSVN];
470 if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
475 VNT.insert(MI, CurrVN++);
480 // Found a common subexpression, eliminate it.
481 unsigned CSVN = VNT.lookup(MI);
482 MachineInstr *CSMI = Exps[CSVN];
483 DEBUG(dbgs() << "Examining: " << *MI);
484 DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
486 // Check if it's profitable to perform this CSE.
488 unsigned NumDefs = MI->getDesc().getNumDefs() +
489 MI->getDesc().getNumImplicitDefs();
491 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
492 MachineOperand &MO = MI->getOperand(i);
493 if (!MO.isReg() || !MO.isDef())
495 unsigned OldReg = MO.getReg();
496 unsigned NewReg = CSMI->getOperand(i).getReg();
498 // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
499 // we should make sure it is not dead at CSMI.
500 if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
501 ImplicitDefsToUpdate.push_back(i);
502 if (OldReg == NewReg) {
507 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
508 TargetRegisterInfo::isVirtualRegister(NewReg) &&
509 "Do not CSE physical register defs!");
511 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
512 DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
517 // Don't perform CSE if the result of the old instruction cannot exist
518 // within the register class of the new instruction.
519 const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
520 if (!MRI->constrainRegClass(NewReg, OldRC)) {
521 DEBUG(dbgs() << "*** Not the same register class, avoid CSE!\n");
526 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
530 // Actually perform the elimination.
532 for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
533 MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
534 MRI->clearKillFlags(CSEPairs[i].second);
537 // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
538 // we should make sure it is not dead at CSMI.
539 for (unsigned i = 0, e = ImplicitDefsToUpdate.size(); i != e; ++i)
540 CSMI->getOperand(ImplicitDefsToUpdate[i]).setIsDead(false);
542 if (CrossMBBPhysDef) {
543 // Add physical register defs now coming in from a predecessor to MBB
545 while (!PhysDefs.empty()) {
546 unsigned LiveIn = PhysDefs.pop_back_val();
547 if (!MBB->isLiveIn(LiveIn))
548 MBB->addLiveIn(LiveIn);
553 MI->eraseFromParent();
555 if (!PhysRefs.empty())
561 VNT.insert(MI, CurrVN++);
565 ImplicitDefsToUpdate.clear();
571 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
572 /// dominator tree node if its a leaf or all of its children are done. Walk
573 /// up the dominator tree to destroy ancestors which are now done.
575 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
576 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren) {
577 if (OpenChildren[Node])
581 ExitScope(Node->getBlock());
583 // Now traverse upwards to pop ancestors whose offsprings are all done.
584 while (MachineDomTreeNode *Parent = Node->getIDom()) {
585 unsigned Left = --OpenChildren[Parent];
588 ExitScope(Parent->getBlock());
593 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
594 SmallVector<MachineDomTreeNode*, 32> Scopes;
595 SmallVector<MachineDomTreeNode*, 8> WorkList;
596 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
600 // Perform a DFS walk to determine the order of visit.
601 WorkList.push_back(Node);
603 Node = WorkList.pop_back_val();
604 Scopes.push_back(Node);
605 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
606 unsigned NumChildren = Children.size();
607 OpenChildren[Node] = NumChildren;
608 for (unsigned i = 0; i != NumChildren; ++i) {
609 MachineDomTreeNode *Child = Children[i];
610 WorkList.push_back(Child);
612 } while (!WorkList.empty());
615 bool Changed = false;
616 for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
617 MachineDomTreeNode *Node = Scopes[i];
618 MachineBasicBlock *MBB = Node->getBlock();
620 Changed |= ProcessBlock(MBB);
621 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
622 ExitScopeIfDone(Node, OpenChildren);
628 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
629 TII = MF.getTarget().getInstrInfo();
630 TRI = MF.getTarget().getRegisterInfo();
631 MRI = &MF.getRegInfo();
632 AA = &getAnalysis<AliasAnalysis>();
633 DT = &getAnalysis<MachineDominatorTree>();
634 return PerformCSE(DT->getRootNode());