1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "machine-cse"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/MachineDominators.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/ScopedHashTable.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/RecyclingAllocator.h"
31 STATISTIC(NumCoalesces, "Number of copies coalesced");
32 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
33 STATISTIC(NumPhysCSEs,
34 "Number of physreg referencing common subexpr eliminated");
35 STATISTIC(NumCrossBBCSEs,
36 "Number of cross-MBB physreg referencing CS eliminated");
37 STATISTIC(NumCommutes, "Number of copies coalesced after commuting");
40 class MachineCSE : public MachineFunctionPass {
41 const TargetInstrInfo *TII;
42 const TargetRegisterInfo *TRI;
44 MachineDominatorTree *DT;
45 MachineRegisterInfo *MRI;
47 static char ID; // Pass identification
48 MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(5), CurrVN(0) {
49 initializeMachineCSEPass(*PassRegistry::getPassRegistry());
52 virtual bool runOnMachineFunction(MachineFunction &MF);
54 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
56 MachineFunctionPass::getAnalysisUsage(AU);
57 AU.addRequired<AliasAnalysis>();
58 AU.addPreservedID(MachineLoopInfoID);
59 AU.addRequired<MachineDominatorTree>();
60 AU.addPreserved<MachineDominatorTree>();
63 virtual void releaseMemory() {
69 const unsigned LookAheadLimit;
70 typedef RecyclingAllocator<BumpPtrAllocator,
71 ScopedHashTableVal<MachineInstr*, unsigned> > AllocatorTy;
72 typedef ScopedHashTable<MachineInstr*, unsigned,
73 MachineInstrExpressionTrait, AllocatorTy> ScopedHTType;
74 typedef ScopedHTType::ScopeTy ScopeType;
75 DenseMap<MachineBasicBlock*, ScopeType*> ScopeMap;
77 SmallVector<MachineInstr*, 64> Exps;
80 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
81 bool isPhysDefTriviallyDead(unsigned Reg,
82 MachineBasicBlock::const_iterator I,
83 MachineBasicBlock::const_iterator E) const ;
84 bool hasLivePhysRegDefUses(const MachineInstr *MI,
85 const MachineBasicBlock *MBB,
86 SmallSet<unsigned,8> &PhysRefs,
87 SmallVector<unsigned,2> &PhysDefs) const;
88 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
89 SmallSet<unsigned,8> &PhysRefs,
90 SmallVector<unsigned,2> &PhysDefs,
91 bool &NonLocal) const;
92 bool isCSECandidate(MachineInstr *MI);
93 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
94 MachineInstr *CSMI, MachineInstr *MI);
95 void EnterScope(MachineBasicBlock *MBB);
96 void ExitScope(MachineBasicBlock *MBB);
97 bool ProcessBlock(MachineBasicBlock *MBB);
98 void ExitScopeIfDone(MachineDomTreeNode *Node,
99 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
100 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap);
101 bool PerformCSE(MachineDomTreeNode *Node);
103 } // end anonymous namespace
105 char MachineCSE::ID = 0;
106 INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
107 "Machine Common Subexpression Elimination", false, false)
108 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
109 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
110 INITIALIZE_PASS_END(MachineCSE, "machine-cse",
111 "Machine Common Subexpression Elimination", false, false)
113 FunctionPass *llvm::createMachineCSEPass() { return new MachineCSE(); }
115 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
116 MachineBasicBlock *MBB) {
117 bool Changed = false;
118 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
119 MachineOperand &MO = MI->getOperand(i);
120 if (!MO.isReg() || !MO.isUse())
122 unsigned Reg = MO.getReg();
123 if (!TargetRegisterInfo::isVirtualRegister(Reg))
125 if (!MRI->hasOneNonDBGUse(Reg))
126 // Only coalesce single use copies. This ensure the copy will be
129 MachineInstr *DefMI = MRI->getVRegDef(Reg);
130 if (DefMI->getParent() != MBB)
132 if (!DefMI->isCopy())
134 unsigned SrcReg = DefMI->getOperand(1).getReg();
135 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
137 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
139 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg)))
141 DEBUG(dbgs() << "Coalescing: " << *DefMI);
142 DEBUG(dbgs() << "*** to: " << *MI);
144 MRI->clearKillFlags(SrcReg);
145 DefMI->eraseFromParent();
154 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
155 MachineBasicBlock::const_iterator I,
156 MachineBasicBlock::const_iterator E) const {
157 unsigned LookAheadLeft = LookAheadLimit;
158 while (LookAheadLeft) {
159 // Skip over dbg_value's.
160 while (I != E && I->isDebugValue())
164 // Reached end of block, register is obviously dead.
167 bool SeenDef = false;
168 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
169 const MachineOperand &MO = I->getOperand(i);
170 if (!MO.isReg() || !MO.getReg())
172 if (!TRI->regsOverlap(MO.getReg(), Reg))
180 // See a def of Reg (or an alias) before encountering any use, it's
190 /// hasLivePhysRegDefUses - Return true if the specified instruction read/write
191 /// physical registers (except for dead defs of physical registers). It also
192 /// returns the physical register def by reference if it's the only one and the
193 /// instruction does not uses a physical register.
194 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
195 const MachineBasicBlock *MBB,
196 SmallSet<unsigned,8> &PhysRefs,
197 SmallVector<unsigned,2> &PhysDefs) const{
198 MachineBasicBlock::const_iterator I = MI; I = llvm::next(I);
199 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
200 const MachineOperand &MO = MI->getOperand(i);
203 unsigned Reg = MO.getReg();
206 if (TargetRegisterInfo::isVirtualRegister(Reg))
208 // If the def is dead, it's ok. But the def may not marked "dead". That's
209 // common since this pass is run before livevariables. We can scan
210 // forward a few instructions and check if it is obviously dead.
212 (MO.isDead() || isPhysDefTriviallyDead(Reg, I, MBB->end())))
214 PhysRefs.insert(Reg);
216 PhysDefs.push_back(Reg);
217 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
218 PhysRefs.insert(*Alias);
221 return !PhysRefs.empty();
224 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
225 SmallSet<unsigned,8> &PhysRefs,
226 SmallVector<unsigned,2> &PhysDefs,
227 bool &NonLocal) const {
228 // For now conservatively returns false if the common subexpression is
229 // not in the same basic block as the given instruction. The only exception
230 // is if the common subexpression is in the sole predecessor block.
231 const MachineBasicBlock *MBB = MI->getParent();
232 const MachineBasicBlock *CSMBB = CSMI->getParent();
234 bool CrossMBB = false;
236 if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
239 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
240 if (TRI->isInAllocatableClass(PhysDefs[i]))
241 // Avoid extending live range of physical registers unless
242 // they are unallocatable.
247 MachineBasicBlock::const_iterator I = CSMI; I = llvm::next(I);
248 MachineBasicBlock::const_iterator E = MI;
249 MachineBasicBlock::const_iterator EE = CSMBB->end();
250 unsigned LookAheadLeft = LookAheadLimit;
251 while (LookAheadLeft) {
252 // Skip over dbg_value's.
253 while (I != E && I != EE && I->isDebugValue())
257 assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
269 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
270 const MachineOperand &MO = I->getOperand(i);
271 if (!MO.isReg() || !MO.isDef())
273 unsigned MOReg = MO.getReg();
274 if (TargetRegisterInfo::isVirtualRegister(MOReg))
276 if (PhysRefs.count(MOReg))
287 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
288 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
289 MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
293 if (MI->isCopyLike())
296 // Ignore stuff that we obviously can't move.
297 if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
298 MI->hasUnmodeledSideEffects())
302 // Okay, this instruction does a load. As a refinement, we allow the target
303 // to decide whether the loaded value is actually a constant. If so, we can
304 // actually use it as a load.
305 if (!MI->isInvariantLoad(AA))
306 // FIXME: we should be able to hoist loads with no other side effects if
307 // there are no other instructions which can change memory in this loop.
308 // This is a trivial form of alias analysis.
314 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
315 /// common expression that defines Reg.
316 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
317 MachineInstr *CSMI, MachineInstr *MI) {
318 // FIXME: Heuristics that works around the lack the live range splitting.
320 // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
321 // an immediate predecessor. We don't want to increase register pressure and
322 // end up causing other computation to be spilled.
323 if (MI->isAsCheapAsAMove()) {
324 MachineBasicBlock *CSBB = CSMI->getParent();
325 MachineBasicBlock *BB = MI->getParent();
326 if (CSBB != BB && !CSBB->isSuccessor(BB))
330 // Heuristics #2: If the expression doesn't not use a vr and the only use
331 // of the redundant computation are copies, do not cse.
332 bool HasVRegUse = false;
333 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
334 const MachineOperand &MO = MI->getOperand(i);
335 if (MO.isReg() && MO.isUse() &&
336 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
342 bool HasNonCopyUse = false;
343 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
344 E = MRI->use_nodbg_end(); I != E; ++I) {
345 MachineInstr *Use = &*I;
347 if (!Use->isCopyLike()) {
348 HasNonCopyUse = true;
356 // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
357 // it unless the defined value is already used in the BB of the new use.
359 SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
360 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg),
361 E = MRI->use_nodbg_end(); I != E; ++I) {
362 MachineInstr *Use = &*I;
363 HasPHI |= Use->isPHI();
364 CSBBs.insert(Use->getParent());
369 return CSBBs.count(MI->getParent());
372 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
373 DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
374 ScopeType *Scope = new ScopeType(VNT);
375 ScopeMap[MBB] = Scope;
378 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
379 DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
380 DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
381 assert(SI != ScopeMap.end());
386 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
387 bool Changed = false;
389 SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
390 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
391 MachineInstr *MI = &*I;
394 if (!isCSECandidate(MI))
397 bool FoundCSE = VNT.count(MI);
399 // Look for trivial copy coalescing opportunities.
400 if (PerformTrivialCoalescing(MI, MBB)) {
403 // After coalescing MI itself may become a copy.
404 if (MI->isCopyLike())
406 FoundCSE = VNT.count(MI);
410 // Commute commutable instructions.
411 bool Commuted = false;
412 if (!FoundCSE && MI->isCommutable()) {
413 MachineInstr *NewMI = TII->commuteInstruction(MI);
416 FoundCSE = VNT.count(NewMI);
418 // New instruction. It doesn't need to be kept.
419 NewMI->eraseFromParent();
421 } else if (!FoundCSE)
422 // MI was changed but it didn't help, commute it back!
423 (void)TII->commuteInstruction(MI);
427 // If the instruction defines physical registers and the values *may* be
428 // used, then it's not safe to replace it with a common subexpression.
429 // It's also not safe if the instruction uses physical registers.
430 bool CrossMBBPhysDef = false;
431 SmallSet<unsigned,8> PhysRefs;
432 SmallVector<unsigned, 2> PhysDefs;
433 if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs, PhysDefs)) {
436 // ... Unless the CS is local or is in the sole predecessor block
437 // and it also defines the physical register which is not clobbered
438 // in between and the physical register uses were not clobbered.
439 unsigned CSVN = VNT.lookup(MI);
440 MachineInstr *CSMI = Exps[CSVN];
441 if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
446 VNT.insert(MI, CurrVN++);
451 // Found a common subexpression, eliminate it.
452 unsigned CSVN = VNT.lookup(MI);
453 MachineInstr *CSMI = Exps[CSVN];
454 DEBUG(dbgs() << "Examining: " << *MI);
455 DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
457 // Check if it's profitable to perform this CSE.
459 unsigned NumDefs = MI->getDesc().getNumDefs();
460 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
461 MachineOperand &MO = MI->getOperand(i);
462 if (!MO.isReg() || !MO.isDef())
464 unsigned OldReg = MO.getReg();
465 unsigned NewReg = CSMI->getOperand(i).getReg();
466 if (OldReg == NewReg)
469 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
470 TargetRegisterInfo::isVirtualRegister(NewReg) &&
471 "Do not CSE physical register defs!");
473 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
478 // Don't perform CSE if the result of the old instruction cannot exist
479 // within the register class of the new instruction.
480 const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
481 if (!MRI->constrainRegClass(NewReg, OldRC)) {
486 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
490 // Actually perform the elimination.
492 for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
493 MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
494 MRI->clearKillFlags(CSEPairs[i].second);
497 if (CrossMBBPhysDef) {
498 // Add physical register defs now coming in from a predecessor to MBB
500 while (!PhysDefs.empty()) {
501 unsigned LiveIn = PhysDefs.pop_back_val();
502 if (!MBB->isLiveIn(LiveIn))
503 MBB->addLiveIn(LiveIn);
508 MI->eraseFromParent();
510 if (!PhysRefs.empty())
516 DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
517 VNT.insert(MI, CurrVN++);
526 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
527 /// dominator tree node if its a leaf or all of its children are done. Walk
528 /// up the dominator tree to destroy ancestors which are now done.
530 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
531 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
532 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap) {
533 if (OpenChildren[Node])
537 ExitScope(Node->getBlock());
539 // Now traverse upwards to pop ancestors whose offsprings are all done.
540 while (MachineDomTreeNode *Parent = ParentMap[Node]) {
541 unsigned Left = --OpenChildren[Parent];
544 ExitScope(Parent->getBlock());
549 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
550 SmallVector<MachineDomTreeNode*, 32> Scopes;
551 SmallVector<MachineDomTreeNode*, 8> WorkList;
552 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> ParentMap;
553 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
557 // Perform a DFS walk to determine the order of visit.
558 WorkList.push_back(Node);
560 Node = WorkList.pop_back_val();
561 Scopes.push_back(Node);
562 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
563 unsigned NumChildren = Children.size();
564 OpenChildren[Node] = NumChildren;
565 for (unsigned i = 0; i != NumChildren; ++i) {
566 MachineDomTreeNode *Child = Children[i];
567 ParentMap[Child] = Node;
568 WorkList.push_back(Child);
570 } while (!WorkList.empty());
573 bool Changed = false;
574 for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
575 MachineDomTreeNode *Node = Scopes[i];
576 MachineBasicBlock *MBB = Node->getBlock();
578 Changed |= ProcessBlock(MBB);
579 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
580 ExitScopeIfDone(Node, OpenChildren, ParentMap);
586 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
587 TII = MF.getTarget().getInstrInfo();
588 TRI = MF.getTarget().getRegisterInfo();
589 MRI = &MF.getRegInfo();
590 AA = &getAnalysis<AliasAnalysis>();
591 DT = &getAnalysis<MachineDominatorTree>();
592 return PerformCSE(DT->getRootNode());