1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "machine-cse"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/MachineDominators.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/ScopedHashTable.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
31 STATISTIC(NumCoalesces, "Number of copies coalesced");
32 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
33 STATISTIC(NumPhysCSEs, "Number of phyreg defining common subexpr eliminated");
36 class MachineCSE : public MachineFunctionPass {
37 const TargetInstrInfo *TII;
38 const TargetRegisterInfo *TRI;
40 MachineDominatorTree *DT;
41 MachineRegisterInfo *MRI;
43 static char ID; // Pass identification
44 MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(5), CurrVN(0) {}
46 virtual bool runOnMachineFunction(MachineFunction &MF);
48 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
50 MachineFunctionPass::getAnalysisUsage(AU);
51 AU.addRequired<AliasAnalysis>();
52 AU.addPreservedID(MachineLoopInfoID);
53 AU.addRequired<MachineDominatorTree>();
54 AU.addPreserved<MachineDominatorTree>();
57 virtual void releaseMemory() {
63 const unsigned LookAheadLimit;
64 typedef ScopedHashTableScope<MachineInstr*, unsigned,
65 MachineInstrExpressionTrait> ScopeType;
66 DenseMap<MachineBasicBlock*, ScopeType*> ScopeMap;
67 ScopedHashTable<MachineInstr*, unsigned, MachineInstrExpressionTrait> VNT;
68 SmallVector<MachineInstr*, 64> Exps;
71 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
72 bool isPhysDefTriviallyDead(unsigned Reg,
73 MachineBasicBlock::const_iterator I,
74 MachineBasicBlock::const_iterator E) const ;
75 bool hasLivePhysRegDefUse(const MachineInstr *MI,
76 const MachineBasicBlock *MBB,
77 unsigned &PhysDef) const;
78 bool PhysRegDefReaches(MachineInstr *CSMI, MachineInstr *MI,
79 unsigned PhysDef) const;
80 bool isCSECandidate(MachineInstr *MI);
81 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
82 MachineInstr *CSMI, MachineInstr *MI);
83 void EnterScope(MachineBasicBlock *MBB);
84 void ExitScope(MachineBasicBlock *MBB);
85 bool ProcessBlock(MachineBasicBlock *MBB);
86 void ExitScopeIfDone(MachineDomTreeNode *Node,
87 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
88 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap);
89 bool PerformCSE(MachineDomTreeNode *Node);
91 } // end anonymous namespace
93 char MachineCSE::ID = 0;
94 INITIALIZE_PASS(MachineCSE, "machine-cse",
95 "Machine Common Subexpression Elimination", false, false);
97 FunctionPass *llvm::createMachineCSEPass() { return new MachineCSE(); }
99 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
100 MachineBasicBlock *MBB) {
101 bool Changed = false;
102 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
103 MachineOperand &MO = MI->getOperand(i);
104 if (!MO.isReg() || !MO.isUse())
106 unsigned Reg = MO.getReg();
107 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
109 if (!MRI->hasOneNonDBGUse(Reg))
110 // Only coalesce single use copies. This ensure the copy will be
113 MachineInstr *DefMI = MRI->getVRegDef(Reg);
114 if (DefMI->getParent() != MBB)
116 if (!DefMI->isCopy())
118 unsigned SrcReg = DefMI->getOperand(1).getReg();
119 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
121 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
123 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
124 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
125 const TargetRegisterClass *NewRC = getCommonSubClass(RC, SRC);
128 DEBUG(dbgs() << "Coalescing: " << *DefMI);
129 DEBUG(dbgs() << "*** to: " << *MI);
131 MRI->clearKillFlags(SrcReg);
133 MRI->setRegClass(SrcReg, NewRC);
134 DefMI->eraseFromParent();
143 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
144 MachineBasicBlock::const_iterator I,
145 MachineBasicBlock::const_iterator E) const {
146 unsigned LookAheadLeft = LookAheadLimit;
147 while (LookAheadLeft) {
148 // Skip over dbg_value's.
149 while (I != E && I->isDebugValue())
153 // Reached end of block, register is obviously dead.
156 bool SeenDef = false;
157 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
158 const MachineOperand &MO = I->getOperand(i);
159 if (!MO.isReg() || !MO.getReg())
161 if (!TRI->regsOverlap(MO.getReg(), Reg))
169 // See a def of Reg (or an alias) before encountering any use, it's
179 /// hasLivePhysRegDefUse - Return true if the specified instruction read / write
180 /// physical registers (except for dead defs of physical registers). It also
181 /// returns the physical register def by reference if it's the only one and the
182 /// instruction does not uses a physical register.
183 bool MachineCSE::hasLivePhysRegDefUse(const MachineInstr *MI,
184 const MachineBasicBlock *MBB,
185 unsigned &PhysDef) const {
187 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
188 const MachineOperand &MO = MI->getOperand(i);
191 unsigned Reg = MO.getReg();
194 if (TargetRegisterInfo::isVirtualRegister(Reg))
197 // Can't touch anything to read a physical register.
202 // If the def is dead, it's ok.
204 // Ok, this is a physical register def that's not marked "dead". That's
205 // common since this pass is run before livevariables. We can scan
206 // forward a few instructions and check if it is obviously dead.
208 // Multiple physical register defs. These are rare, forget about it.
216 MachineBasicBlock::const_iterator I = MI; I = llvm::next(I);
217 if (!isPhysDefTriviallyDead(PhysDef, I, MBB->end()))
223 bool MachineCSE::PhysRegDefReaches(MachineInstr *CSMI, MachineInstr *MI,
224 unsigned PhysDef) const {
225 // For now conservatively returns false if the common subexpression is
226 // not in the same basic block as the given instruction.
227 MachineBasicBlock *MBB = MI->getParent();
228 if (CSMI->getParent() != MBB)
230 MachineBasicBlock::const_iterator I = CSMI; I = llvm::next(I);
231 MachineBasicBlock::const_iterator E = MI;
232 unsigned LookAheadLeft = LookAheadLimit;
233 while (LookAheadLeft) {
234 // Skip over dbg_value's.
235 while (I != E && I->isDebugValue())
240 if (I->modifiesRegister(PhysDef, TRI))
250 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
251 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
252 MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
256 if (MI->isCopyLike())
259 // Ignore stuff that we obviously can't move.
260 const TargetInstrDesc &TID = MI->getDesc();
261 if (TID.mayStore() || TID.isCall() || TID.isTerminator() ||
262 TID.hasUnmodeledSideEffects())
266 // Okay, this instruction does a load. As a refinement, we allow the target
267 // to decide whether the loaded value is actually a constant. If so, we can
268 // actually use it as a load.
269 if (!MI->isInvariantLoad(AA))
270 // FIXME: we should be able to hoist loads with no other side effects if
271 // there are no other instructions which can change memory in this loop.
272 // This is a trivial form of alias analysis.
278 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
279 /// common expression that defines Reg.
280 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
281 MachineInstr *CSMI, MachineInstr *MI) {
282 // FIXME: Heuristics that works around the lack the live range splitting.
284 // Heuristics #1: Don't cse "cheap" computating if the def is not local or in an
285 // immediate predecessor. We don't want to increase register pressure and end up
286 // causing other computation to be spilled.
287 if (MI->getDesc().isAsCheapAsAMove()) {
288 MachineBasicBlock *CSBB = CSMI->getParent();
289 MachineBasicBlock *BB = MI->getParent();
291 find(CSBB->succ_begin(), CSBB->succ_end(), BB) == CSBB->succ_end())
295 // Heuristics #2: If the expression doesn't not use a vr and the only use
296 // of the redundant computation are copies, do not cse.
297 bool HasVRegUse = false;
298 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
299 const MachineOperand &MO = MI->getOperand(i);
300 if (MO.isReg() && MO.isUse() && MO.getReg() &&
301 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
307 bool HasNonCopyUse = false;
308 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
309 E = MRI->use_nodbg_end(); I != E; ++I) {
310 MachineInstr *Use = &*I;
312 if (!Use->isCopyLike()) {
313 HasNonCopyUse = true;
321 // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
322 // it unless the defined value is already used in the BB of the new use.
324 SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
325 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg),
326 E = MRI->use_nodbg_end(); I != E; ++I) {
327 MachineInstr *Use = &*I;
328 HasPHI |= Use->isPHI();
329 CSBBs.insert(Use->getParent());
334 return CSBBs.count(MI->getParent());
337 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
338 DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
339 ScopeType *Scope = new ScopeType(VNT);
340 ScopeMap[MBB] = Scope;
343 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
344 DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
345 DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
346 assert(SI != ScopeMap.end());
351 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
352 bool Changed = false;
354 SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
355 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
356 MachineInstr *MI = &*I;
359 if (!isCSECandidate(MI))
362 bool DefPhys = false;
363 bool FoundCSE = VNT.count(MI);
365 // Look for trivial copy coalescing opportunities.
366 if (PerformTrivialCoalescing(MI, MBB)) {
367 // After coalescing MI itself may become a copy.
368 if (MI->isCopyLike())
370 FoundCSE = VNT.count(MI);
373 // FIXME: commute commutable instructions?
375 // If the instruction defines a physical register and the value *may* be
376 // used, then it's not safe to replace it with a common subexpression.
377 unsigned PhysDef = 0;
378 if (FoundCSE && hasLivePhysRegDefUse(MI, MBB, PhysDef)) {
381 // ... Unless the CS is local and it also defines the physical register
382 // which is not clobbered in between.
384 unsigned CSVN = VNT.lookup(MI);
385 MachineInstr *CSMI = Exps[CSVN];
386 if (PhysRegDefReaches(CSMI, MI, PhysDef)) {
394 VNT.insert(MI, CurrVN++);
399 // Found a common subexpression, eliminate it.
400 unsigned CSVN = VNT.lookup(MI);
401 MachineInstr *CSMI = Exps[CSVN];
402 DEBUG(dbgs() << "Examining: " << *MI);
403 DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
405 // Check if it's profitable to perform this CSE.
407 unsigned NumDefs = MI->getDesc().getNumDefs();
408 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
409 MachineOperand &MO = MI->getOperand(i);
410 if (!MO.isReg() || !MO.isDef())
412 unsigned OldReg = MO.getReg();
413 unsigned NewReg = CSMI->getOperand(i).getReg();
414 if (OldReg == NewReg)
416 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
417 TargetRegisterInfo::isVirtualRegister(NewReg) &&
418 "Do not CSE physical register defs!");
419 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
423 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
427 // Actually perform the elimination.
429 for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
430 MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
431 MRI->clearKillFlags(CSEPairs[i].second);
433 MI->eraseFromParent();
438 DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
439 VNT.insert(MI, CurrVN++);
448 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
449 /// dominator tree node if its a leaf or all of its children are done. Walk
450 /// up the dominator tree to destroy ancestors which are now done.
452 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
453 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
454 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap) {
455 if (OpenChildren[Node])
459 ExitScope(Node->getBlock());
461 // Now traverse upwards to pop ancestors whose offsprings are all done.
462 while (MachineDomTreeNode *Parent = ParentMap[Node]) {
463 unsigned Left = --OpenChildren[Parent];
466 ExitScope(Parent->getBlock());
471 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
472 SmallVector<MachineDomTreeNode*, 32> Scopes;
473 SmallVector<MachineDomTreeNode*, 8> WorkList;
474 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> ParentMap;
475 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
479 // Perform a DFS walk to determine the order of visit.
480 WorkList.push_back(Node);
482 Node = WorkList.pop_back_val();
483 Scopes.push_back(Node);
484 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
485 unsigned NumChildren = Children.size();
486 OpenChildren[Node] = NumChildren;
487 for (unsigned i = 0; i != NumChildren; ++i) {
488 MachineDomTreeNode *Child = Children[i];
489 ParentMap[Child] = Node;
490 WorkList.push_back(Child);
492 } while (!WorkList.empty());
495 bool Changed = false;
496 for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
497 MachineDomTreeNode *Node = Scopes[i];
498 MachineBasicBlock *MBB = Node->getBlock();
500 Changed |= ProcessBlock(MBB);
501 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
502 ExitScopeIfDone(Node, OpenChildren, ParentMap);
508 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
509 TII = MF.getTarget().getInstrInfo();
510 TRI = MF.getTarget().getRegisterInfo();
511 MRI = &MF.getRegInfo();
512 AA = &getAnalysis<AliasAnalysis>();
513 DT = &getAnalysis<MachineDominatorTree>();
514 return PerformCSE(DT->getRootNode());