1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "machine-cse"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/ScopedHashTable.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/RecyclingAllocator.h"
28 #include "llvm/Target/TargetInstrInfo.h"
31 STATISTIC(NumCoalesces, "Number of copies coalesced");
32 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
33 STATISTIC(NumPhysCSEs,
34 "Number of physreg referencing common subexpr eliminated");
35 STATISTIC(NumCrossBBCSEs,
36 "Number of cross-MBB physreg referencing CS eliminated");
37 STATISTIC(NumCommutes, "Number of copies coalesced after commuting");
40 class MachineCSE : public MachineFunctionPass {
41 const TargetInstrInfo *TII;
42 const TargetRegisterInfo *TRI;
44 MachineDominatorTree *DT;
45 MachineRegisterInfo *MRI;
47 static char ID; // Pass identification
48 MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(5), CurrVN(0) {
49 initializeMachineCSEPass(*PassRegistry::getPassRegistry());
52 virtual bool runOnMachineFunction(MachineFunction &MF);
54 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
56 MachineFunctionPass::getAnalysisUsage(AU);
57 AU.addRequired<AliasAnalysis>();
58 AU.addPreservedID(MachineLoopInfoID);
59 AU.addRequired<MachineDominatorTree>();
60 AU.addPreserved<MachineDominatorTree>();
63 virtual void releaseMemory() {
69 const unsigned LookAheadLimit;
70 typedef RecyclingAllocator<BumpPtrAllocator,
71 ScopedHashTableVal<MachineInstr*, unsigned> > AllocatorTy;
72 typedef ScopedHashTable<MachineInstr*, unsigned,
73 MachineInstrExpressionTrait, AllocatorTy> ScopedHTType;
74 typedef ScopedHTType::ScopeTy ScopeType;
75 DenseMap<MachineBasicBlock*, ScopeType*> ScopeMap;
77 SmallVector<MachineInstr*, 64> Exps;
80 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
81 bool isPhysDefTriviallyDead(unsigned Reg,
82 MachineBasicBlock::const_iterator I,
83 MachineBasicBlock::const_iterator E) const;
84 bool hasLivePhysRegDefUses(const MachineInstr *MI,
85 const MachineBasicBlock *MBB,
86 SmallSet<unsigned,8> &PhysRefs,
87 SmallVector<unsigned,2> &PhysDefs,
88 bool &PhysUseDef) const;
89 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
90 SmallSet<unsigned,8> &PhysRefs,
91 SmallVector<unsigned,2> &PhysDefs,
92 bool &NonLocal) const;
93 bool isCSECandidate(MachineInstr *MI);
94 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
95 MachineInstr *CSMI, MachineInstr *MI);
96 void EnterScope(MachineBasicBlock *MBB);
97 void ExitScope(MachineBasicBlock *MBB);
98 bool ProcessBlock(MachineBasicBlock *MBB);
99 void ExitScopeIfDone(MachineDomTreeNode *Node,
100 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren);
101 bool PerformCSE(MachineDomTreeNode *Node);
103 } // end anonymous namespace
105 char MachineCSE::ID = 0;
106 char &llvm::MachineCSEID = MachineCSE::ID;
107 INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
108 "Machine Common Subexpression Elimination", false, false)
109 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
110 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
111 INITIALIZE_PASS_END(MachineCSE, "machine-cse",
112 "Machine Common Subexpression Elimination", false, false)
114 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
115 MachineBasicBlock *MBB) {
116 bool Changed = false;
117 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
118 MachineOperand &MO = MI->getOperand(i);
119 if (!MO.isReg() || !MO.isUse())
121 unsigned Reg = MO.getReg();
122 if (!TargetRegisterInfo::isVirtualRegister(Reg))
124 if (!MRI->hasOneNonDBGUse(Reg))
125 // Only coalesce single use copies. This ensure the copy will be
128 MachineInstr *DefMI = MRI->getVRegDef(Reg);
129 if (!DefMI->isCopy())
131 unsigned SrcReg = DefMI->getOperand(1).getReg();
132 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
134 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
136 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg)))
138 DEBUG(dbgs() << "Coalescing: " << *DefMI);
139 DEBUG(dbgs() << "*** to: " << *MI);
141 MRI->clearKillFlags(SrcReg);
142 DefMI->eraseFromParent();
151 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
152 MachineBasicBlock::const_iterator I,
153 MachineBasicBlock::const_iterator E) const {
154 unsigned LookAheadLeft = LookAheadLimit;
155 while (LookAheadLeft) {
156 // Skip over dbg_value's.
157 while (I != E && I->isDebugValue())
161 // Reached end of block, register is obviously dead.
164 bool SeenDef = false;
165 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
166 const MachineOperand &MO = I->getOperand(i);
167 if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
169 if (!MO.isReg() || !MO.getReg())
171 if (!TRI->regsOverlap(MO.getReg(), Reg))
179 // See a def of Reg (or an alias) before encountering any use, it's
189 /// hasLivePhysRegDefUses - Return true if the specified instruction read/write
190 /// physical registers (except for dead defs of physical registers). It also
191 /// returns the physical register def by reference if it's the only one and the
192 /// instruction does not uses a physical register.
193 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
194 const MachineBasicBlock *MBB,
195 SmallSet<unsigned,8> &PhysRefs,
196 SmallVector<unsigned,2> &PhysDefs,
197 bool &PhysUseDef) const{
198 // First, add all uses to PhysRefs.
199 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
200 const MachineOperand &MO = MI->getOperand(i);
201 if (!MO.isReg() || MO.isDef())
203 unsigned Reg = MO.getReg();
206 if (TargetRegisterInfo::isVirtualRegister(Reg))
208 // Reading constant physregs is ok.
209 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
210 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
211 PhysRefs.insert(*AI);
214 // Next, collect all defs into PhysDefs. If any is already in PhysRefs
215 // (which currently contains only uses), set the PhysUseDef flag.
217 MachineBasicBlock::const_iterator I = MI; I = llvm::next(I);
218 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
219 const MachineOperand &MO = MI->getOperand(i);
220 if (!MO.isReg() || !MO.isDef())
222 unsigned Reg = MO.getReg();
225 if (TargetRegisterInfo::isVirtualRegister(Reg))
227 // Check against PhysRefs even if the def is "dead".
228 if (PhysRefs.count(Reg))
230 // If the def is dead, it's ok. But the def may not marked "dead". That's
231 // common since this pass is run before livevariables. We can scan
232 // forward a few instructions and check if it is obviously dead.
233 if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end()))
234 PhysDefs.push_back(Reg);
237 // Finally, add all defs to PhysRefs as well.
238 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
239 for (MCRegAliasIterator AI(PhysDefs[i], TRI, true); AI.isValid(); ++AI)
240 PhysRefs.insert(*AI);
242 return !PhysRefs.empty();
245 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
246 SmallSet<unsigned,8> &PhysRefs,
247 SmallVector<unsigned,2> &PhysDefs,
248 bool &NonLocal) const {
249 // For now conservatively returns false if the common subexpression is
250 // not in the same basic block as the given instruction. The only exception
251 // is if the common subexpression is in the sole predecessor block.
252 const MachineBasicBlock *MBB = MI->getParent();
253 const MachineBasicBlock *CSMBB = CSMI->getParent();
255 bool CrossMBB = false;
257 if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
260 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
261 if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i]))
262 // Avoid extending live range of physical registers if they are
263 //allocatable or reserved.
268 MachineBasicBlock::const_iterator I = CSMI; I = llvm::next(I);
269 MachineBasicBlock::const_iterator E = MI;
270 MachineBasicBlock::const_iterator EE = CSMBB->end();
271 unsigned LookAheadLeft = LookAheadLimit;
272 while (LookAheadLeft) {
273 // Skip over dbg_value's.
274 while (I != E && I != EE && I->isDebugValue())
278 assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
290 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
291 const MachineOperand &MO = I->getOperand(i);
292 // RegMasks go on instructions like calls that clobber lots of physregs.
293 // Don't attempt to CSE across such an instruction.
296 if (!MO.isReg() || !MO.isDef())
298 unsigned MOReg = MO.getReg();
299 if (TargetRegisterInfo::isVirtualRegister(MOReg))
301 if (PhysRefs.count(MOReg))
312 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
313 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
314 MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
318 if (MI->isCopyLike())
321 // Ignore stuff that we obviously can't move.
322 if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
323 MI->hasUnmodeledSideEffects())
327 // Okay, this instruction does a load. As a refinement, we allow the target
328 // to decide whether the loaded value is actually a constant. If so, we can
329 // actually use it as a load.
330 if (!MI->isInvariantLoad(AA))
331 // FIXME: we should be able to hoist loads with no other side effects if
332 // there are no other instructions which can change memory in this loop.
333 // This is a trivial form of alias analysis.
339 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
340 /// common expression that defines Reg.
341 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
342 MachineInstr *CSMI, MachineInstr *MI) {
343 // FIXME: Heuristics that works around the lack the live range splitting.
345 // If CSReg is used at all uses of Reg, CSE should not increase register
346 // pressure of CSReg.
347 bool MayIncreasePressure = true;
348 if (TargetRegisterInfo::isVirtualRegister(CSReg) &&
349 TargetRegisterInfo::isVirtualRegister(Reg)) {
350 MayIncreasePressure = false;
351 SmallPtrSet<MachineInstr*, 8> CSUses;
352 for (MachineRegisterInfo::use_nodbg_iterator I =MRI->use_nodbg_begin(CSReg),
353 E = MRI->use_nodbg_end(); I != E; ++I) {
354 MachineInstr *Use = &*I;
357 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
358 E = MRI->use_nodbg_end(); I != E; ++I) {
359 MachineInstr *Use = &*I;
360 if (!CSUses.count(Use)) {
361 MayIncreasePressure = true;
366 if (!MayIncreasePressure) return true;
368 // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
369 // an immediate predecessor. We don't want to increase register pressure and
370 // end up causing other computation to be spilled.
371 if (MI->isAsCheapAsAMove()) {
372 MachineBasicBlock *CSBB = CSMI->getParent();
373 MachineBasicBlock *BB = MI->getParent();
374 if (CSBB != BB && !CSBB->isSuccessor(BB))
378 // Heuristics #2: If the expression doesn't not use a vr and the only use
379 // of the redundant computation are copies, do not cse.
380 bool HasVRegUse = false;
381 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
382 const MachineOperand &MO = MI->getOperand(i);
383 if (MO.isReg() && MO.isUse() &&
384 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
390 bool HasNonCopyUse = false;
391 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
392 E = MRI->use_nodbg_end(); I != E; ++I) {
393 MachineInstr *Use = &*I;
395 if (!Use->isCopyLike()) {
396 HasNonCopyUse = true;
404 // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
405 // it unless the defined value is already used in the BB of the new use.
407 SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
408 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg),
409 E = MRI->use_nodbg_end(); I != E; ++I) {
410 MachineInstr *Use = &*I;
411 HasPHI |= Use->isPHI();
412 CSBBs.insert(Use->getParent());
417 return CSBBs.count(MI->getParent());
420 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
421 DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
422 ScopeType *Scope = new ScopeType(VNT);
423 ScopeMap[MBB] = Scope;
426 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
427 DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
428 DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
429 assert(SI != ScopeMap.end());
434 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
435 bool Changed = false;
437 SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
438 SmallVector<unsigned, 2> ImplicitDefsToUpdate;
439 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
440 MachineInstr *MI = &*I;
443 if (!isCSECandidate(MI))
446 bool FoundCSE = VNT.count(MI);
448 // Look for trivial copy coalescing opportunities.
449 if (PerformTrivialCoalescing(MI, MBB)) {
452 // After coalescing MI itself may become a copy.
453 if (MI->isCopyLike())
455 FoundCSE = VNT.count(MI);
459 // Commute commutable instructions.
460 bool Commuted = false;
461 if (!FoundCSE && MI->isCommutable()) {
462 MachineInstr *NewMI = TII->commuteInstruction(MI);
465 FoundCSE = VNT.count(NewMI);
467 // New instruction. It doesn't need to be kept.
468 NewMI->eraseFromParent();
470 } else if (!FoundCSE)
471 // MI was changed but it didn't help, commute it back!
472 (void)TII->commuteInstruction(MI);
476 // If the instruction defines physical registers and the values *may* be
477 // used, then it's not safe to replace it with a common subexpression.
478 // It's also not safe if the instruction uses physical registers.
479 bool CrossMBBPhysDef = false;
480 SmallSet<unsigned, 8> PhysRefs;
481 SmallVector<unsigned, 2> PhysDefs;
482 bool PhysUseDef = false;
483 if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs,
484 PhysDefs, PhysUseDef)) {
487 // ... Unless the CS is local or is in the sole predecessor block
488 // and it also defines the physical register which is not clobbered
489 // in between and the physical register uses were not clobbered.
490 // This can never be the case if the instruction both uses and
491 // defines the same physical register, which was detected above.
493 unsigned CSVN = VNT.lookup(MI);
494 MachineInstr *CSMI = Exps[CSVN];
495 if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
501 VNT.insert(MI, CurrVN++);
506 // Found a common subexpression, eliminate it.
507 unsigned CSVN = VNT.lookup(MI);
508 MachineInstr *CSMI = Exps[CSVN];
509 DEBUG(dbgs() << "Examining: " << *MI);
510 DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
512 // Check if it's profitable to perform this CSE.
514 unsigned NumDefs = MI->getDesc().getNumDefs() +
515 MI->getDesc().getNumImplicitDefs();
517 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
518 MachineOperand &MO = MI->getOperand(i);
519 if (!MO.isReg() || !MO.isDef())
521 unsigned OldReg = MO.getReg();
522 unsigned NewReg = CSMI->getOperand(i).getReg();
524 // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
525 // we should make sure it is not dead at CSMI.
526 if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
527 ImplicitDefsToUpdate.push_back(i);
528 if (OldReg == NewReg) {
533 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
534 TargetRegisterInfo::isVirtualRegister(NewReg) &&
535 "Do not CSE physical register defs!");
537 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
538 DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
543 // Don't perform CSE if the result of the old instruction cannot exist
544 // within the register class of the new instruction.
545 const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
546 if (!MRI->constrainRegClass(NewReg, OldRC)) {
547 DEBUG(dbgs() << "*** Not the same register class, avoid CSE!\n");
552 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
556 // Actually perform the elimination.
558 for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
559 MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
560 MRI->clearKillFlags(CSEPairs[i].second);
563 // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
564 // we should make sure it is not dead at CSMI.
565 for (unsigned i = 0, e = ImplicitDefsToUpdate.size(); i != e; ++i)
566 CSMI->getOperand(ImplicitDefsToUpdate[i]).setIsDead(false);
568 if (CrossMBBPhysDef) {
569 // Add physical register defs now coming in from a predecessor to MBB
571 while (!PhysDefs.empty()) {
572 unsigned LiveIn = PhysDefs.pop_back_val();
573 if (!MBB->isLiveIn(LiveIn))
574 MBB->addLiveIn(LiveIn);
579 MI->eraseFromParent();
581 if (!PhysRefs.empty())
587 VNT.insert(MI, CurrVN++);
591 ImplicitDefsToUpdate.clear();
597 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
598 /// dominator tree node if its a leaf or all of its children are done. Walk
599 /// up the dominator tree to destroy ancestors which are now done.
601 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
602 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren) {
603 if (OpenChildren[Node])
607 ExitScope(Node->getBlock());
609 // Now traverse upwards to pop ancestors whose offsprings are all done.
610 while (MachineDomTreeNode *Parent = Node->getIDom()) {
611 unsigned Left = --OpenChildren[Parent];
614 ExitScope(Parent->getBlock());
619 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
620 SmallVector<MachineDomTreeNode*, 32> Scopes;
621 SmallVector<MachineDomTreeNode*, 8> WorkList;
622 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
626 // Perform a DFS walk to determine the order of visit.
627 WorkList.push_back(Node);
629 Node = WorkList.pop_back_val();
630 Scopes.push_back(Node);
631 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
632 unsigned NumChildren = Children.size();
633 OpenChildren[Node] = NumChildren;
634 for (unsigned i = 0; i != NumChildren; ++i) {
635 MachineDomTreeNode *Child = Children[i];
636 WorkList.push_back(Child);
638 } while (!WorkList.empty());
641 bool Changed = false;
642 for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
643 MachineDomTreeNode *Node = Scopes[i];
644 MachineBasicBlock *MBB = Node->getBlock();
646 Changed |= ProcessBlock(MBB);
647 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
648 ExitScopeIfDone(Node, OpenChildren);
654 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
655 TII = MF.getTarget().getInstrInfo();
656 TRI = MF.getTarget().getRegisterInfo();
657 MRI = &MF.getRegInfo();
658 AA = &getAnalysis<AliasAnalysis>();
659 DT = &getAnalysis<MachineDominatorTree>();
660 return PerformCSE(DT->getRootNode());