1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "machine-cse"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/MachineDominators.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/ScopedHashTable.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Support/Debug.h"
30 STATISTIC(NumCoalesces, "Number of copies coalesced");
31 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
34 class MachineCSE : public MachineFunctionPass {
35 const TargetInstrInfo *TII;
36 const TargetRegisterInfo *TRI;
38 MachineDominatorTree *DT;
39 MachineRegisterInfo *MRI;
41 static char ID; // Pass identification
42 MachineCSE() : MachineFunctionPass(&ID), CurrVN(0) {}
44 virtual bool runOnMachineFunction(MachineFunction &MF);
46 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
48 MachineFunctionPass::getAnalysisUsage(AU);
49 AU.addRequired<AliasAnalysis>();
50 AU.addRequired<MachineDominatorTree>();
51 AU.addPreserved<MachineDominatorTree>();
55 typedef ScopedHashTableScope<MachineInstr*, unsigned,
56 MachineInstrExpressionTrait> ScopeType;
57 DenseMap<MachineBasicBlock*, ScopeType*> ScopeMap;
58 ScopedHashTable<MachineInstr*, unsigned, MachineInstrExpressionTrait> VNT;
59 SmallVector<MachineInstr*, 64> Exps;
62 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
63 bool isPhysDefTriviallyDead(unsigned Reg,
64 MachineBasicBlock::const_iterator I,
65 MachineBasicBlock::const_iterator E);
66 bool hasLivePhysRegDefUse(MachineInstr *MI, MachineBasicBlock *MBB);
67 bool isCSECandidate(MachineInstr *MI);
68 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
69 MachineInstr *CSMI, MachineInstr *MI);
70 void EnterScope(MachineBasicBlock *MBB);
71 void ExitScope(MachineBasicBlock *MBB);
72 bool ProcessBlock(MachineBasicBlock *MBB);
73 void ExitScopeIfDone(MachineDomTreeNode *Node,
74 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
75 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap);
76 bool PerformCSE(MachineDomTreeNode *Node);
78 } // end anonymous namespace
80 char MachineCSE::ID = 0;
81 static RegisterPass<MachineCSE>
82 X("machine-cse", "Machine Common Subexpression Elimination");
84 FunctionPass *llvm::createMachineCSEPass() { return new MachineCSE(); }
86 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
87 MachineBasicBlock *MBB) {
89 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
90 MachineOperand &MO = MI->getOperand(i);
91 if (!MO.isReg() || !MO.isUse())
93 unsigned Reg = MO.getReg();
94 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
96 if (!MRI->hasOneUse(Reg))
97 // Only coalesce single use copies. This ensure the copy will be
100 MachineInstr *DefMI = MRI->getVRegDef(Reg);
101 if (DefMI->getParent() != MBB)
103 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
104 if (TII->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
105 TargetRegisterInfo::isVirtualRegister(SrcReg) &&
106 !SrcSubIdx && !DstSubIdx) {
107 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
108 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
109 const TargetRegisterClass *NewRC = getCommonSubClass(RC, SRC);
112 DEBUG(dbgs() << "Coalescing: " << *DefMI);
113 DEBUG(dbgs() << "*** to: " << *MI);
116 MRI->setRegClass(SrcReg, NewRC);
117 DefMI->eraseFromParent();
126 bool MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
127 MachineBasicBlock::const_iterator I,
128 MachineBasicBlock::const_iterator E) {
129 unsigned LookAheadLeft = 5;
130 while (LookAheadLeft) {
131 // Skip over dbg_value's.
132 while (I != E && I->isDebugValue())
136 // Reached end of block, register is obviously dead.
139 bool SeenDef = false;
140 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
141 const MachineOperand &MO = I->getOperand(i);
142 if (!MO.isReg() || !MO.getReg())
144 if (!TRI->regsOverlap(MO.getReg(), Reg))
151 // See a def of Reg (or an alias) before encountering any use, it's
161 /// hasLivePhysRegDefUse - Return true if the specified instruction read / write
162 /// physical registers (except for dead defs of physical registers).
163 bool MachineCSE::hasLivePhysRegDefUse(MachineInstr *MI, MachineBasicBlock *MBB){
164 unsigned PhysDef = 0;
165 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
166 MachineOperand &MO = MI->getOperand(i);
169 unsigned Reg = MO.getReg();
172 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
174 // Can't touch anything to read a physical register.
177 // If the def is dead, it's ok.
179 // Ok, this is a physical register def that's not marked "dead". That's
180 // common since this pass is run before livevariables. We can scan
181 // forward a few instructions and check if it is obviously dead.
183 // Multiple physical register defs. These are rare, forget about it.
190 MachineBasicBlock::iterator I = MI; I = llvm::next(I);
191 if (!isPhysDefTriviallyDead(PhysDef, I, MBB->end()))
197 static bool isCopy(const MachineInstr *MI, const TargetInstrInfo *TII) {
198 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
199 return TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) ||
200 MI->isExtractSubreg() || MI->isInsertSubreg() || MI->isSubregToReg();
203 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
204 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
205 MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
212 // Ignore stuff that we obviously can't move.
213 const TargetInstrDesc &TID = MI->getDesc();
214 if (TID.mayStore() || TID.isCall() || TID.isTerminator() ||
215 TID.hasUnmodeledSideEffects())
219 // Okay, this instruction does a load. As a refinement, we allow the target
220 // to decide whether the loaded value is actually a constant. If so, we can
221 // actually use it as a load.
222 if (!MI->isInvariantLoad(AA))
223 // FIXME: we should be able to hoist loads with no other side effects if
224 // there are no other instructions which can change memory in this loop.
225 // This is a trivial form of alias analysis.
231 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
232 /// common expression that defines Reg.
233 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
234 MachineInstr *CSMI, MachineInstr *MI) {
235 // FIXME: Heuristics that works around the lack the live range splitting.
237 // Heuristics #1: Don't cse "cheap" computating if the def is not local or in an
238 // immediate predecessor. We don't want to increase register pressure and end up
239 // causing other computation to be spilled.
240 if (MI->getDesc().isAsCheapAsAMove()) {
241 MachineBasicBlock *CSBB = CSMI->getParent();
242 MachineBasicBlock *BB = MI->getParent();
244 find(CSBB->succ_begin(), CSBB->succ_end(), BB) == CSBB->succ_end())
248 // Heuristics #2: If the expression doesn't not use a vr and the only use
249 // of the redundant computation are copies, do not cse.
250 bool HasVRegUse = false;
251 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
252 const MachineOperand &MO = MI->getOperand(i);
253 if (MO.isReg() && MO.isUse() && MO.getReg() &&
254 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
260 bool HasNonCopyUse = false;
261 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
262 E = MRI->use_nodbg_end(); I != E; ++I) {
263 MachineInstr *Use = &*I;
265 if (!isCopy(Use, TII)) {
266 HasNonCopyUse = true;
274 // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
275 // it unless the defined value is already used in the BB of the new use.
277 SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
278 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg),
279 E = MRI->use_nodbg_end(); I != E; ++I) {
280 MachineInstr *Use = &*I;
281 HasPHI |= Use->isPHI();
282 CSBBs.insert(Use->getParent());
287 return CSBBs.count(MI->getParent());
290 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
291 DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
292 ScopeType *Scope = new ScopeType(VNT);
293 ScopeMap[MBB] = Scope;
296 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
297 DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
298 DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
299 assert(SI != ScopeMap.end());
304 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
305 bool Changed = false;
307 SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
308 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
309 MachineInstr *MI = &*I;
312 if (!isCSECandidate(MI))
315 bool FoundCSE = VNT.count(MI);
317 // Look for trivial copy coalescing opportunities.
318 if (PerformTrivialCoalescing(MI, MBB)) {
319 // After coalescing MI itself may become a copy.
322 FoundCSE = VNT.count(MI);
325 // FIXME: commute commutable instructions?
327 // If the instruction defines a physical register and the value *may* be
328 // used, then it's not safe to replace it with a common subexpression.
329 if (FoundCSE && hasLivePhysRegDefUse(MI, MBB))
333 VNT.insert(MI, CurrVN++);
338 // Found a common subexpression, eliminate it.
339 unsigned CSVN = VNT.lookup(MI);
340 MachineInstr *CSMI = Exps[CSVN];
341 DEBUG(dbgs() << "Examining: " << *MI);
342 DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
344 // Check if it's profitable to perform this CSE.
346 unsigned NumDefs = MI->getDesc().getNumDefs();
347 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
348 MachineOperand &MO = MI->getOperand(i);
349 if (!MO.isReg() || !MO.isDef())
351 unsigned OldReg = MO.getReg();
352 unsigned NewReg = CSMI->getOperand(i).getReg();
353 if (OldReg == NewReg)
355 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
356 TargetRegisterInfo::isVirtualRegister(NewReg) &&
357 "Do not CSE physical register defs!");
358 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
362 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
366 // Actually perform the elimination.
368 for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i)
369 MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
370 MI->eraseFromParent();
373 DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
374 VNT.insert(MI, CurrVN++);
383 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
384 /// dominator tree node if its a leaf or all of its children are done. Walk
385 /// up the dominator tree to destroy ancestors which are now done.
387 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
388 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
389 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap) {
390 if (OpenChildren[Node])
394 ExitScope(Node->getBlock());
396 // Now traverse upwards to pop ancestors whose offsprings are all done.
397 while (MachineDomTreeNode *Parent = ParentMap[Node]) {
398 unsigned Left = --OpenChildren[Parent];
401 ExitScope(Parent->getBlock());
406 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
407 SmallVector<MachineDomTreeNode*, 32> Scopes;
408 SmallVector<MachineDomTreeNode*, 8> WorkList;
409 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> ParentMap;
410 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
412 // Perform a DFS walk to determine the order of visit.
413 WorkList.push_back(Node);
415 Node = WorkList.pop_back_val();
416 Scopes.push_back(Node);
417 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
418 unsigned NumChildren = Children.size();
419 OpenChildren[Node] = NumChildren;
420 for (unsigned i = 0; i != NumChildren; ++i) {
421 MachineDomTreeNode *Child = Children[i];
422 ParentMap[Child] = Node;
423 WorkList.push_back(Child);
425 } while (!WorkList.empty());
428 bool Changed = false;
429 for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
430 MachineDomTreeNode *Node = Scopes[i];
431 MachineBasicBlock *MBB = Node->getBlock();
433 Changed |= ProcessBlock(MBB);
434 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
435 ExitScopeIfDone(Node, OpenChildren, ParentMap);
441 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
442 TII = MF.getTarget().getInstrInfo();
443 TRI = MF.getTarget().getRegisterInfo();
444 MRI = &MF.getRegInfo();
445 AA = &getAnalysis<AliasAnalysis>();
446 DT = &getAnalysis<MachineDominatorTree>();
447 return PerformCSE(DT->getRootNode());