1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "machine-cse"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/MachineDominators.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/ScopedHashTable.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
31 STATISTIC(NumCoalesces, "Number of copies coalesced");
32 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
33 STATISTIC(NumPhysCSEs, "Number of phyreg defining common subexpr eliminated");
36 class MachineCSE : public MachineFunctionPass {
37 const TargetInstrInfo *TII;
38 const TargetRegisterInfo *TRI;
40 MachineDominatorTree *DT;
41 MachineRegisterInfo *MRI;
43 static char ID; // Pass identification
44 MachineCSE() : MachineFunctionPass(&ID), LookAheadLimit(5), CurrVN(0) {}
46 virtual bool runOnMachineFunction(MachineFunction &MF);
48 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
50 MachineFunctionPass::getAnalysisUsage(AU);
51 AU.addRequired<AliasAnalysis>();
52 AU.addRequired<MachineDominatorTree>();
53 AU.addPreserved<MachineDominatorTree>();
57 const unsigned LookAheadLimit;
58 typedef ScopedHashTableScope<MachineInstr*, unsigned,
59 MachineInstrExpressionTrait> ScopeType;
60 DenseMap<MachineBasicBlock*, ScopeType*> ScopeMap;
61 ScopedHashTable<MachineInstr*, unsigned, MachineInstrExpressionTrait> VNT;
62 SmallVector<MachineInstr*, 64> Exps;
65 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
66 bool isPhysDefTriviallyDead(unsigned Reg,
67 MachineBasicBlock::const_iterator I,
68 MachineBasicBlock::const_iterator E) const ;
69 bool hasLivePhysRegDefUse(const MachineInstr *MI,
70 const MachineBasicBlock *MBB,
71 unsigned &PhysDef) const;
72 bool PhysRegDefReaches(MachineInstr *CSMI, MachineInstr *MI,
73 unsigned PhysDef) const;
74 bool isCSECandidate(MachineInstr *MI);
75 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
76 MachineInstr *CSMI, MachineInstr *MI);
77 void EnterScope(MachineBasicBlock *MBB);
78 void ExitScope(MachineBasicBlock *MBB);
79 bool ProcessBlock(MachineBasicBlock *MBB);
80 void ExitScopeIfDone(MachineDomTreeNode *Node,
81 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
82 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap);
83 bool PerformCSE(MachineDomTreeNode *Node);
85 } // end anonymous namespace
87 char MachineCSE::ID = 0;
88 static RegisterPass<MachineCSE>
89 X("machine-cse", "Machine Common Subexpression Elimination");
91 FunctionPass *llvm::createMachineCSEPass() { return new MachineCSE(); }
93 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
94 MachineBasicBlock *MBB) {
96 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
97 MachineOperand &MO = MI->getOperand(i);
98 if (!MO.isReg() || !MO.isUse())
100 unsigned Reg = MO.getReg();
101 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
103 if (!MRI->hasOneUse(Reg))
104 // Only coalesce single use copies. This ensure the copy will be
107 MachineInstr *DefMI = MRI->getVRegDef(Reg);
108 if (DefMI->getParent() != MBB)
110 if (!DefMI->isCopy())
112 unsigned SrcReg = DefMI->getOperand(1).getReg();
113 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
115 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
117 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
118 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
119 const TargetRegisterClass *NewRC = getCommonSubClass(RC, SRC);
122 DEBUG(dbgs() << "Coalescing: " << *DefMI);
123 DEBUG(dbgs() << "*** to: " << *MI);
125 MRI->clearKillFlags(SrcReg);
127 MRI->setRegClass(SrcReg, NewRC);
128 DefMI->eraseFromParent();
137 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
138 MachineBasicBlock::const_iterator I,
139 MachineBasicBlock::const_iterator E) const {
140 unsigned LookAheadLeft = LookAheadLimit;
141 while (LookAheadLeft) {
142 // Skip over dbg_value's.
143 while (I != E && I->isDebugValue())
147 // Reached end of block, register is obviously dead.
150 bool SeenDef = false;
151 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
152 const MachineOperand &MO = I->getOperand(i);
153 if (!MO.isReg() || !MO.getReg())
155 if (!TRI->regsOverlap(MO.getReg(), Reg))
163 // See a def of Reg (or an alias) before encountering any use, it's
173 /// hasLivePhysRegDefUse - Return true if the specified instruction read / write
174 /// physical registers (except for dead defs of physical registers). It also
175 /// returns the physical register def by reference if it's the only one and the
176 /// instruction does not uses a physical register.
177 bool MachineCSE::hasLivePhysRegDefUse(const MachineInstr *MI,
178 const MachineBasicBlock *MBB,
179 unsigned &PhysDef) const {
181 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
182 const MachineOperand &MO = MI->getOperand(i);
185 unsigned Reg = MO.getReg();
188 if (TargetRegisterInfo::isVirtualRegister(Reg))
191 // Can't touch anything to read a physical register.
196 // If the def is dead, it's ok.
198 // Ok, this is a physical register def that's not marked "dead". That's
199 // common since this pass is run before livevariables. We can scan
200 // forward a few instructions and check if it is obviously dead.
202 // Multiple physical register defs. These are rare, forget about it.
210 MachineBasicBlock::const_iterator I = MI; I = llvm::next(I);
211 if (!isPhysDefTriviallyDead(PhysDef, I, MBB->end()))
217 bool MachineCSE::PhysRegDefReaches(MachineInstr *CSMI, MachineInstr *MI,
218 unsigned PhysDef) const {
219 // For now conservatively returns false if the common subexpression is
220 // not in the same basic block as the given instruction.
221 MachineBasicBlock *MBB = MI->getParent();
222 if (CSMI->getParent() != MBB)
224 MachineBasicBlock::const_iterator I = CSMI; I = llvm::next(I);
225 MachineBasicBlock::const_iterator E = MI;
226 unsigned LookAheadLeft = LookAheadLimit;
227 while (LookAheadLeft) {
228 // Skip over dbg_value's.
229 while (I != E && I->isDebugValue())
234 if (I->modifiesRegister(PhysDef, TRI))
244 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
245 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
246 MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
250 if (MI->isCopyLike())
253 // Ignore stuff that we obviously can't move.
254 const TargetInstrDesc &TID = MI->getDesc();
255 if (TID.mayStore() || TID.isCall() || TID.isTerminator() ||
256 TID.hasUnmodeledSideEffects())
260 // Okay, this instruction does a load. As a refinement, we allow the target
261 // to decide whether the loaded value is actually a constant. If so, we can
262 // actually use it as a load.
263 if (!MI->isInvariantLoad(AA))
264 // FIXME: we should be able to hoist loads with no other side effects if
265 // there are no other instructions which can change memory in this loop.
266 // This is a trivial form of alias analysis.
272 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
273 /// common expression that defines Reg.
274 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
275 MachineInstr *CSMI, MachineInstr *MI) {
276 // FIXME: Heuristics that works around the lack the live range splitting.
278 // Heuristics #1: Don't cse "cheap" computating if the def is not local or in an
279 // immediate predecessor. We don't want to increase register pressure and end up
280 // causing other computation to be spilled.
281 if (MI->getDesc().isAsCheapAsAMove()) {
282 MachineBasicBlock *CSBB = CSMI->getParent();
283 MachineBasicBlock *BB = MI->getParent();
285 find(CSBB->succ_begin(), CSBB->succ_end(), BB) == CSBB->succ_end())
289 // Heuristics #2: If the expression doesn't not use a vr and the only use
290 // of the redundant computation are copies, do not cse.
291 bool HasVRegUse = false;
292 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
293 const MachineOperand &MO = MI->getOperand(i);
294 if (MO.isReg() && MO.isUse() && MO.getReg() &&
295 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
301 bool HasNonCopyUse = false;
302 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
303 E = MRI->use_nodbg_end(); I != E; ++I) {
304 MachineInstr *Use = &*I;
306 if (!Use->isCopyLike()) {
307 HasNonCopyUse = true;
315 // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
316 // it unless the defined value is already used in the BB of the new use.
318 SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
319 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg),
320 E = MRI->use_nodbg_end(); I != E; ++I) {
321 MachineInstr *Use = &*I;
322 HasPHI |= Use->isPHI();
323 CSBBs.insert(Use->getParent());
328 return CSBBs.count(MI->getParent());
331 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
332 DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
333 ScopeType *Scope = new ScopeType(VNT);
334 ScopeMap[MBB] = Scope;
337 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
338 DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
339 DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
340 assert(SI != ScopeMap.end());
345 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
346 bool Changed = false;
348 SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
349 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
350 MachineInstr *MI = &*I;
353 if (!isCSECandidate(MI))
356 bool DefPhys = false;
357 bool FoundCSE = VNT.count(MI);
359 // Look for trivial copy coalescing opportunities.
360 if (PerformTrivialCoalescing(MI, MBB)) {
361 // After coalescing MI itself may become a copy.
362 if (MI->isCopyLike())
364 FoundCSE = VNT.count(MI);
367 // FIXME: commute commutable instructions?
369 // If the instruction defines a physical register and the value *may* be
370 // used, then it's not safe to replace it with a common subexpression.
371 unsigned PhysDef = 0;
372 if (FoundCSE && hasLivePhysRegDefUse(MI, MBB, PhysDef)) {
375 // ... Unless the CS is local and it also defines the physical register
376 // which is not clobbered in between.
378 unsigned CSVN = VNT.lookup(MI);
379 MachineInstr *CSMI = Exps[CSVN];
380 if (PhysRegDefReaches(CSMI, MI, PhysDef)) {
388 VNT.insert(MI, CurrVN++);
393 // Found a common subexpression, eliminate it.
394 unsigned CSVN = VNT.lookup(MI);
395 MachineInstr *CSMI = Exps[CSVN];
396 DEBUG(dbgs() << "Examining: " << *MI);
397 DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
399 // Check if it's profitable to perform this CSE.
401 unsigned NumDefs = MI->getDesc().getNumDefs();
402 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
403 MachineOperand &MO = MI->getOperand(i);
404 if (!MO.isReg() || !MO.isDef())
406 unsigned OldReg = MO.getReg();
407 unsigned NewReg = CSMI->getOperand(i).getReg();
408 if (OldReg == NewReg)
410 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
411 TargetRegisterInfo::isVirtualRegister(NewReg) &&
412 "Do not CSE physical register defs!");
413 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
417 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
421 // Actually perform the elimination.
423 for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
424 MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
425 MRI->clearKillFlags(CSEPairs[i].second);
427 MI->eraseFromParent();
432 DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
433 VNT.insert(MI, CurrVN++);
442 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
443 /// dominator tree node if its a leaf or all of its children are done. Walk
444 /// up the dominator tree to destroy ancestors which are now done.
446 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
447 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
448 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap) {
449 if (OpenChildren[Node])
453 ExitScope(Node->getBlock());
455 // Now traverse upwards to pop ancestors whose offsprings are all done.
456 while (MachineDomTreeNode *Parent = ParentMap[Node]) {
457 unsigned Left = --OpenChildren[Parent];
460 ExitScope(Parent->getBlock());
465 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
466 SmallVector<MachineDomTreeNode*, 32> Scopes;
467 SmallVector<MachineDomTreeNode*, 8> WorkList;
468 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> ParentMap;
469 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
471 // Perform a DFS walk to determine the order of visit.
472 WorkList.push_back(Node);
474 Node = WorkList.pop_back_val();
475 Scopes.push_back(Node);
476 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
477 unsigned NumChildren = Children.size();
478 OpenChildren[Node] = NumChildren;
479 for (unsigned i = 0; i != NumChildren; ++i) {
480 MachineDomTreeNode *Child = Children[i];
481 ParentMap[Child] = Node;
482 WorkList.push_back(Child);
484 } while (!WorkList.empty());
487 bool Changed = false;
488 for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
489 MachineDomTreeNode *Node = Scopes[i];
490 MachineBasicBlock *MBB = Node->getBlock();
492 Changed |= ProcessBlock(MBB);
493 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
494 ExitScopeIfDone(Node, OpenChildren, ParentMap);
500 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
501 TII = MF.getTarget().getInstrInfo();
502 TRI = MF.getTarget().getRegisterInfo();
503 MRI = &MF.getRegInfo();
504 AA = &getAnalysis<AliasAnalysis>();
505 DT = &getAnalysis<MachineDominatorTree>();
506 return PerformCSE(DT->getRootNode());