1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "machine-cse"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/ScopedHashTable.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/RecyclingAllocator.h"
28 #include "llvm/Target/TargetInstrInfo.h"
31 STATISTIC(NumCoalesces, "Number of copies coalesced");
32 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
33 STATISTIC(NumPhysCSEs,
34 "Number of physreg referencing common subexpr eliminated");
35 STATISTIC(NumCrossBBCSEs,
36 "Number of cross-MBB physreg referencing CS eliminated");
37 STATISTIC(NumCommutes, "Number of copies coalesced after commuting");
40 class MachineCSE : public MachineFunctionPass {
41 const TargetInstrInfo *TII;
42 const TargetRegisterInfo *TRI;
44 MachineDominatorTree *DT;
45 MachineRegisterInfo *MRI;
47 static char ID; // Pass identification
48 MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(5), CurrVN(0) {
49 initializeMachineCSEPass(*PassRegistry::getPassRegistry());
52 bool runOnMachineFunction(MachineFunction &MF) override;
54 void getAnalysisUsage(AnalysisUsage &AU) const override {
56 MachineFunctionPass::getAnalysisUsage(AU);
57 AU.addRequired<AliasAnalysis>();
58 AU.addPreservedID(MachineLoopInfoID);
59 AU.addRequired<MachineDominatorTree>();
60 AU.addPreserved<MachineDominatorTree>();
63 void releaseMemory() override {
69 const unsigned LookAheadLimit;
70 typedef RecyclingAllocator<BumpPtrAllocator,
71 ScopedHashTableVal<MachineInstr*, unsigned> > AllocatorTy;
72 typedef ScopedHashTable<MachineInstr*, unsigned,
73 MachineInstrExpressionTrait, AllocatorTy> ScopedHTType;
74 typedef ScopedHTType::ScopeTy ScopeType;
75 DenseMap<MachineBasicBlock*, ScopeType*> ScopeMap;
77 SmallVector<MachineInstr*, 64> Exps;
80 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
81 bool isPhysDefTriviallyDead(unsigned Reg,
82 MachineBasicBlock::const_iterator I,
83 MachineBasicBlock::const_iterator E) const;
84 bool hasLivePhysRegDefUses(const MachineInstr *MI,
85 const MachineBasicBlock *MBB,
86 SmallSet<unsigned,8> &PhysRefs,
87 SmallVectorImpl<unsigned> &PhysDefs,
88 bool &PhysUseDef) const;
89 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
90 SmallSet<unsigned,8> &PhysRefs,
91 SmallVectorImpl<unsigned> &PhysDefs,
92 bool &NonLocal) const;
93 bool isCSECandidate(MachineInstr *MI);
94 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
95 MachineInstr *CSMI, MachineInstr *MI);
96 void EnterScope(MachineBasicBlock *MBB);
97 void ExitScope(MachineBasicBlock *MBB);
98 bool ProcessBlock(MachineBasicBlock *MBB);
99 void ExitScopeIfDone(MachineDomTreeNode *Node,
100 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren);
101 bool PerformCSE(MachineDomTreeNode *Node);
103 } // end anonymous namespace
105 char MachineCSE::ID = 0;
106 char &llvm::MachineCSEID = MachineCSE::ID;
107 INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
108 "Machine Common Subexpression Elimination", false, false)
109 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
110 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
111 INITIALIZE_PASS_END(MachineCSE, "machine-cse",
112 "Machine Common Subexpression Elimination", false, false)
114 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
115 MachineBasicBlock *MBB) {
116 bool Changed = false;
117 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
118 MachineOperand &MO = MI->getOperand(i);
119 if (!MO.isReg() || !MO.isUse())
121 unsigned Reg = MO.getReg();
122 if (!TargetRegisterInfo::isVirtualRegister(Reg))
124 if (!MRI->hasOneNonDBGUse(Reg))
125 // Only coalesce single use copies. This ensure the copy will be
128 MachineInstr *DefMI = MRI->getVRegDef(Reg);
129 if (!DefMI->isCopy())
131 unsigned SrcReg = DefMI->getOperand(1).getReg();
132 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
134 if (DefMI->getOperand(0).getSubReg())
136 // FIXME: We should trivially coalesce subregister copies to expose CSE
137 // opportunities on instructions with truncated operands (see
138 // cse-add-with-overflow.ll). This can be done here as follows:
140 // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
142 // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
144 // The 2-addr pass has been updated to handle coalesced subregs. However,
145 // some machine-specific code still can't handle it.
146 // To handle it properly we also need a way find a constrained subregister
147 // class given a super-reg class and subreg index.
148 if (DefMI->getOperand(1).getSubReg())
150 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
151 if (!MRI->constrainRegClass(SrcReg, RC))
153 DEBUG(dbgs() << "Coalescing: " << *DefMI);
154 DEBUG(dbgs() << "*** to: " << *MI);
156 MRI->clearKillFlags(SrcReg);
157 DefMI->eraseFromParent();
166 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
167 MachineBasicBlock::const_iterator I,
168 MachineBasicBlock::const_iterator E) const {
169 unsigned LookAheadLeft = LookAheadLimit;
170 while (LookAheadLeft) {
171 // Skip over dbg_value's.
172 while (I != E && I->isDebugValue())
176 // Reached end of block, register is obviously dead.
179 bool SeenDef = false;
180 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
181 const MachineOperand &MO = I->getOperand(i);
182 if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
184 if (!MO.isReg() || !MO.getReg())
186 if (!TRI->regsOverlap(MO.getReg(), Reg))
194 // See a def of Reg (or an alias) before encountering any use, it's
204 /// hasLivePhysRegDefUses - Return true if the specified instruction read/write
205 /// physical registers (except for dead defs of physical registers). It also
206 /// returns the physical register def by reference if it's the only one and the
207 /// instruction does not uses a physical register.
208 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
209 const MachineBasicBlock *MBB,
210 SmallSet<unsigned,8> &PhysRefs,
211 SmallVectorImpl<unsigned> &PhysDefs,
212 bool &PhysUseDef) const{
213 // First, add all uses to PhysRefs.
214 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
215 const MachineOperand &MO = MI->getOperand(i);
216 if (!MO.isReg() || MO.isDef())
218 unsigned Reg = MO.getReg();
221 if (TargetRegisterInfo::isVirtualRegister(Reg))
223 // Reading constant physregs is ok.
224 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
225 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
226 PhysRefs.insert(*AI);
229 // Next, collect all defs into PhysDefs. If any is already in PhysRefs
230 // (which currently contains only uses), set the PhysUseDef flag.
232 MachineBasicBlock::const_iterator I = MI; I = std::next(I);
233 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
234 const MachineOperand &MO = MI->getOperand(i);
235 if (!MO.isReg() || !MO.isDef())
237 unsigned Reg = MO.getReg();
240 if (TargetRegisterInfo::isVirtualRegister(Reg))
242 // Check against PhysRefs even if the def is "dead".
243 if (PhysRefs.count(Reg))
245 // If the def is dead, it's ok. But the def may not marked "dead". That's
246 // common since this pass is run before livevariables. We can scan
247 // forward a few instructions and check if it is obviously dead.
248 if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end()))
249 PhysDefs.push_back(Reg);
252 // Finally, add all defs to PhysRefs as well.
253 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
254 for (MCRegAliasIterator AI(PhysDefs[i], TRI, true); AI.isValid(); ++AI)
255 PhysRefs.insert(*AI);
257 return !PhysRefs.empty();
260 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
261 SmallSet<unsigned,8> &PhysRefs,
262 SmallVectorImpl<unsigned> &PhysDefs,
263 bool &NonLocal) const {
264 // For now conservatively returns false if the common subexpression is
265 // not in the same basic block as the given instruction. The only exception
266 // is if the common subexpression is in the sole predecessor block.
267 const MachineBasicBlock *MBB = MI->getParent();
268 const MachineBasicBlock *CSMBB = CSMI->getParent();
270 bool CrossMBB = false;
272 if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
275 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
276 if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i]))
277 // Avoid extending live range of physical registers if they are
278 //allocatable or reserved.
283 MachineBasicBlock::const_iterator I = CSMI; I = std::next(I);
284 MachineBasicBlock::const_iterator E = MI;
285 MachineBasicBlock::const_iterator EE = CSMBB->end();
286 unsigned LookAheadLeft = LookAheadLimit;
287 while (LookAheadLeft) {
288 // Skip over dbg_value's.
289 while (I != E && I != EE && I->isDebugValue())
293 assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
305 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
306 const MachineOperand &MO = I->getOperand(i);
307 // RegMasks go on instructions like calls that clobber lots of physregs.
308 // Don't attempt to CSE across such an instruction.
311 if (!MO.isReg() || !MO.isDef())
313 unsigned MOReg = MO.getReg();
314 if (TargetRegisterInfo::isVirtualRegister(MOReg))
316 if (PhysRefs.count(MOReg))
327 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
328 if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() || MI->isKill() ||
329 MI->isInlineAsm() || MI->isDebugValue())
333 if (MI->isCopyLike())
336 // Ignore stuff that we obviously can't move.
337 if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
338 MI->hasUnmodeledSideEffects())
342 // Okay, this instruction does a load. As a refinement, we allow the target
343 // to decide whether the loaded value is actually a constant. If so, we can
344 // actually use it as a load.
345 if (!MI->isInvariantLoad(AA))
346 // FIXME: we should be able to hoist loads with no other side effects if
347 // there are no other instructions which can change memory in this loop.
348 // This is a trivial form of alias analysis.
354 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
355 /// common expression that defines Reg.
356 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
357 MachineInstr *CSMI, MachineInstr *MI) {
358 // FIXME: Heuristics that works around the lack the live range splitting.
360 // If CSReg is used at all uses of Reg, CSE should not increase register
361 // pressure of CSReg.
362 bool MayIncreasePressure = true;
363 if (TargetRegisterInfo::isVirtualRegister(CSReg) &&
364 TargetRegisterInfo::isVirtualRegister(Reg)) {
365 MayIncreasePressure = false;
366 SmallPtrSet<MachineInstr*, 8> CSUses;
367 for (MachineRegisterInfo::use_nodbg_iterator I =MRI->use_nodbg_begin(CSReg),
368 E = MRI->use_nodbg_end(); I != E; ++I) {
369 MachineInstr *Use = &*I;
372 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
373 E = MRI->use_nodbg_end(); I != E; ++I) {
374 MachineInstr *Use = &*I;
375 if (!CSUses.count(Use)) {
376 MayIncreasePressure = true;
381 if (!MayIncreasePressure) return true;
383 // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
384 // an immediate predecessor. We don't want to increase register pressure and
385 // end up causing other computation to be spilled.
386 if (MI->isAsCheapAsAMove()) {
387 MachineBasicBlock *CSBB = CSMI->getParent();
388 MachineBasicBlock *BB = MI->getParent();
389 if (CSBB != BB && !CSBB->isSuccessor(BB))
393 // Heuristics #2: If the expression doesn't not use a vr and the only use
394 // of the redundant computation are copies, do not cse.
395 bool HasVRegUse = false;
396 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
397 const MachineOperand &MO = MI->getOperand(i);
398 if (MO.isReg() && MO.isUse() &&
399 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
405 bool HasNonCopyUse = false;
406 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
407 E = MRI->use_nodbg_end(); I != E; ++I) {
408 MachineInstr *Use = &*I;
410 if (!Use->isCopyLike()) {
411 HasNonCopyUse = true;
419 // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
420 // it unless the defined value is already used in the BB of the new use.
422 SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
423 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg),
424 E = MRI->use_nodbg_end(); I != E; ++I) {
425 MachineInstr *Use = &*I;
426 HasPHI |= Use->isPHI();
427 CSBBs.insert(Use->getParent());
432 return CSBBs.count(MI->getParent());
435 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
436 DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
437 ScopeType *Scope = new ScopeType(VNT);
438 ScopeMap[MBB] = Scope;
441 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
442 DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
443 DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
444 assert(SI != ScopeMap.end());
449 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
450 bool Changed = false;
452 SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
453 SmallVector<unsigned, 2> ImplicitDefsToUpdate;
454 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
455 MachineInstr *MI = &*I;
458 if (!isCSECandidate(MI))
461 bool FoundCSE = VNT.count(MI);
463 // Look for trivial copy coalescing opportunities.
464 if (PerformTrivialCoalescing(MI, MBB)) {
467 // After coalescing MI itself may become a copy.
468 if (MI->isCopyLike())
470 FoundCSE = VNT.count(MI);
474 // Commute commutable instructions.
475 bool Commuted = false;
476 if (!FoundCSE && MI->isCommutable()) {
477 MachineInstr *NewMI = TII->commuteInstruction(MI);
480 FoundCSE = VNT.count(NewMI);
482 // New instruction. It doesn't need to be kept.
483 NewMI->eraseFromParent();
485 } else if (!FoundCSE)
486 // MI was changed but it didn't help, commute it back!
487 (void)TII->commuteInstruction(MI);
491 // If the instruction defines physical registers and the values *may* be
492 // used, then it's not safe to replace it with a common subexpression.
493 // It's also not safe if the instruction uses physical registers.
494 bool CrossMBBPhysDef = false;
495 SmallSet<unsigned, 8> PhysRefs;
496 SmallVector<unsigned, 2> PhysDefs;
497 bool PhysUseDef = false;
498 if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs,
499 PhysDefs, PhysUseDef)) {
502 // ... Unless the CS is local or is in the sole predecessor block
503 // and it also defines the physical register which is not clobbered
504 // in between and the physical register uses were not clobbered.
505 // This can never be the case if the instruction both uses and
506 // defines the same physical register, which was detected above.
508 unsigned CSVN = VNT.lookup(MI);
509 MachineInstr *CSMI = Exps[CSVN];
510 if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
516 VNT.insert(MI, CurrVN++);
521 // Found a common subexpression, eliminate it.
522 unsigned CSVN = VNT.lookup(MI);
523 MachineInstr *CSMI = Exps[CSVN];
524 DEBUG(dbgs() << "Examining: " << *MI);
525 DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
527 // Check if it's profitable to perform this CSE.
529 unsigned NumDefs = MI->getDesc().getNumDefs() +
530 MI->getDesc().getNumImplicitDefs();
532 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
533 MachineOperand &MO = MI->getOperand(i);
534 if (!MO.isReg() || !MO.isDef())
536 unsigned OldReg = MO.getReg();
537 unsigned NewReg = CSMI->getOperand(i).getReg();
539 // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
540 // we should make sure it is not dead at CSMI.
541 if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
542 ImplicitDefsToUpdate.push_back(i);
543 if (OldReg == NewReg) {
548 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
549 TargetRegisterInfo::isVirtualRegister(NewReg) &&
550 "Do not CSE physical register defs!");
552 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
553 DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
558 // Don't perform CSE if the result of the old instruction cannot exist
559 // within the register class of the new instruction.
560 const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
561 if (!MRI->constrainRegClass(NewReg, OldRC)) {
562 DEBUG(dbgs() << "*** Not the same register class, avoid CSE!\n");
567 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
571 // Actually perform the elimination.
573 for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
574 MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
575 MRI->clearKillFlags(CSEPairs[i].second);
578 // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
579 // we should make sure it is not dead at CSMI.
580 for (unsigned i = 0, e = ImplicitDefsToUpdate.size(); i != e; ++i)
581 CSMI->getOperand(ImplicitDefsToUpdate[i]).setIsDead(false);
583 if (CrossMBBPhysDef) {
584 // Add physical register defs now coming in from a predecessor to MBB
586 while (!PhysDefs.empty()) {
587 unsigned LiveIn = PhysDefs.pop_back_val();
588 if (!MBB->isLiveIn(LiveIn))
589 MBB->addLiveIn(LiveIn);
594 MI->eraseFromParent();
596 if (!PhysRefs.empty())
602 VNT.insert(MI, CurrVN++);
606 ImplicitDefsToUpdate.clear();
612 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
613 /// dominator tree node if its a leaf or all of its children are done. Walk
614 /// up the dominator tree to destroy ancestors which are now done.
616 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
617 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren) {
618 if (OpenChildren[Node])
622 ExitScope(Node->getBlock());
624 // Now traverse upwards to pop ancestors whose offsprings are all done.
625 while (MachineDomTreeNode *Parent = Node->getIDom()) {
626 unsigned Left = --OpenChildren[Parent];
629 ExitScope(Parent->getBlock());
634 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
635 SmallVector<MachineDomTreeNode*, 32> Scopes;
636 SmallVector<MachineDomTreeNode*, 8> WorkList;
637 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
641 // Perform a DFS walk to determine the order of visit.
642 WorkList.push_back(Node);
644 Node = WorkList.pop_back_val();
645 Scopes.push_back(Node);
646 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
647 unsigned NumChildren = Children.size();
648 OpenChildren[Node] = NumChildren;
649 for (unsigned i = 0; i != NumChildren; ++i) {
650 MachineDomTreeNode *Child = Children[i];
651 WorkList.push_back(Child);
653 } while (!WorkList.empty());
656 bool Changed = false;
657 for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
658 MachineDomTreeNode *Node = Scopes[i];
659 MachineBasicBlock *MBB = Node->getBlock();
661 Changed |= ProcessBlock(MBB);
662 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
663 ExitScopeIfDone(Node, OpenChildren);
669 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
670 TII = MF.getTarget().getInstrInfo();
671 TRI = MF.getTarget().getRegisterInfo();
672 MRI = &MF.getRegInfo();
673 AA = &getAnalysis<AliasAnalysis>();
674 DT = &getAnalysis<MachineDominatorTree>();
675 return PerformCSE(DT->getRootNode());