1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "machine-cse"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/MachineDominators.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/ScopedHashTable.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/RecyclingAllocator.h"
31 STATISTIC(NumCoalesces, "Number of copies coalesced");
32 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
33 STATISTIC(NumPhysCSEs,
34 "Number of physreg referencing common subexpr eliminated");
35 STATISTIC(NumCrossBBCSEs,
36 "Number of cross-MBB physreg referencing CS eliminated");
37 STATISTIC(NumCommutes, "Number of copies coalesced after commuting");
40 class MachineCSE : public MachineFunctionPass {
41 const TargetInstrInfo *TII;
42 const TargetRegisterInfo *TRI;
44 MachineDominatorTree *DT;
45 MachineRegisterInfo *MRI;
47 static char ID; // Pass identification
48 MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(5), CurrVN(0) {
49 initializeMachineCSEPass(*PassRegistry::getPassRegistry());
52 virtual bool runOnMachineFunction(MachineFunction &MF);
54 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
56 MachineFunctionPass::getAnalysisUsage(AU);
57 AU.addRequired<AliasAnalysis>();
58 AU.addPreservedID(MachineLoopInfoID);
59 AU.addRequired<MachineDominatorTree>();
60 AU.addPreserved<MachineDominatorTree>();
63 virtual void releaseMemory() {
69 const unsigned LookAheadLimit;
70 typedef RecyclingAllocator<BumpPtrAllocator,
71 ScopedHashTableVal<MachineInstr*, unsigned> > AllocatorTy;
72 typedef ScopedHashTable<MachineInstr*, unsigned,
73 MachineInstrExpressionTrait, AllocatorTy> ScopedHTType;
74 typedef ScopedHTType::ScopeTy ScopeType;
75 DenseMap<MachineBasicBlock*, ScopeType*> ScopeMap;
77 SmallVector<MachineInstr*, 64> Exps;
80 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
81 bool isPhysDefTriviallyDead(unsigned Reg,
82 MachineBasicBlock::const_iterator I,
83 MachineBasicBlock::const_iterator E) const;
84 bool hasLivePhysRegDefUses(const MachineInstr *MI,
85 const MachineBasicBlock *MBB,
86 SmallSet<unsigned,8> &PhysRefs,
87 SmallVector<unsigned,2> &PhysDefs,
88 bool &PhysUseDef) const;
89 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
90 SmallSet<unsigned,8> &PhysRefs,
91 SmallVector<unsigned,2> &PhysDefs,
92 bool &NonLocal) const;
93 bool isCSECandidate(MachineInstr *MI);
94 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
95 MachineInstr *CSMI, MachineInstr *MI);
96 void EnterScope(MachineBasicBlock *MBB);
97 void ExitScope(MachineBasicBlock *MBB);
98 bool ProcessBlock(MachineBasicBlock *MBB);
99 void ExitScopeIfDone(MachineDomTreeNode *Node,
100 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren);
101 bool PerformCSE(MachineDomTreeNode *Node);
103 } // end anonymous namespace
105 char MachineCSE::ID = 0;
106 char &llvm::MachineCSEID = MachineCSE::ID;
107 INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
108 "Machine Common Subexpression Elimination", false, false)
109 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
110 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
111 INITIALIZE_PASS_END(MachineCSE, "machine-cse",
112 "Machine Common Subexpression Elimination", false, false)
114 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
115 MachineBasicBlock *MBB) {
116 bool Changed = false;
117 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
118 MachineOperand &MO = MI->getOperand(i);
119 if (!MO.isReg() || !MO.isUse())
121 unsigned Reg = MO.getReg();
122 if (!TargetRegisterInfo::isVirtualRegister(Reg))
124 if (!MRI->hasOneNonDBGUse(Reg))
125 // Only coalesce single use copies. This ensure the copy will be
128 MachineInstr *DefMI = MRI->getVRegDef(Reg);
129 if (DefMI->getParent() != MBB)
131 if (!DefMI->isCopy())
133 unsigned SrcReg = DefMI->getOperand(1).getReg();
134 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
136 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
138 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg)))
140 DEBUG(dbgs() << "Coalescing: " << *DefMI);
141 DEBUG(dbgs() << "*** to: " << *MI);
143 MRI->clearKillFlags(SrcReg);
144 DefMI->eraseFromParent();
153 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
154 MachineBasicBlock::const_iterator I,
155 MachineBasicBlock::const_iterator E) const {
156 unsigned LookAheadLeft = LookAheadLimit;
157 while (LookAheadLeft) {
158 // Skip over dbg_value's.
159 while (I != E && I->isDebugValue())
163 // Reached end of block, register is obviously dead.
166 bool SeenDef = false;
167 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
168 const MachineOperand &MO = I->getOperand(i);
169 if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
171 if (!MO.isReg() || !MO.getReg())
173 if (!TRI->regsOverlap(MO.getReg(), Reg))
181 // See a def of Reg (or an alias) before encountering any use, it's
191 /// hasLivePhysRegDefUses - Return true if the specified instruction read/write
192 /// physical registers (except for dead defs of physical registers). It also
193 /// returns the physical register def by reference if it's the only one and the
194 /// instruction does not uses a physical register.
195 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
196 const MachineBasicBlock *MBB,
197 SmallSet<unsigned,8> &PhysRefs,
198 SmallVector<unsigned,2> &PhysDefs,
199 bool &PhysUseDef) const{
200 // First, add all uses to PhysRefs.
201 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
202 const MachineOperand &MO = MI->getOperand(i);
203 if (!MO.isReg() || MO.isDef())
205 unsigned Reg = MO.getReg();
208 if (TargetRegisterInfo::isVirtualRegister(Reg))
210 // Reading constant physregs is ok.
211 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
212 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
213 PhysRefs.insert(*AI);
216 // Next, collect all defs into PhysDefs. If any is already in PhysRefs
217 // (which currently contains only uses), set the PhysUseDef flag.
219 MachineBasicBlock::const_iterator I = MI; I = llvm::next(I);
220 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
221 const MachineOperand &MO = MI->getOperand(i);
222 if (!MO.isReg() || !MO.isDef())
224 unsigned Reg = MO.getReg();
227 if (TargetRegisterInfo::isVirtualRegister(Reg))
229 // Check against PhysRefs even if the def is "dead".
230 if (PhysRefs.count(Reg))
232 // If the def is dead, it's ok. But the def may not marked "dead". That's
233 // common since this pass is run before livevariables. We can scan
234 // forward a few instructions and check if it is obviously dead.
235 if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end()))
236 PhysDefs.push_back(Reg);
239 // Finally, add all defs to PhysRefs as well.
240 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
241 for (MCRegAliasIterator AI(PhysDefs[i], TRI, true); AI.isValid(); ++AI)
242 PhysRefs.insert(*AI);
244 return !PhysRefs.empty();
247 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
248 SmallSet<unsigned,8> &PhysRefs,
249 SmallVector<unsigned,2> &PhysDefs,
250 bool &NonLocal) const {
251 // For now conservatively returns false if the common subexpression is
252 // not in the same basic block as the given instruction. The only exception
253 // is if the common subexpression is in the sole predecessor block.
254 const MachineBasicBlock *MBB = MI->getParent();
255 const MachineBasicBlock *CSMBB = CSMI->getParent();
257 bool CrossMBB = false;
259 if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
262 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
263 if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i]))
264 // Avoid extending live range of physical registers if they are
265 //allocatable or reserved.
270 MachineBasicBlock::const_iterator I = CSMI; I = llvm::next(I);
271 MachineBasicBlock::const_iterator E = MI;
272 MachineBasicBlock::const_iterator EE = CSMBB->end();
273 unsigned LookAheadLeft = LookAheadLimit;
274 while (LookAheadLeft) {
275 // Skip over dbg_value's.
276 while (I != E && I != EE && I->isDebugValue())
280 assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
292 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
293 const MachineOperand &MO = I->getOperand(i);
294 // RegMasks go on instructions like calls that clobber lots of physregs.
295 // Don't attempt to CSE across such an instruction.
298 if (!MO.isReg() || !MO.isDef())
300 unsigned MOReg = MO.getReg();
301 if (TargetRegisterInfo::isVirtualRegister(MOReg))
303 if (PhysRefs.count(MOReg))
314 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
315 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
316 MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
320 if (MI->isCopyLike())
323 // Ignore stuff that we obviously can't move.
324 if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
325 MI->hasUnmodeledSideEffects())
329 // Okay, this instruction does a load. As a refinement, we allow the target
330 // to decide whether the loaded value is actually a constant. If so, we can
331 // actually use it as a load.
332 if (!MI->isInvariantLoad(AA))
333 // FIXME: we should be able to hoist loads with no other side effects if
334 // there are no other instructions which can change memory in this loop.
335 // This is a trivial form of alias analysis.
341 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
342 /// common expression that defines Reg.
343 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
344 MachineInstr *CSMI, MachineInstr *MI) {
345 // FIXME: Heuristics that works around the lack the live range splitting.
347 // If CSReg is used at all uses of Reg, CSE should not increase register
348 // pressure of CSReg.
349 bool MayIncreasePressure = true;
350 if (TargetRegisterInfo::isVirtualRegister(CSReg) &&
351 TargetRegisterInfo::isVirtualRegister(Reg)) {
352 MayIncreasePressure = false;
353 SmallPtrSet<MachineInstr*, 8> CSUses;
354 for (MachineRegisterInfo::use_nodbg_iterator I =MRI->use_nodbg_begin(CSReg),
355 E = MRI->use_nodbg_end(); I != E; ++I) {
356 MachineInstr *Use = &*I;
359 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
360 E = MRI->use_nodbg_end(); I != E; ++I) {
361 MachineInstr *Use = &*I;
362 if (!CSUses.count(Use)) {
363 MayIncreasePressure = true;
368 if (!MayIncreasePressure) return true;
370 // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
371 // an immediate predecessor. We don't want to increase register pressure and
372 // end up causing other computation to be spilled.
373 if (MI->isAsCheapAsAMove()) {
374 MachineBasicBlock *CSBB = CSMI->getParent();
375 MachineBasicBlock *BB = MI->getParent();
376 if (CSBB != BB && !CSBB->isSuccessor(BB))
380 // Heuristics #2: If the expression doesn't not use a vr and the only use
381 // of the redundant computation are copies, do not cse.
382 bool HasVRegUse = false;
383 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
384 const MachineOperand &MO = MI->getOperand(i);
385 if (MO.isReg() && MO.isUse() &&
386 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
392 bool HasNonCopyUse = false;
393 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
394 E = MRI->use_nodbg_end(); I != E; ++I) {
395 MachineInstr *Use = &*I;
397 if (!Use->isCopyLike()) {
398 HasNonCopyUse = true;
406 // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
407 // it unless the defined value is already used in the BB of the new use.
409 SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
410 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg),
411 E = MRI->use_nodbg_end(); I != E; ++I) {
412 MachineInstr *Use = &*I;
413 HasPHI |= Use->isPHI();
414 CSBBs.insert(Use->getParent());
419 return CSBBs.count(MI->getParent());
422 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
423 DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
424 ScopeType *Scope = new ScopeType(VNT);
425 ScopeMap[MBB] = Scope;
428 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
429 DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
430 DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
431 assert(SI != ScopeMap.end());
436 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
437 bool Changed = false;
439 SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
440 SmallVector<unsigned, 2> ImplicitDefsToUpdate;
441 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
442 MachineInstr *MI = &*I;
445 if (!isCSECandidate(MI))
448 bool FoundCSE = VNT.count(MI);
450 // Look for trivial copy coalescing opportunities.
451 if (PerformTrivialCoalescing(MI, MBB)) {
454 // After coalescing MI itself may become a copy.
455 if (MI->isCopyLike())
457 FoundCSE = VNT.count(MI);
461 // Commute commutable instructions.
462 bool Commuted = false;
463 if (!FoundCSE && MI->isCommutable()) {
464 MachineInstr *NewMI = TII->commuteInstruction(MI);
467 FoundCSE = VNT.count(NewMI);
469 // New instruction. It doesn't need to be kept.
470 NewMI->eraseFromParent();
472 } else if (!FoundCSE)
473 // MI was changed but it didn't help, commute it back!
474 (void)TII->commuteInstruction(MI);
478 // If the instruction defines physical registers and the values *may* be
479 // used, then it's not safe to replace it with a common subexpression.
480 // It's also not safe if the instruction uses physical registers.
481 bool CrossMBBPhysDef = false;
482 SmallSet<unsigned, 8> PhysRefs;
483 SmallVector<unsigned, 2> PhysDefs;
484 bool PhysUseDef = false;
485 if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs,
486 PhysDefs, PhysUseDef)) {
489 // ... Unless the CS is local or is in the sole predecessor block
490 // and it also defines the physical register which is not clobbered
491 // in between and the physical register uses were not clobbered.
492 // This can never be the case if the instruction both uses and
493 // defines the same physical register, which was detected above.
495 unsigned CSVN = VNT.lookup(MI);
496 MachineInstr *CSMI = Exps[CSVN];
497 if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
503 VNT.insert(MI, CurrVN++);
508 // Found a common subexpression, eliminate it.
509 unsigned CSVN = VNT.lookup(MI);
510 MachineInstr *CSMI = Exps[CSVN];
511 DEBUG(dbgs() << "Examining: " << *MI);
512 DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
514 // Check if it's profitable to perform this CSE.
516 unsigned NumDefs = MI->getDesc().getNumDefs() +
517 MI->getDesc().getNumImplicitDefs();
519 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
520 MachineOperand &MO = MI->getOperand(i);
521 if (!MO.isReg() || !MO.isDef())
523 unsigned OldReg = MO.getReg();
524 unsigned NewReg = CSMI->getOperand(i).getReg();
526 // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
527 // we should make sure it is not dead at CSMI.
528 if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
529 ImplicitDefsToUpdate.push_back(i);
530 if (OldReg == NewReg) {
535 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
536 TargetRegisterInfo::isVirtualRegister(NewReg) &&
537 "Do not CSE physical register defs!");
539 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
540 DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
545 // Don't perform CSE if the result of the old instruction cannot exist
546 // within the register class of the new instruction.
547 const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
548 if (!MRI->constrainRegClass(NewReg, OldRC)) {
549 DEBUG(dbgs() << "*** Not the same register class, avoid CSE!\n");
554 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
558 // Actually perform the elimination.
560 for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
561 MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
562 MRI->clearKillFlags(CSEPairs[i].second);
565 // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
566 // we should make sure it is not dead at CSMI.
567 for (unsigned i = 0, e = ImplicitDefsToUpdate.size(); i != e; ++i)
568 CSMI->getOperand(ImplicitDefsToUpdate[i]).setIsDead(false);
570 if (CrossMBBPhysDef) {
571 // Add physical register defs now coming in from a predecessor to MBB
573 while (!PhysDefs.empty()) {
574 unsigned LiveIn = PhysDefs.pop_back_val();
575 if (!MBB->isLiveIn(LiveIn))
576 MBB->addLiveIn(LiveIn);
581 MI->eraseFromParent();
583 if (!PhysRefs.empty())
589 VNT.insert(MI, CurrVN++);
593 ImplicitDefsToUpdate.clear();
599 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
600 /// dominator tree node if its a leaf or all of its children are done. Walk
601 /// up the dominator tree to destroy ancestors which are now done.
603 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
604 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren) {
605 if (OpenChildren[Node])
609 ExitScope(Node->getBlock());
611 // Now traverse upwards to pop ancestors whose offsprings are all done.
612 while (MachineDomTreeNode *Parent = Node->getIDom()) {
613 unsigned Left = --OpenChildren[Parent];
616 ExitScope(Parent->getBlock());
621 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
622 SmallVector<MachineDomTreeNode*, 32> Scopes;
623 SmallVector<MachineDomTreeNode*, 8> WorkList;
624 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
628 // Perform a DFS walk to determine the order of visit.
629 WorkList.push_back(Node);
631 Node = WorkList.pop_back_val();
632 Scopes.push_back(Node);
633 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
634 unsigned NumChildren = Children.size();
635 OpenChildren[Node] = NumChildren;
636 for (unsigned i = 0; i != NumChildren; ++i) {
637 MachineDomTreeNode *Child = Children[i];
638 WorkList.push_back(Child);
640 } while (!WorkList.empty());
643 bool Changed = false;
644 for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
645 MachineDomTreeNode *Node = Scopes[i];
646 MachineBasicBlock *MBB = Node->getBlock();
648 Changed |= ProcessBlock(MBB);
649 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
650 ExitScopeIfDone(Node, OpenChildren);
656 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
657 TII = MF.getTarget().getInstrInfo();
658 TRI = MF.getTarget().getRegisterInfo();
659 MRI = &MF.getRegInfo();
660 AA = &getAnalysis<AliasAnalysis>();
661 DT = &getAnalysis<MachineDominatorTree>();
662 return PerformCSE(DT->getRootNode());