1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 // FIXME: Now that MachineInstrs have parent pointers, they should always
13 // print themselves using their MachineFunction's TargetMachine.
15 //===----------------------------------------------------------------------===//
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Value.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/MRegisterInfo.h"
23 #include "llvm/Support/LeakDetector.h"
28 // Global variable holding an array of descriptors for machine instructions.
29 // The actual object needs to be created separately for each target machine.
30 // This variable is initialized and reset by class TargetInstrInfo.
32 // FIXME: This should be a property of the target so that more than one target
33 // at a time can be active...
36 extern const TargetInstrDescriptor *TargetInstrDescriptors;
39 // Constructor for instructions with variable #operands
40 MachineInstr::MachineInstr(short opcode, unsigned numOperands)
43 operands(numOperands, MachineOperand()),
45 // Make sure that we get added to a machine basicblock
46 LeakDetector::addGarbageObject(this);
49 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
50 /// not a resize for them. It is expected that if you use this that you call
51 /// add* methods below to fill up the operands, instead of the Set methods.
52 /// Eventually, the "resizing" ctors will be phased out.
54 MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY)
55 : Opcode(opcode), numImplicitRefs(0), parent(0) {
56 operands.reserve(numOperands);
57 // Make sure that we get added to a machine basicblock
58 LeakDetector::addGarbageObject(this);
61 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
62 /// MachineInstr is created and added to the end of the specified basic block.
64 MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
66 : Opcode(opcode), numImplicitRefs(0), parent(0) {
67 assert(MBB && "Cannot use inserting ctor with null basic block!");
68 operands.reserve(numOperands);
69 // Make sure that we get added to a machine basicblock
70 LeakDetector::addGarbageObject(this);
71 MBB->push_back(this); // Add instruction to end of basic block!
74 /// MachineInstr ctor - Copies MachineInstr arg exactly
76 MachineInstr::MachineInstr(const MachineInstr &MI) {
77 Opcode = MI.getOpcode();
78 numImplicitRefs = MI.getNumImplicitRefs();
79 operands.reserve(MI.getNumOperands());
82 for (unsigned i = 0; i < MI.getNumOperands(); ++i)
83 operands.push_back(MachineOperand(MI.getOperand(i)));
85 // Set parent, next, and prev to null
92 MachineInstr::~MachineInstr() {
93 LeakDetector::removeGarbageObject(this);
96 /// clone - Create a copy of 'this' instruction that is identical in all ways
97 /// except the following: the new instruction has no parent and it has no name
99 MachineInstr* MachineInstr::clone() const {
100 return new MachineInstr(*this);
103 /// removeFromParent - This method unlinks 'this' from the containing basic
104 /// block, and returns it, but does not delete it.
105 MachineInstr *MachineInstr::removeFromParent() {
106 assert(getParent() && "Not embedded in a basic block!");
107 getParent()->remove(this);
112 /// OperandComplete - Return true if it's illegal to add a new operand
114 bool MachineInstr::OperandsComplete() const {
115 int NumOperands = TargetInstrDescriptors[Opcode].numOperands;
116 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
117 return true; // Broken: we have all the operands of this instruction!
121 /// replace - Support for replacing opcode and operands of a MachineInstr in
122 /// place. This only resets the size of the operand vector and initializes it.
123 /// The new operands must be set explicitly later.
125 void MachineInstr::replace(short opcode, unsigned numOperands) {
126 assert(getNumImplicitRefs() == 0 &&
127 "This is probably broken because implicit refs are going to be lost.");
130 operands.resize(numOperands, MachineOperand());
133 void MachineInstr::SetMachineOperandVal(unsigned i,
134 MachineOperand::MachineOperandType opTy,
136 assert(i < operands.size()); // may be explicit or implicit op
137 operands[i].opType = opTy;
138 operands[i].contents.value = V;
139 operands[i].extra.regNum = -1;
143 MachineInstr::SetMachineOperandConst(unsigned i,
144 MachineOperand::MachineOperandType opTy,
146 assert(i < getNumOperands()); // must be explicit op
147 assert(TargetInstrDescriptors[Opcode].resultPos != (int) i &&
148 "immed. constant cannot be defined");
150 operands[i].opType = opTy;
151 operands[i].contents.value = NULL;
152 operands[i].contents.immedVal = intValue;
153 operands[i].extra.regNum = -1;
154 operands[i].flags = 0;
157 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
158 assert(i < getNumOperands()); // must be explicit op
160 operands[i].opType = MachineOperand::MO_MachineRegister;
161 operands[i].contents.value = NULL;
162 operands[i].extra.regNum = regNum;
165 // Used only by the SPARC back-end.
166 void MachineInstr::SetRegForOperand(unsigned i, int regNum) {
167 assert(i < getNumOperands()); // must be explicit op
168 operands[i].setRegForValue(regNum);
171 // Used only by the SPARC back-end.
172 void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) {
173 getImplicitOp(i).setRegForValue(regNum);
176 /// substituteValue - Substitute all occurrences of Value* oldVal with newVal
177 /// in all operands and all implicit refs. If defsOnly == true, substitute defs
180 /// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865,
181 /// or make it a static function in that file.
184 MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
185 bool defsOnly, bool notDefsAndUses,
186 bool& someArgsWereIgnored)
188 assert((!defsOnly || !notDefsAndUses) &&
189 "notDefsAndUses is irrelevant if defsOnly == true.");
191 unsigned numSubst = 0;
193 // Substitute operands
194 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
197 notDefsAndUses && (O.isDef() && !O.isUse()) ||
198 !notDefsAndUses && O.isDef())
200 O.getMachineOperand().contents.value = newVal;
203 someArgsWereIgnored = true;
205 // Substitute implicit refs
206 for (unsigned i = 0, N = getNumImplicitRefs(); i < N; ++i)
207 if (getImplicitRef(i) == oldVal) {
208 MachineOperand Op = getImplicitOp(i);
210 notDefsAndUses && (Op.isDef() && !Op.isUse()) ||
211 !notDefsAndUses && Op.isDef())
213 Op.contents.value = newVal;
216 someArgsWereIgnored = true;
221 void MachineInstr::dump() const {
222 std::cerr << " " << *this;
225 static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
227 os << (void*) val; // print address always
228 if (val && val->hasName())
229 os << " " << val->getName(); // print name also, if available
234 static inline void OutputReg(std::ostream &os, unsigned RegNo,
235 const MRegisterInfo *MRI = 0) {
236 if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
238 os << "%" << MRI->get(RegNo).Name;
240 os << "%mreg(" << RegNo << ")";
242 os << "%reg" << RegNo;
245 static void print(const MachineOperand &MO, std::ostream &OS,
246 const TargetMachine *TM) {
247 const MRegisterInfo *MRI = 0;
249 if (TM) MRI = TM->getRegisterInfo();
251 bool CloseParen = true;
254 else if (MO.isLoBits32())
256 else if (MO.isHiBits64())
258 else if (MO.isLoBits64())
263 switch (MO.getType()) {
264 case MachineOperand::MO_VirtualRegister:
265 if (MO.getVRegValue()) {
267 OutputValue(OS, MO.getVRegValue());
268 if (MO.hasAllocatedReg())
271 if (MO.hasAllocatedReg())
272 OutputReg(OS, MO.getReg(), MRI);
274 case MachineOperand::MO_CCRegister:
276 OutputValue(OS, MO.getVRegValue());
277 if (MO.hasAllocatedReg()) {
279 OutputReg(OS, MO.getReg(), MRI);
282 case MachineOperand::MO_MachineRegister:
283 OutputReg(OS, MO.getMachineRegNum(), MRI);
285 case MachineOperand::MO_SignExtendedImmed:
286 OS << (long)MO.getImmedValue();
288 case MachineOperand::MO_UnextendedImmed:
289 OS << (long)MO.getImmedValue();
291 case MachineOperand::MO_PCRelativeDisp: {
292 const Value* opVal = MO.getVRegValue();
293 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
294 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
295 if (opVal->hasName())
296 OS << opVal->getName();
298 OS << (const void*) opVal;
302 case MachineOperand::MO_MachineBasicBlock:
304 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
305 << "," << (void*)MO.getMachineBasicBlock() << ">";
307 case MachineOperand::MO_FrameIndex:
308 OS << "<fi#" << MO.getFrameIndex() << ">";
310 case MachineOperand::MO_ConstantPoolIndex:
311 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
313 case MachineOperand::MO_GlobalAddress:
314 OS << "<ga:" << ((Value*)MO.getGlobal())->getName();
315 if (MO.getOffset()) OS << "+" << MO.getOffset();
318 case MachineOperand::MO_ExternalSymbol:
319 OS << "<es:" << MO.getSymbolName();
320 if (MO.getOffset()) OS << "+" << MO.getOffset();
324 assert(0 && "Unrecognized operand type");
331 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
332 unsigned StartOp = 0;
334 // Specialize printing if op#0 is definition
335 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
336 ::print(getOperand(0), OS, TM);
338 ++StartOp; // Don't print this operand again!
341 // Must check if Target machine is not null because machine BB could not
342 // be attached to a Machine function yet
344 OS << TM->getInstrInfo()->getName(getOpcode());
346 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
347 const MachineOperand& mop = getOperand(i);
351 ::print(mop, OS, TM);
360 // code for printing implicit references
361 if (getNumImplicitRefs()) {
362 OS << "\tImplicitRefs: ";
363 for (unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
365 OutputValue(OS, getImplicitRef(i));
366 if (getImplicitOp(i).isDef())
367 if (getImplicitOp(i).isUse())
378 std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
379 // If the instruction is embedded into a basic block, we can find the target
380 // info for the instruction.
381 if (const MachineBasicBlock *MBB = MI.getParent()) {
382 const MachineFunction *MF = MBB->getParent();
384 MI.print(os, &MF->getTarget());
390 // Otherwise, print it out in the "raw" format without symbolic register names
392 os << TargetInstrDescriptors[MI.getOpcode()].Name;
394 for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
395 os << "\t" << MI.getOperand(i);
396 if (MI.getOperand(i).isDef())
397 if (MI.getOperand(i).isUse())
403 // code for printing implicit references
404 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
405 if (NumOfImpRefs > 0) {
406 os << "\tImplicit: ";
407 for (unsigned z = 0; z < NumOfImpRefs; z++) {
408 OutputValue(os, MI.getImplicitRef(z));
409 if (MI.getImplicitOp(z).isDef())
410 if (MI.getImplicitOp(z).isUse())
421 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
424 else if (MO.isLoBits32())
426 else if (MO.isHiBits64())
428 else if (MO.isLoBits64())
431 switch (MO.getType()) {
432 case MachineOperand::MO_VirtualRegister:
433 if (MO.hasAllocatedReg())
434 OutputReg(OS, MO.getReg());
436 if (MO.getVRegValue()) {
437 if (MO.hasAllocatedReg()) OS << "==";
439 OutputValue(OS, MO.getVRegValue());
442 case MachineOperand::MO_CCRegister:
444 OutputValue(OS, MO.getVRegValue());
445 if (MO.hasAllocatedReg()) {
447 OutputReg(OS, MO.getReg());
450 case MachineOperand::MO_MachineRegister:
451 OutputReg(OS, MO.getMachineRegNum());
453 case MachineOperand::MO_SignExtendedImmed:
454 OS << (long)MO.getImmedValue();
456 case MachineOperand::MO_UnextendedImmed:
457 OS << (long)MO.getImmedValue();
459 case MachineOperand::MO_PCRelativeDisp: {
460 const Value* opVal = MO.getVRegValue();
461 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
462 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
463 if (opVal->hasName())
464 OS << opVal->getName();
466 OS << (const void*) opVal;
470 case MachineOperand::MO_MachineBasicBlock:
472 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
473 << "@" << (void*)MO.getMachineBasicBlock() << ">";
475 case MachineOperand::MO_FrameIndex:
476 OS << "<fi#" << MO.getFrameIndex() << ">";
478 case MachineOperand::MO_ConstantPoolIndex:
479 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
481 case MachineOperand::MO_GlobalAddress:
482 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
484 case MachineOperand::MO_ExternalSymbol:
485 OS << "<es:" << MO.getSymbolName() << ">";
488 assert(0 && "Unrecognized operand type");
492 if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())