1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Function.h"
17 #include "llvm/InlineAsm.h"
18 #include "llvm/Type.h"
19 #include "llvm/Value.h"
20 #include "llvm/Assembly/Writer.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetInstrDesc.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Analysis/AliasAnalysis.h"
30 #include "llvm/Analysis/DebugInfo.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/LeakDetector.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/ADT/FoldingSet.h"
39 //===----------------------------------------------------------------------===//
40 // MachineOperand Implementation
41 //===----------------------------------------------------------------------===//
43 /// AddRegOperandToRegInfo - Add this register operand to the specified
44 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
45 /// explicitly nulled out.
46 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
47 assert(isReg() && "Can only add reg operand to use lists");
49 // If the reginfo pointer is null, just explicitly null out or next/prev
50 // pointers, to ensure they are not garbage.
52 Contents.Reg.Prev = 0;
53 Contents.Reg.Next = 0;
57 // Otherwise, add this operand to the head of the registers use/def list.
58 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
60 // For SSA values, we prefer to keep the definition at the start of the list.
61 // we do this by skipping over the definition if it is at the head of the
63 if (*Head && (*Head)->isDef())
64 Head = &(*Head)->Contents.Reg.Next;
66 Contents.Reg.Next = *Head;
67 if (Contents.Reg.Next) {
68 assert(getReg() == Contents.Reg.Next->getReg() &&
69 "Different regs on the same list!");
70 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
73 Contents.Reg.Prev = Head;
77 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
78 /// MachineRegisterInfo it is linked with.
79 void MachineOperand::RemoveRegOperandFromRegInfo() {
80 assert(isOnRegUseList() && "Reg operand is not on a use list");
81 // Unlink this from the doubly linked list of operands.
82 MachineOperand *NextOp = Contents.Reg.Next;
83 *Contents.Reg.Prev = NextOp;
85 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
86 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
88 Contents.Reg.Prev = 0;
89 Contents.Reg.Next = 0;
92 void MachineOperand::setReg(unsigned Reg) {
93 if (getReg() == Reg) return; // No change.
95 // Otherwise, we have to change the register. If this operand is embedded
96 // into a machine function, we need to update the old and new register's
98 if (MachineInstr *MI = getParent())
99 if (MachineBasicBlock *MBB = MI->getParent())
100 if (MachineFunction *MF = MBB->getParent()) {
101 RemoveRegOperandFromRegInfo();
102 Contents.Reg.RegNo = Reg;
103 AddRegOperandToRegInfo(&MF->getRegInfo());
107 // Otherwise, just change the register, no problem. :)
108 Contents.Reg.RegNo = Reg;
111 /// ChangeToImmediate - Replace this operand with a new immediate operand of
112 /// the specified value. If an operand is known to be an immediate already,
113 /// the setImm method should be used.
114 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
115 // If this operand is currently a register operand, and if this is in a
116 // function, deregister the operand from the register's use/def list.
117 if (isReg() && getParent() && getParent()->getParent() &&
118 getParent()->getParent()->getParent())
119 RemoveRegOperandFromRegInfo();
121 OpKind = MO_Immediate;
122 Contents.ImmVal = ImmVal;
125 /// ChangeToRegister - Replace this operand with a new register operand of
126 /// the specified value. If an operand is known to be an register already,
127 /// the setReg method should be used.
128 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
129 bool isKill, bool isDead, bool isUndef) {
130 // If this operand is already a register operand, use setReg to update the
131 // register's use/def lists.
133 assert(!isEarlyClobber());
136 // Otherwise, change this to a register and set the reg#.
137 OpKind = MO_Register;
138 Contents.Reg.RegNo = Reg;
140 // If this operand is embedded in a function, add the operand to the
141 // register's use/def list.
142 if (MachineInstr *MI = getParent())
143 if (MachineBasicBlock *MBB = MI->getParent())
144 if (MachineFunction *MF = MBB->getParent())
145 AddRegOperandToRegInfo(&MF->getRegInfo());
153 IsEarlyClobber = false;
157 /// isIdenticalTo - Return true if this operand is identical to the specified
159 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
160 if (getType() != Other.getType() ||
161 getTargetFlags() != Other.getTargetFlags())
165 default: llvm_unreachable("Unrecognized operand type");
166 case MachineOperand::MO_Register:
167 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
168 getSubReg() == Other.getSubReg();
169 case MachineOperand::MO_Immediate:
170 return getImm() == Other.getImm();
171 case MachineOperand::MO_FPImmediate:
172 return getFPImm() == Other.getFPImm();
173 case MachineOperand::MO_MachineBasicBlock:
174 return getMBB() == Other.getMBB();
175 case MachineOperand::MO_FrameIndex:
176 return getIndex() == Other.getIndex();
177 case MachineOperand::MO_ConstantPoolIndex:
178 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
179 case MachineOperand::MO_JumpTableIndex:
180 return getIndex() == Other.getIndex();
181 case MachineOperand::MO_GlobalAddress:
182 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
183 case MachineOperand::MO_ExternalSymbol:
184 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
185 getOffset() == Other.getOffset();
186 case MachineOperand::MO_BlockAddress:
187 return getBlockAddress() == Other.getBlockAddress();
191 /// print - Print the specified machine operand.
193 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
194 // If the instruction is embedded into a basic block, we can find the
195 // target info for the instruction.
197 if (const MachineInstr *MI = getParent())
198 if (const MachineBasicBlock *MBB = MI->getParent())
199 if (const MachineFunction *MF = MBB->getParent())
200 TM = &MF->getTarget();
203 case MachineOperand::MO_Register:
204 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
205 OS << "%reg" << getReg();
208 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
210 OS << "%physreg" << getReg();
213 if (getSubReg() != 0)
214 OS << ':' << getSubReg();
216 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
219 bool NeedComma = false;
221 if (NeedComma) OS << ',';
222 if (isEarlyClobber())
223 OS << "earlyclobber,";
228 } else if (isImplicit()) {
233 if (isKill() || isDead() || isUndef()) {
234 if (NeedComma) OS << ',';
235 if (isKill()) OS << "kill";
236 if (isDead()) OS << "dead";
238 if (isKill() || isDead())
246 case MachineOperand::MO_Immediate:
249 case MachineOperand::MO_FPImmediate:
250 if (getFPImm()->getType()->isFloatTy())
251 OS << getFPImm()->getValueAPF().convertToFloat();
253 OS << getFPImm()->getValueAPF().convertToDouble();
255 case MachineOperand::MO_MachineBasicBlock:
256 OS << "<BB#" << getMBB()->getNumber() << ">";
258 case MachineOperand::MO_FrameIndex:
259 OS << "<fi#" << getIndex() << '>';
261 case MachineOperand::MO_ConstantPoolIndex:
262 OS << "<cp#" << getIndex();
263 if (getOffset()) OS << "+" << getOffset();
266 case MachineOperand::MO_JumpTableIndex:
267 OS << "<jt#" << getIndex() << '>';
269 case MachineOperand::MO_GlobalAddress:
271 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
272 if (getOffset()) OS << "+" << getOffset();
275 case MachineOperand::MO_ExternalSymbol:
276 OS << "<es:" << getSymbolName();
277 if (getOffset()) OS << "+" << getOffset();
280 case MachineOperand::MO_BlockAddress:
282 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
286 llvm_unreachable("Unrecognized operand type");
289 if (unsigned TF = getTargetFlags())
290 OS << "[TF=" << TF << ']';
293 //===----------------------------------------------------------------------===//
294 // MachineMemOperand Implementation
295 //===----------------------------------------------------------------------===//
297 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
298 int64_t o, uint64_t s, unsigned int a)
299 : Offset(o), Size(s), V(v),
300 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
301 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
302 assert((isLoad() || isStore()) && "Not a load/store!");
305 /// Profile - Gather unique data for the object.
307 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
308 ID.AddInteger(Offset);
311 ID.AddInteger(Flags);
314 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
315 // The Value and Offset may differ due to CSE. But the flags and size
316 // should be the same.
317 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
318 assert(MMO->getSize() == getSize() && "Size mismatch!");
320 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
321 // Update the alignment value.
322 Flags = (Flags & 7) | ((Log2_32(MMO->getBaseAlignment()) + 1) << 3);
323 // Also update the base and offset, because the new alignment may
324 // not be applicable with the old ones.
326 Offset = MMO->getOffset();
330 /// getAlignment - Return the minimum known alignment in bytes of the
331 /// actual memory reference.
332 uint64_t MachineMemOperand::getAlignment() const {
333 return MinAlign(getBaseAlignment(), getOffset());
336 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
337 assert((MMO.isLoad() || MMO.isStore()) &&
338 "SV has to be a load, store or both.");
340 if (MMO.isVolatile())
349 // Print the address information.
354 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
356 // If the alignment of the memory reference itself differs from the alignment
357 // of the base pointer, print the base alignment explicitly, next to the base
359 if (MMO.getBaseAlignment() != MMO.getAlignment())
360 OS << "(align=" << MMO.getBaseAlignment() << ")";
362 if (MMO.getOffset() != 0)
363 OS << "+" << MMO.getOffset();
366 // Print the alignment of the reference.
367 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
368 MMO.getBaseAlignment() != MMO.getSize())
369 OS << "(align=" << MMO.getAlignment() << ")";
374 //===----------------------------------------------------------------------===//
375 // MachineInstr Implementation
376 //===----------------------------------------------------------------------===//
378 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
379 /// TID NULL and no operands.
380 MachineInstr::MachineInstr()
381 : TID(0), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
382 Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
383 // Make sure that we get added to a machine basicblock
384 LeakDetector::addGarbageObject(this);
387 void MachineInstr::addImplicitDefUseOperands() {
388 if (TID->ImplicitDefs)
389 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
390 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
391 if (TID->ImplicitUses)
392 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
393 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
396 /// MachineInstr ctor - This constructor create a MachineInstr and add the
397 /// implicit operands. It reserves space for number of operands specified by
398 /// TargetInstrDesc or the numOperands if it is not zero. (for
399 /// instructions with variable number of operands).
400 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
401 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
402 MemRefs(0), MemRefsEnd(0), Parent(0),
403 debugLoc(DebugLoc::getUnknownLoc()) {
404 if (!NoImp && TID->getImplicitDefs())
405 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
407 if (!NoImp && TID->getImplicitUses())
408 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
410 Operands.reserve(NumImplicitOps + TID->getNumOperands());
412 addImplicitDefUseOperands();
413 // Make sure that we get added to a machine basicblock
414 LeakDetector::addGarbageObject(this);
417 /// MachineInstr ctor - As above, but with a DebugLoc.
418 MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
420 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
421 Parent(0), debugLoc(dl) {
422 if (!NoImp && TID->getImplicitDefs())
423 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
425 if (!NoImp && TID->getImplicitUses())
426 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
428 Operands.reserve(NumImplicitOps + TID->getNumOperands());
430 addImplicitDefUseOperands();
431 // Make sure that we get added to a machine basicblock
432 LeakDetector::addGarbageObject(this);
435 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
436 /// that the MachineInstr is created and added to the end of the specified
439 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
440 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
441 MemRefs(0), MemRefsEnd(0), Parent(0),
442 debugLoc(DebugLoc::getUnknownLoc()) {
443 assert(MBB && "Cannot use inserting ctor with null basic block!");
444 if (TID->ImplicitDefs)
445 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
447 if (TID->ImplicitUses)
448 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
450 Operands.reserve(NumImplicitOps + TID->getNumOperands());
451 addImplicitDefUseOperands();
452 // Make sure that we get added to a machine basicblock
453 LeakDetector::addGarbageObject(this);
454 MBB->push_back(this); // Add instruction to end of basic block!
457 /// MachineInstr ctor - As above, but with a DebugLoc.
459 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
460 const TargetInstrDesc &tid)
461 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
462 Parent(0), debugLoc(dl) {
463 assert(MBB && "Cannot use inserting ctor with null basic block!");
464 if (TID->ImplicitDefs)
465 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
467 if (TID->ImplicitUses)
468 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
470 Operands.reserve(NumImplicitOps + TID->getNumOperands());
471 addImplicitDefUseOperands();
472 // Make sure that we get added to a machine basicblock
473 LeakDetector::addGarbageObject(this);
474 MBB->push_back(this); // Add instruction to end of basic block!
477 /// MachineInstr ctor - Copies MachineInstr arg exactly
479 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
480 : TID(&MI.getDesc()), NumImplicitOps(0), AsmPrinterFlags(0),
481 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
482 Parent(0), debugLoc(MI.getDebugLoc()) {
483 Operands.reserve(MI.getNumOperands());
486 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
487 addOperand(MI.getOperand(i));
488 NumImplicitOps = MI.NumImplicitOps;
490 // Set parent to null.
493 LeakDetector::addGarbageObject(this);
496 MachineInstr::~MachineInstr() {
497 LeakDetector::removeGarbageObject(this);
499 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
500 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
501 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
502 "Reg operand def/use list corrupted");
507 /// getRegInfo - If this instruction is embedded into a MachineFunction,
508 /// return the MachineRegisterInfo object for the current function, otherwise
510 MachineRegisterInfo *MachineInstr::getRegInfo() {
511 if (MachineBasicBlock *MBB = getParent())
512 return &MBB->getParent()->getRegInfo();
516 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
517 /// this instruction from their respective use lists. This requires that the
518 /// operands already be on their use lists.
519 void MachineInstr::RemoveRegOperandsFromUseLists() {
520 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
521 if (Operands[i].isReg())
522 Operands[i].RemoveRegOperandFromRegInfo();
526 /// AddRegOperandsToUseLists - Add all of the register operands in
527 /// this instruction from their respective use lists. This requires that the
528 /// operands not be on their use lists yet.
529 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
530 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
531 if (Operands[i].isReg())
532 Operands[i].AddRegOperandToRegInfo(&RegInfo);
537 /// addOperand - Add the specified operand to the instruction. If it is an
538 /// implicit operand, it is added to the end of the operand list. If it is
539 /// an explicit operand it is added at the end of the explicit operand list
540 /// (before the first implicit operand).
541 void MachineInstr::addOperand(const MachineOperand &Op) {
542 bool isImpReg = Op.isReg() && Op.isImplicit();
543 assert((isImpReg || !OperandsComplete()) &&
544 "Trying to add an operand to a machine instr that is already done!");
546 MachineRegisterInfo *RegInfo = getRegInfo();
548 // If we are adding the operand to the end of the list, our job is simpler.
549 // This is true most of the time, so this is a reasonable optimization.
550 if (isImpReg || NumImplicitOps == 0) {
551 // We can only do this optimization if we know that the operand list won't
553 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
554 Operands.push_back(Op);
556 // Set the parent of the operand.
557 Operands.back().ParentMI = this;
559 // If the operand is a register, update the operand's use list.
561 Operands.back().AddRegOperandToRegInfo(RegInfo);
562 // If the register operand is flagged as early, mark the operand as such
563 unsigned OpNo = Operands.size() - 1;
564 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
565 Operands[OpNo].setIsEarlyClobber(true);
571 // Otherwise, we have to insert a real operand before any implicit ones.
572 unsigned OpNo = Operands.size()-NumImplicitOps;
574 // If this instruction isn't embedded into a function, then we don't need to
575 // update any operand lists.
577 // Simple insertion, no reginfo update needed for other register operands.
578 Operands.insert(Operands.begin()+OpNo, Op);
579 Operands[OpNo].ParentMI = this;
581 // Do explicitly set the reginfo for this operand though, to ensure the
582 // next/prev fields are properly nulled out.
583 if (Operands[OpNo].isReg()) {
584 Operands[OpNo].AddRegOperandToRegInfo(0);
585 // If the register operand is flagged as early, mark the operand as such
586 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
587 Operands[OpNo].setIsEarlyClobber(true);
590 } else if (Operands.size()+1 <= Operands.capacity()) {
591 // Otherwise, we have to remove register operands from their register use
592 // list, add the operand, then add the register operands back to their use
593 // list. This also must handle the case when the operand list reallocates
594 // to somewhere else.
596 // If insertion of this operand won't cause reallocation of the operand
597 // list, just remove the implicit operands, add the operand, then re-add all
598 // the rest of the operands.
599 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
600 assert(Operands[i].isReg() && "Should only be an implicit reg!");
601 Operands[i].RemoveRegOperandFromRegInfo();
604 // Add the operand. If it is a register, add it to the reg list.
605 Operands.insert(Operands.begin()+OpNo, Op);
606 Operands[OpNo].ParentMI = this;
608 if (Operands[OpNo].isReg()) {
609 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
610 // If the register operand is flagged as early, mark the operand as such
611 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
612 Operands[OpNo].setIsEarlyClobber(true);
615 // Re-add all the implicit ops.
616 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
617 assert(Operands[i].isReg() && "Should only be an implicit reg!");
618 Operands[i].AddRegOperandToRegInfo(RegInfo);
621 // Otherwise, we will be reallocating the operand list. Remove all reg
622 // operands from their list, then readd them after the operand list is
624 RemoveRegOperandsFromUseLists();
626 Operands.insert(Operands.begin()+OpNo, Op);
627 Operands[OpNo].ParentMI = this;
629 // Re-add all the operands.
630 AddRegOperandsToUseLists(*RegInfo);
632 // If the register operand is flagged as early, mark the operand as such
633 if (Operands[OpNo].isReg()
634 && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
635 Operands[OpNo].setIsEarlyClobber(true);
639 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
640 /// fewer operand than it started with.
642 void MachineInstr::RemoveOperand(unsigned OpNo) {
643 assert(OpNo < Operands.size() && "Invalid operand number");
645 // Special case removing the last one.
646 if (OpNo == Operands.size()-1) {
647 // If needed, remove from the reg def/use list.
648 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
649 Operands.back().RemoveRegOperandFromRegInfo();
655 // Otherwise, we are removing an interior operand. If we have reginfo to
656 // update, remove all operands that will be shifted down from their reg lists,
657 // move everything down, then re-add them.
658 MachineRegisterInfo *RegInfo = getRegInfo();
660 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
661 if (Operands[i].isReg())
662 Operands[i].RemoveRegOperandFromRegInfo();
666 Operands.erase(Operands.begin()+OpNo);
669 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
670 if (Operands[i].isReg())
671 Operands[i].AddRegOperandToRegInfo(RegInfo);
676 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
677 /// This function should be used only occasionally. The setMemRefs function
678 /// is the primary method for setting up a MachineInstr's MemRefs list.
679 void MachineInstr::addMemOperand(MachineFunction &MF,
680 MachineMemOperand *MO) {
681 mmo_iterator OldMemRefs = MemRefs;
682 mmo_iterator OldMemRefsEnd = MemRefsEnd;
684 size_t NewNum = (MemRefsEnd - MemRefs) + 1;
685 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
686 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
688 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
689 NewMemRefs[NewNum - 1] = MO;
691 MemRefs = NewMemRefs;
692 MemRefsEnd = NewMemRefsEnd;
695 /// removeFromParent - This method unlinks 'this' from the containing basic
696 /// block, and returns it, but does not delete it.
697 MachineInstr *MachineInstr::removeFromParent() {
698 assert(getParent() && "Not embedded in a basic block!");
699 getParent()->remove(this);
704 /// eraseFromParent - This method unlinks 'this' from the containing basic
705 /// block, and deletes it.
706 void MachineInstr::eraseFromParent() {
707 assert(getParent() && "Not embedded in a basic block!");
708 getParent()->erase(this);
712 /// OperandComplete - Return true if it's illegal to add a new operand
714 bool MachineInstr::OperandsComplete() const {
715 unsigned short NumOperands = TID->getNumOperands();
716 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
717 return true; // Broken: we have all the operands of this instruction!
721 /// getNumExplicitOperands - Returns the number of non-implicit operands.
723 unsigned MachineInstr::getNumExplicitOperands() const {
724 unsigned NumOperands = TID->getNumOperands();
725 if (!TID->isVariadic())
728 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
729 const MachineOperand &MO = getOperand(i);
730 if (!MO.isReg() || !MO.isImplicit())
737 /// isLabel - Returns true if the MachineInstr represents a label.
739 bool MachineInstr::isLabel() const {
740 return getOpcode() == TargetInstrInfo::DBG_LABEL ||
741 getOpcode() == TargetInstrInfo::EH_LABEL ||
742 getOpcode() == TargetInstrInfo::GC_LABEL;
745 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
747 bool MachineInstr::isDebugLabel() const {
748 return getOpcode() == TargetInstrInfo::DBG_LABEL;
751 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
752 /// the specific register or -1 if it is not found. It further tightens
753 /// the search criteria to a use that kills the register if isKill is true.
754 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
755 const TargetRegisterInfo *TRI) const {
756 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
757 const MachineOperand &MO = getOperand(i);
758 if (!MO.isReg() || !MO.isUse())
760 unsigned MOReg = MO.getReg();
765 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
766 TargetRegisterInfo::isPhysicalRegister(Reg) &&
767 TRI->isSubRegister(MOReg, Reg)))
768 if (!isKill || MO.isKill())
774 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
775 /// the specified register or -1 if it is not found. If isDead is true, defs
776 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
777 /// also checks if there is a def of a super-register.
778 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
779 const TargetRegisterInfo *TRI) const {
780 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
781 const MachineOperand &MO = getOperand(i);
782 if (!MO.isReg() || !MO.isDef())
784 unsigned MOReg = MO.getReg();
787 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
788 TargetRegisterInfo::isPhysicalRegister(Reg) &&
789 TRI->isSubRegister(MOReg, Reg)))
790 if (!isDead || MO.isDead())
796 /// findFirstPredOperandIdx() - Find the index of the first operand in the
797 /// operand list that is used to represent the predicate. It returns -1 if
799 int MachineInstr::findFirstPredOperandIdx() const {
800 const TargetInstrDesc &TID = getDesc();
801 if (TID.isPredicable()) {
802 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
803 if (TID.OpInfo[i].isPredicate())
810 /// isRegTiedToUseOperand - Given the index of a register def operand,
811 /// check if the register def is tied to a source operand, due to either
812 /// two-address elimination or inline assembly constraints. Returns the
813 /// first tied use operand index by reference is UseOpIdx is not null.
815 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
816 if (getOpcode() == TargetInstrInfo::INLINEASM) {
817 assert(DefOpIdx >= 2);
818 const MachineOperand &MO = getOperand(DefOpIdx);
819 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
821 // Determine the actual operand index that corresponds to this index.
823 unsigned DefPart = 0;
824 for (unsigned i = 1, e = getNumOperands(); i < e; ) {
825 const MachineOperand &FMO = getOperand(i);
826 // After the normal asm operands there may be additional imp-def regs.
829 // Skip over this def.
830 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
831 unsigned PrevDef = i + 1;
832 i = PrevDef + NumOps;
834 DefPart = DefOpIdx - PrevDef;
839 for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
840 const MachineOperand &FMO = getOperand(i);
843 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
846 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
849 *UseOpIdx = (unsigned)i + 1 + DefPart;
856 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
857 const TargetInstrDesc &TID = getDesc();
858 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
859 const MachineOperand &MO = getOperand(i);
860 if (MO.isReg() && MO.isUse() &&
861 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
863 *UseOpIdx = (unsigned)i;
870 /// isRegTiedToDefOperand - Return true if the operand of the specified index
871 /// is a register use and it is tied to an def operand. It also returns the def
872 /// operand index by reference.
874 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
875 if (getOpcode() == TargetInstrInfo::INLINEASM) {
876 const MachineOperand &MO = getOperand(UseOpIdx);
877 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
880 // Find the flag operand corresponding to UseOpIdx
881 unsigned FlagIdx, NumOps=0;
882 for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
883 const MachineOperand &UFMO = getOperand(FlagIdx);
884 // After the normal asm operands there may be additional imp-def regs.
887 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
888 assert(NumOps < getNumOperands() && "Invalid inline asm flag");
889 if (UseOpIdx < FlagIdx+NumOps+1)
892 if (FlagIdx >= UseOpIdx)
894 const MachineOperand &UFMO = getOperand(FlagIdx);
896 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
901 // Remember to adjust the index. First operand is asm string, then there
902 // is a flag for each.
904 const MachineOperand &FMO = getOperand(DefIdx);
906 // Skip over this def.
907 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
910 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
916 const TargetInstrDesc &TID = getDesc();
917 if (UseOpIdx >= TID.getNumOperands())
919 const MachineOperand &MO = getOperand(UseOpIdx);
920 if (!MO.isReg() || !MO.isUse())
922 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
926 *DefOpIdx = (unsigned)DefIdx;
930 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
932 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
933 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
934 const MachineOperand &MO = MI->getOperand(i);
935 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
937 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
938 MachineOperand &MOp = getOperand(j);
939 if (!MOp.isIdenticalTo(MO))
950 /// copyPredicates - Copies predicate operand(s) from MI.
951 void MachineInstr::copyPredicates(const MachineInstr *MI) {
952 const TargetInstrDesc &TID = MI->getDesc();
953 if (!TID.isPredicable())
955 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
956 if (TID.OpInfo[i].isPredicate()) {
957 // Predicated operands must be last operands.
958 addOperand(MI->getOperand(i));
963 /// isSafeToMove - Return true if it is safe to move this instruction. If
964 /// SawStore is set to true, it means that there is a store (or call) between
965 /// the instruction's location and its intended destination.
966 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
968 AliasAnalysis *AA) const {
969 // Ignore stuff that we obviously can't move.
970 if (TID->mayStore() || TID->isCall()) {
974 if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
977 // See if this instruction does a load. If so, we have to guarantee that the
978 // loaded value doesn't change between the load and the its intended
979 // destination. The check for isInvariantLoad gives the targe the chance to
980 // classify the load as always returning a constant, e.g. a constant pool
982 if (TID->mayLoad() && !isInvariantLoad(AA))
983 // Otherwise, this is a real load. If there is a store between the load and
984 // end of block, or if the load is volatile, we can't move it.
985 return !SawStore && !hasVolatileMemoryRef();
990 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
991 /// instruction which defined the specified register instead of copying it.
992 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
994 AliasAnalysis *AA) const {
995 bool SawStore = false;
996 if (!TII->isTriviallyReMaterializable(this, AA) ||
997 !isSafeToMove(TII, SawStore, AA))
999 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1000 const MachineOperand &MO = getOperand(i);
1003 // FIXME: For now, do not remat any instruction with register operands.
1004 // Later on, we can loosen the restriction is the register operands have
1005 // not been modified between the def and use. Note, this is different from
1006 // MachineSink because the code is no longer in two-address form (at least
1010 else if (!MO.isDead() && MO.getReg() != DstReg)
1016 /// hasVolatileMemoryRef - Return true if this instruction may have a
1017 /// volatile memory reference, or if the information describing the
1018 /// memory reference is not available. Return false if it is known to
1019 /// have no volatile memory references.
1020 bool MachineInstr::hasVolatileMemoryRef() const {
1021 // An instruction known never to access memory won't have a volatile access.
1022 if (!TID->mayStore() &&
1025 !TID->hasUnmodeledSideEffects())
1028 // Otherwise, if the instruction has no memory reference information,
1029 // conservatively assume it wasn't preserved.
1030 if (memoperands_empty())
1033 // Check the memory reference information for volatile references.
1034 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1035 if ((*I)->isVolatile())
1041 /// isInvariantLoad - Return true if this instruction is loading from a
1042 /// location whose value is invariant across the function. For example,
1043 /// loading a value from the constant pool or from from the argument area
1044 /// of a function if it does not change. This should only return true of
1045 /// *all* loads the instruction does are invariant (if it does multiple loads).
1046 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1047 // If the instruction doesn't load at all, it isn't an invariant load.
1048 if (!TID->mayLoad())
1051 // If the instruction has lost its memoperands, conservatively assume that
1052 // it may not be an invariant load.
1053 if (memoperands_empty())
1056 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1058 for (mmo_iterator I = memoperands_begin(),
1059 E = memoperands_end(); I != E; ++I) {
1060 if ((*I)->isVolatile()) return false;
1061 if ((*I)->isStore()) return false;
1063 if (const Value *V = (*I)->getValue()) {
1064 // A load from a constant PseudoSourceValue is invariant.
1065 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1066 if (PSV->isConstant(MFI))
1068 // If we have an AliasAnalysis, ask it whether the memory is constant.
1069 if (AA && AA->pointsToConstantMemory(V))
1073 // Otherwise assume conservatively.
1077 // Everything checks out.
1081 /// isConstantValuePHI - If the specified instruction is a PHI that always
1082 /// merges together the same virtual register, return the register, otherwise
1084 unsigned MachineInstr::isConstantValuePHI() const {
1085 if (getOpcode() != TargetInstrInfo::PHI)
1087 assert(getNumOperands() >= 3 &&
1088 "It's illegal to have a PHI without source operands");
1090 unsigned Reg = getOperand(1).getReg();
1091 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1092 if (getOperand(i).getReg() != Reg)
1097 void MachineInstr::dump() const {
1098 dbgs() << " " << *this;
1101 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1102 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1103 const MachineFunction *MF = 0;
1104 if (const MachineBasicBlock *MBB = getParent()) {
1105 MF = MBB->getParent();
1107 TM = &MF->getTarget();
1110 // Print explicitly defined operands on the left of an assignment syntax.
1111 unsigned StartOp = 0, e = getNumOperands();
1112 for (; StartOp < e && getOperand(StartOp).isReg() &&
1113 getOperand(StartOp).isDef() &&
1114 !getOperand(StartOp).isImplicit();
1116 if (StartOp != 0) OS << ", ";
1117 getOperand(StartOp).print(OS, TM);
1123 // Print the opcode name.
1124 OS << getDesc().getName();
1126 // Print the rest of the operands.
1127 bool OmittedAnyCallClobbers = false;
1128 bool FirstOp = true;
1129 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1130 const MachineOperand &MO = getOperand(i);
1132 // Omit call-clobbered registers which aren't used anywhere. This makes
1133 // call instructions much less noisy on targets where calls clobber lots
1134 // of registers. Don't rely on MO.isDead() because we may be called before
1135 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1136 if (MF && getDesc().isCall() &&
1137 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1138 unsigned Reg = MO.getReg();
1139 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
1140 const MachineRegisterInfo &MRI = MF->getRegInfo();
1141 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1142 bool HasAliasLive = false;
1143 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1144 unsigned AliasReg = *Alias; ++Alias)
1145 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1146 HasAliasLive = true;
1149 if (!HasAliasLive) {
1150 OmittedAnyCallClobbers = true;
1157 if (FirstOp) FirstOp = false; else OS << ",";
1162 // Briefly indicate whether any call clobbers were omitted.
1163 if (OmittedAnyCallClobbers) {
1164 if (!FirstOp) OS << ",";
1168 bool HaveSemi = false;
1169 if (!memoperands_empty()) {
1170 if (!HaveSemi) OS << ";"; HaveSemi = true;
1173 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1181 if (!debugLoc.isUnknown() && MF) {
1182 if (!HaveSemi) OS << ";";
1184 // TODO: print InlinedAtLoc information
1186 DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc);
1187 DIScope Scope(DLT.Scope);
1189 // Omit the directory, since it's usually long and uninteresting.
1190 if (!Scope.isNull())
1191 OS << Scope.getFilename();
1194 OS << ':' << DLT.Line;
1196 OS << ':' << DLT.Col;
1202 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1203 const TargetRegisterInfo *RegInfo,
1204 bool AddIfNotFound) {
1205 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1206 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1208 SmallVector<unsigned,4> DeadOps;
1209 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1210 MachineOperand &MO = getOperand(i);
1211 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1213 unsigned Reg = MO.getReg();
1217 if (Reg == IncomingReg) {
1220 // The register is already marked kill.
1222 if (isPhysReg && isRegTiedToDefOperand(i))
1223 // Two-address uses of physregs must not be marked kill.
1228 } else if (hasAliases && MO.isKill() &&
1229 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1230 // A super-register kill already exists.
1231 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1233 if (RegInfo->isSubRegister(IncomingReg, Reg))
1234 DeadOps.push_back(i);
1238 // Trim unneeded kill operands.
1239 while (!DeadOps.empty()) {
1240 unsigned OpIdx = DeadOps.back();
1241 if (getOperand(OpIdx).isImplicit())
1242 RemoveOperand(OpIdx);
1244 getOperand(OpIdx).setIsKill(false);
1248 // If not found, this means an alias of one of the operands is killed. Add a
1249 // new implicit operand if required.
1250 if (!Found && AddIfNotFound) {
1251 addOperand(MachineOperand::CreateReg(IncomingReg,
1260 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1261 const TargetRegisterInfo *RegInfo,
1262 bool AddIfNotFound) {
1263 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1264 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1266 SmallVector<unsigned,4> DeadOps;
1267 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1268 MachineOperand &MO = getOperand(i);
1269 if (!MO.isReg() || !MO.isDef())
1271 unsigned Reg = MO.getReg();
1275 if (Reg == IncomingReg) {
1278 // The register is already marked dead.
1283 } else if (hasAliases && MO.isDead() &&
1284 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1285 // There exists a super-register that's marked dead.
1286 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1288 if (RegInfo->getSubRegisters(IncomingReg) &&
1289 RegInfo->getSuperRegisters(Reg) &&
1290 RegInfo->isSubRegister(IncomingReg, Reg))
1291 DeadOps.push_back(i);
1295 // Trim unneeded dead operands.
1296 while (!DeadOps.empty()) {
1297 unsigned OpIdx = DeadOps.back();
1298 if (getOperand(OpIdx).isImplicit())
1299 RemoveOperand(OpIdx);
1301 getOperand(OpIdx).setIsDead(false);
1305 // If not found, this means an alias of one of the operands is dead. Add a
1306 // new implicit operand if required.
1307 if (Found || !AddIfNotFound)
1310 addOperand(MachineOperand::CreateReg(IncomingReg,