1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Constants.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/Value.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetInstrDesc.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Support/MathExtras.h"
25 #include "llvm/Support/Streams.h"
29 //===----------------------------------------------------------------------===//
30 // MachineOperand Implementation
31 //===----------------------------------------------------------------------===//
33 /// AddRegOperandToRegInfo - Add this register operand to the specified
34 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
35 /// explicitly nulled out.
36 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
37 assert(isReg() && "Can only add reg operand to use lists");
39 // If the reginfo pointer is null, just explicitly null out or next/prev
40 // pointers, to ensure they are not garbage.
42 Contents.Reg.Prev = 0;
43 Contents.Reg.Next = 0;
47 // Otherwise, add this operand to the head of the registers use/def list.
48 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
50 // For SSA values, we prefer to keep the definition at the start of the list.
51 // we do this by skipping over the definition if it is at the head of the
53 if (*Head && (*Head)->isDef())
54 Head = &(*Head)->Contents.Reg.Next;
56 Contents.Reg.Next = *Head;
57 if (Contents.Reg.Next) {
58 assert(getReg() == Contents.Reg.Next->getReg() &&
59 "Different regs on the same list!");
60 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
63 Contents.Reg.Prev = Head;
67 void MachineOperand::setReg(unsigned Reg) {
68 if (getReg() == Reg) return; // No change.
70 // Otherwise, we have to change the register. If this operand is embedded
71 // into a machine function, we need to update the old and new register's
73 if (MachineInstr *MI = getParent())
74 if (MachineBasicBlock *MBB = MI->getParent())
75 if (MachineFunction *MF = MBB->getParent()) {
76 RemoveRegOperandFromRegInfo();
77 Contents.Reg.RegNo = Reg;
78 AddRegOperandToRegInfo(&MF->getRegInfo());
82 // Otherwise, just change the register, no problem. :)
83 Contents.Reg.RegNo = Reg;
86 /// ChangeToImmediate - Replace this operand with a new immediate operand of
87 /// the specified value. If an operand is known to be an immediate already,
88 /// the setImm method should be used.
89 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
90 // If this operand is currently a register operand, and if this is in a
91 // function, deregister the operand from the register's use/def list.
92 if (isReg() && getParent() && getParent()->getParent() &&
93 getParent()->getParent()->getParent())
94 RemoveRegOperandFromRegInfo();
96 OpKind = MO_Immediate;
97 Contents.ImmVal = ImmVal;
100 /// ChangeToRegister - Replace this operand with a new register operand of
101 /// the specified value. If an operand is known to be an register already,
102 /// the setReg method should be used.
103 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
104 bool isKill, bool isDead) {
105 // If this operand is already a register operand, use setReg to update the
106 // register's use/def lists.
110 // Otherwise, change this to a register and set the reg#.
111 OpKind = MO_Register;
112 Contents.Reg.RegNo = Reg;
114 // If this operand is embedded in a function, add the operand to the
115 // register's use/def list.
116 if (MachineInstr *MI = getParent())
117 if (MachineBasicBlock *MBB = MI->getParent())
118 if (MachineFunction *MF = MBB->getParent())
119 AddRegOperandToRegInfo(&MF->getRegInfo());
129 /// isIdenticalTo - Return true if this operand is identical to the specified
131 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
132 if (getType() != Other.getType()) return false;
135 default: assert(0 && "Unrecognized operand type");
136 case MachineOperand::MO_Register:
137 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
138 getSubReg() == Other.getSubReg();
139 case MachineOperand::MO_Immediate:
140 return getImm() == Other.getImm();
141 case MachineOperand::MO_FPImmediate:
142 return getFPImm() == Other.getFPImm();
143 case MachineOperand::MO_MachineBasicBlock:
144 return getMBB() == Other.getMBB();
145 case MachineOperand::MO_FrameIndex:
146 return getIndex() == Other.getIndex();
147 case MachineOperand::MO_ConstantPoolIndex:
148 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
149 case MachineOperand::MO_JumpTableIndex:
150 return getIndex() == Other.getIndex();
151 case MachineOperand::MO_GlobalAddress:
152 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
153 case MachineOperand::MO_ExternalSymbol:
154 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
155 getOffset() == Other.getOffset();
159 /// print - Print the specified machine operand.
161 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
163 case MachineOperand::MO_Register:
164 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
165 OS << "%reg" << getReg();
167 // If the instruction is embedded into a basic block, we can find the
168 // target info for the instruction.
170 if (const MachineInstr *MI = getParent())
171 if (const MachineBasicBlock *MBB = MI->getParent())
172 if (const MachineFunction *MF = MBB->getParent())
173 TM = &MF->getTarget();
176 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
178 OS << "%mreg" << getReg();
181 if (isDef() || isKill() || isDead() || isImplicit()) {
183 bool NeedComma = false;
185 OS << (isDef() ? "imp-def" : "imp-use");
187 } else if (isDef()) {
191 if (isKill() || isDead()) {
192 if (NeedComma) OS << ",";
193 if (isKill()) OS << "kill";
194 if (isDead()) OS << "dead";
199 case MachineOperand::MO_Immediate:
202 case MachineOperand::MO_FPImmediate:
203 if (getFPImm()->getType() == Type::FloatTy) {
204 OS << getFPImm()->getValueAPF().convertToFloat();
206 OS << getFPImm()->getValueAPF().convertToDouble();
209 case MachineOperand::MO_MachineBasicBlock:
211 << ((Value*)getMBB()->getBasicBlock())->getName()
212 << "," << (void*)getMBB() << ">";
214 case MachineOperand::MO_FrameIndex:
215 OS << "<fi#" << getIndex() << ">";
217 case MachineOperand::MO_ConstantPoolIndex:
218 OS << "<cp#" << getIndex();
219 if (getOffset()) OS << "+" << getOffset();
222 case MachineOperand::MO_JumpTableIndex:
223 OS << "<jt#" << getIndex() << ">";
225 case MachineOperand::MO_GlobalAddress:
226 OS << "<ga:" << ((Value*)getGlobal())->getName();
227 if (getOffset()) OS << "+" << getOffset();
230 case MachineOperand::MO_ExternalSymbol:
231 OS << "<es:" << getSymbolName();
232 if (getOffset()) OS << "+" << getOffset();
236 assert(0 && "Unrecognized operand type");
240 //===----------------------------------------------------------------------===//
241 // MachineMemOperand Implementation
242 //===----------------------------------------------------------------------===//
244 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
245 int64_t o, uint64_t s, unsigned int a)
246 : Offset(o), Size(s), V(v),
247 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
248 assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
251 //===----------------------------------------------------------------------===//
252 // MachineInstr Implementation
253 //===----------------------------------------------------------------------===//
255 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
256 /// TID NULL and no operands.
257 MachineInstr::MachineInstr()
258 : TID(0), NumImplicitOps(0), Parent(0) {
261 void MachineInstr::addImplicitDefUseOperands() {
262 if (TID->ImplicitDefs)
263 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
264 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
265 if (TID->ImplicitUses)
266 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
267 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
270 /// MachineInstr ctor - This constructor create a MachineInstr and add the
271 /// implicit operands. It reserves space for number of operands specified by
272 /// TargetInstrDesc or the numOperands if it is not zero. (for
273 /// instructions with variable number of operands).
274 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
275 : TID(&tid), NumImplicitOps(0), Parent(0) {
276 if (!NoImp && TID->getImplicitDefs())
277 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
279 if (!NoImp && TID->getImplicitUses())
280 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
282 Operands.reserve(NumImplicitOps + TID->getNumOperands());
284 addImplicitDefUseOperands();
287 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
288 /// MachineInstr is created and added to the end of the specified basic block.
290 MachineInstr::MachineInstr(MachineBasicBlock *MBB,
291 const TargetInstrDesc &tid)
292 : TID(&tid), NumImplicitOps(0), Parent(0) {
293 assert(MBB && "Cannot use inserting ctor with null basic block!");
294 if (TID->ImplicitDefs)
295 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
297 if (TID->ImplicitUses)
298 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
300 Operands.reserve(NumImplicitOps + TID->getNumOperands());
301 addImplicitDefUseOperands();
302 MBB->push_back(this); // Add instruction to end of basic block!
305 /// MachineInstr ctor - Copies MachineInstr arg exactly
307 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) {
309 NumImplicitOps = MI.NumImplicitOps;
310 Operands.reserve(MI.getNumOperands());
313 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
314 Operands.push_back(MI.getOperand(i));
315 Operands.back().ParentMI = this;
318 // Add memory operands.
319 for (alist<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
320 j = MI.memoperands_end(); i != j; ++i)
321 addMemOperand(MF, *i);
323 // Set parent to null.
327 MachineInstr::~MachineInstr() {
328 assert(MemOperands.empty() &&
329 "MachineInstr being deleted with live memoperands!");
331 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
332 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
333 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
334 "Reg operand def/use list corrupted");
339 /// getOpcode - Returns the opcode of this MachineInstr.
341 int MachineInstr::getOpcode() const {
345 /// getRegInfo - If this instruction is embedded into a MachineFunction,
346 /// return the MachineRegisterInfo object for the current function, otherwise
348 MachineRegisterInfo *MachineInstr::getRegInfo() {
349 if (MachineBasicBlock *MBB = getParent())
350 return &MBB->getParent()->getRegInfo();
354 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
355 /// this instruction from their respective use lists. This requires that the
356 /// operands already be on their use lists.
357 void MachineInstr::RemoveRegOperandsFromUseLists() {
358 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
359 if (Operands[i].isReg())
360 Operands[i].RemoveRegOperandFromRegInfo();
364 /// AddRegOperandsToUseLists - Add all of the register operands in
365 /// this instruction from their respective use lists. This requires that the
366 /// operands not be on their use lists yet.
367 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
368 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
369 if (Operands[i].isReg())
370 Operands[i].AddRegOperandToRegInfo(&RegInfo);
375 /// addOperand - Add the specified operand to the instruction. If it is an
376 /// implicit operand, it is added to the end of the operand list. If it is
377 /// an explicit operand it is added at the end of the explicit operand list
378 /// (before the first implicit operand).
379 void MachineInstr::addOperand(const MachineOperand &Op) {
380 bool isImpReg = Op.isReg() && Op.isImplicit();
381 assert((isImpReg || !OperandsComplete()) &&
382 "Trying to add an operand to a machine instr that is already done!");
384 // If we are adding the operand to the end of the list, our job is simpler.
385 // This is true most of the time, so this is a reasonable optimization.
386 if (isImpReg || NumImplicitOps == 0) {
387 // We can only do this optimization if we know that the operand list won't
389 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
390 Operands.push_back(Op);
392 // Set the parent of the operand.
393 Operands.back().ParentMI = this;
395 // If the operand is a register, update the operand's use list.
397 Operands.back().AddRegOperandToRegInfo(getRegInfo());
402 // Otherwise, we have to insert a real operand before any implicit ones.
403 unsigned OpNo = Operands.size()-NumImplicitOps;
405 MachineRegisterInfo *RegInfo = getRegInfo();
407 // If this instruction isn't embedded into a function, then we don't need to
408 // update any operand lists.
410 // Simple insertion, no reginfo update needed for other register operands.
411 Operands.insert(Operands.begin()+OpNo, Op);
412 Operands[OpNo].ParentMI = this;
414 // Do explicitly set the reginfo for this operand though, to ensure the
415 // next/prev fields are properly nulled out.
416 if (Operands[OpNo].isReg())
417 Operands[OpNo].AddRegOperandToRegInfo(0);
419 } else if (Operands.size()+1 <= Operands.capacity()) {
420 // Otherwise, we have to remove register operands from their register use
421 // list, add the operand, then add the register operands back to their use
422 // list. This also must handle the case when the operand list reallocates
423 // to somewhere else.
425 // If insertion of this operand won't cause reallocation of the operand
426 // list, just remove the implicit operands, add the operand, then re-add all
427 // the rest of the operands.
428 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
429 assert(Operands[i].isReg() && "Should only be an implicit reg!");
430 Operands[i].RemoveRegOperandFromRegInfo();
433 // Add the operand. If it is a register, add it to the reg list.
434 Operands.insert(Operands.begin()+OpNo, Op);
435 Operands[OpNo].ParentMI = this;
437 if (Operands[OpNo].isReg())
438 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
440 // Re-add all the implicit ops.
441 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
442 assert(Operands[i].isReg() && "Should only be an implicit reg!");
443 Operands[i].AddRegOperandToRegInfo(RegInfo);
446 // Otherwise, we will be reallocating the operand list. Remove all reg
447 // operands from their list, then readd them after the operand list is
449 RemoveRegOperandsFromUseLists();
451 Operands.insert(Operands.begin()+OpNo, Op);
452 Operands[OpNo].ParentMI = this;
454 // Re-add all the operands.
455 AddRegOperandsToUseLists(*RegInfo);
459 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
460 /// fewer operand than it started with.
462 void MachineInstr::RemoveOperand(unsigned OpNo) {
463 assert(OpNo < Operands.size() && "Invalid operand number");
465 // Special case removing the last one.
466 if (OpNo == Operands.size()-1) {
467 // If needed, remove from the reg def/use list.
468 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
469 Operands.back().RemoveRegOperandFromRegInfo();
475 // Otherwise, we are removing an interior operand. If we have reginfo to
476 // update, remove all operands that will be shifted down from their reg lists,
477 // move everything down, then re-add them.
478 MachineRegisterInfo *RegInfo = getRegInfo();
480 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
481 if (Operands[i].isReg())
482 Operands[i].RemoveRegOperandFromRegInfo();
486 Operands.erase(Operands.begin()+OpNo);
489 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
490 if (Operands[i].isReg())
491 Operands[i].AddRegOperandToRegInfo(RegInfo);
496 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
497 /// referencing arbitrary storage.
498 void MachineInstr::addMemOperand(MachineFunction &MF,
499 const MachineMemOperand &MO) {
500 MemOperands.push_back(MF.CreateMachineMemOperand(MO));
503 /// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
504 void MachineInstr::clearMemOperands(MachineFunction &MF) {
505 while (!MemOperands.empty())
506 MF.DeleteMachineMemOperand(MemOperands.remove(MemOperands.begin()));
510 /// removeFromParent - This method unlinks 'this' from the containing basic
511 /// block, and returns it, but does not delete it.
512 MachineInstr *MachineInstr::removeFromParent() {
513 assert(getParent() && "Not embedded in a basic block!");
514 getParent()->remove(this);
519 /// eraseFromParent - This method unlinks 'this' from the containing basic
520 /// block, and deletes it.
521 void MachineInstr::eraseFromParent() {
522 assert(getParent() && "Not embedded in a basic block!");
523 getParent()->erase(this);
527 /// OperandComplete - Return true if it's illegal to add a new operand
529 bool MachineInstr::OperandsComplete() const {
530 unsigned short NumOperands = TID->getNumOperands();
531 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
532 return true; // Broken: we have all the operands of this instruction!
536 /// getNumExplicitOperands - Returns the number of non-implicit operands.
538 unsigned MachineInstr::getNumExplicitOperands() const {
539 unsigned NumOperands = TID->getNumOperands();
540 if (!TID->isVariadic())
543 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
544 const MachineOperand &MO = getOperand(NumOperands);
545 if (!MO.isRegister() || !MO.isImplicit())
552 /// isLabel - Returns true if the MachineInstr represents a label.
554 bool MachineInstr::isLabel() const {
555 return getOpcode() == TargetInstrInfo::DBG_LABEL ||
556 getOpcode() == TargetInstrInfo::EH_LABEL ||
557 getOpcode() == TargetInstrInfo::GC_LABEL;
560 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
562 bool MachineInstr::isDebugLabel() const {
563 return getOpcode() == TargetInstrInfo::DBG_LABEL;
566 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
567 /// the specific register or -1 if it is not found. It further tightening
568 /// the search criteria to a use that kills the register if isKill is true.
569 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
570 const TargetRegisterInfo *TRI) const {
571 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
572 const MachineOperand &MO = getOperand(i);
573 if (!MO.isRegister() || !MO.isUse())
575 unsigned MOReg = MO.getReg();
580 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
581 TargetRegisterInfo::isPhysicalRegister(Reg) &&
582 TRI->isSubRegister(MOReg, Reg)))
583 if (!isKill || MO.isKill())
589 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
590 /// the specified register or -1 if it is not found. If isDead is true, defs
591 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
592 /// also checks if there is a def of a super-register.
593 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
594 const TargetRegisterInfo *TRI) const {
595 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
596 const MachineOperand &MO = getOperand(i);
597 if (!MO.isRegister() || !MO.isDef())
599 unsigned MOReg = MO.getReg();
602 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
603 TargetRegisterInfo::isPhysicalRegister(Reg) &&
604 TRI->isSubRegister(MOReg, Reg)))
605 if (!isDead || MO.isDead())
611 /// findFirstPredOperandIdx() - Find the index of the first operand in the
612 /// operand list that is used to represent the predicate. It returns -1 if
614 int MachineInstr::findFirstPredOperandIdx() const {
615 const TargetInstrDesc &TID = getDesc();
616 if (TID.isPredicable()) {
617 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
618 if (TID.OpInfo[i].isPredicate())
625 /// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
626 /// check if the register def is a re-definition due to two addr elimination.
627 bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const{
628 const TargetInstrDesc &TID = getDesc();
629 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
630 const MachineOperand &MO = getOperand(i);
631 if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg &&
632 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
638 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
640 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
641 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
642 const MachineOperand &MO = MI->getOperand(i);
643 if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
645 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
646 MachineOperand &MOp = getOperand(j);
647 if (!MOp.isIdenticalTo(MO))
658 /// copyPredicates - Copies predicate operand(s) from MI.
659 void MachineInstr::copyPredicates(const MachineInstr *MI) {
660 const TargetInstrDesc &TID = MI->getDesc();
661 if (!TID.isPredicable())
663 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
664 if (TID.OpInfo[i].isPredicate()) {
665 // Predicated operands must be last operands.
666 addOperand(MI->getOperand(i));
671 /// isSafeToMove - Return true if it is safe to move this instruction. If
672 /// SawStore is set to true, it means that there is a store (or call) between
673 /// the instruction's location and its intended destination.
674 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) {
675 // Ignore stuff that we obviously can't move.
676 if (TID->mayStore() || TID->isCall()) {
680 if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects())
683 // See if this instruction does a load. If so, we have to guarantee that the
684 // loaded value doesn't change between the load and the its intended
685 // destination. The check for isInvariantLoad gives the targe the chance to
686 // classify the load as always returning a constant, e.g. a constant pool
688 if (TID->mayLoad() && !TII->isInvariantLoad(this)) {
689 // Otherwise, this is a real load. If there is a store between the load and
690 // end of block, we can't sink the load.
692 // FIXME: we can't do this transformation until we know that the load is
693 // not volatile, and machineinstrs don't keep this info. :(
701 void MachineInstr::dump() const {
702 cerr << " " << *this;
705 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
706 // Specialize printing if op#0 is definition
707 unsigned StartOp = 0;
708 if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
709 getOperand(0).print(OS, TM);
711 ++StartOp; // Don't print this operand again!
714 OS << getDesc().getName();
716 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
720 getOperand(i).print(OS, TM);
723 if (!memoperands_empty()) {
725 for (alist<MachineMemOperand>::const_iterator i = memoperands_begin(),
726 e = memoperands_end(); i != e; ++i) {
727 const MachineMemOperand &MRO = *i;
728 const Value *V = MRO.getValue();
730 assert((MRO.isLoad() || MRO.isStore()) &&
731 "SV has to be a load, store or both.");
733 if (MRO.isVolatile())
741 OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
745 else if (!V->getName().empty())
747 else if (isa<PseudoSourceValue>(V))
752 OS << " + " << MRO.getOffset() << "]";
759 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
760 const TargetRegisterInfo *RegInfo,
761 bool AddIfNotFound) {
762 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
763 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
764 SmallVector<unsigned,4> DeadOps;
765 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
766 MachineOperand &MO = getOperand(i);
767 if (!MO.isRegister() || !MO.isUse())
769 unsigned Reg = MO.getReg();
773 if (Reg == IncomingReg) {
777 if (hasAliases && MO.isKill() &&
778 TargetRegisterInfo::isPhysicalRegister(Reg)) {
779 // A super-register kill already exists.
780 if (RegInfo->isSuperRegister(IncomingReg, Reg))
782 if (RegInfo->isSubRegister(IncomingReg, Reg))
783 DeadOps.push_back(i);
787 // Trim unneeded kill operands.
788 while (!DeadOps.empty()) {
789 unsigned OpIdx = DeadOps.back();
790 if (getOperand(OpIdx).isImplicit())
791 RemoveOperand(OpIdx);
793 getOperand(OpIdx).setIsKill(false);
797 // If not found, this means an alias of one of the operands is killed. Add a
798 // new implicit operand if required.
800 addOperand(MachineOperand::CreateReg(IncomingReg,
809 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
810 const TargetRegisterInfo *RegInfo,
811 bool AddIfNotFound) {
812 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
813 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
814 SmallVector<unsigned,4> DeadOps;
815 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
816 MachineOperand &MO = getOperand(i);
817 if (!MO.isRegister() || !MO.isDef())
819 unsigned Reg = MO.getReg();
820 if (Reg == IncomingReg) {
824 if (hasAliases && MO.isDead() &&
825 TargetRegisterInfo::isPhysicalRegister(Reg)) {
826 // There exists a super-register that's marked dead.
827 if (RegInfo->isSuperRegister(IncomingReg, Reg))
829 if (RegInfo->isSubRegister(IncomingReg, Reg))
830 DeadOps.push_back(i);
834 // Trim unneeded dead operands.
835 while (!DeadOps.empty()) {
836 unsigned OpIdx = DeadOps.back();
837 if (getOperand(OpIdx).isImplicit())
838 RemoveOperand(OpIdx);
840 getOperand(OpIdx).setIsDead(false);
844 // If not found, this means an alias of one of the operand is dead. Add a
845 // new implicit operand.
847 addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/,
848 true/*IsImp*/,false/*IsKill*/,