1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 // FIXME: Now that MachineInstrs have parent pointers, they should always
13 // print themselves using their MachineFunction's TargetMachine.
15 //===----------------------------------------------------------------------===//
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Value.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/MRegisterInfo.h"
23 #include "Support/LeakDetector.h"
26 // Global variable holding an array of descriptors for machine instructions.
27 // The actual object needs to be created separately for each target machine.
28 // This variable is initialized and reset by class TargetInstrInfo.
30 // FIXME: This should be a property of the target so that more than one target
31 // at a time can be active...
34 extern const TargetInstrDescriptor *TargetInstrDescriptors;
37 // Constructor for instructions with variable #operands
38 MachineInstr::MachineInstr(short opcode, unsigned numOperands)
41 operands(numOperands, MachineOperand()),
43 // Make sure that we get added to a machine basicblock
44 LeakDetector::addGarbageObject(this);
47 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
48 /// not a resize for them. It is expected that if you use this that you call
49 /// add* methods below to fill up the operands, instead of the Set methods.
50 /// Eventually, the "resizing" ctors will be phased out.
52 MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY)
53 : Opcode(opcode), numImplicitRefs(0), parent(0) {
54 operands.reserve(numOperands);
55 // Make sure that we get added to a machine basicblock
56 LeakDetector::addGarbageObject(this);
59 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
60 /// MachineInstr is created and added to the end of the specified basic block.
62 MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
64 : Opcode(opcode), numImplicitRefs(0), parent(0) {
65 assert(MBB && "Cannot use inserting ctor with null basic block!");
66 operands.reserve(numOperands);
67 // Make sure that we get added to a machine basicblock
68 LeakDetector::addGarbageObject(this);
69 MBB->push_back(this); // Add instruction to end of basic block!
72 MachineInstr::~MachineInstr()
74 LeakDetector::removeGarbageObject(this);
77 /// OperandComplete - Return true if it's illegal to add a new operand
79 bool MachineInstr::OperandsComplete() const {
80 int NumOperands = TargetInstrDescriptors[Opcode].numOperands;
81 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
82 return true; // Broken: we have all the operands of this instruction!
86 /// replace - Support for replacing opcode and operands of a MachineInstr in
87 /// place. This only resets the size of the operand vector and initializes it.
88 /// The new operands must be set explicitly later.
90 void MachineInstr::replace(short opcode, unsigned numOperands) {
91 assert(getNumImplicitRefs() == 0 &&
92 "This is probably broken because implicit refs are going to be lost.");
95 operands.resize(numOperands, MachineOperand());
98 void MachineInstr::SetMachineOperandVal(unsigned i,
99 MachineOperand::MachineOperandType opTy,
101 assert(i < operands.size()); // may be explicit or implicit op
102 operands[i].opType = opTy;
103 operands[i].contents.value = V;
104 operands[i].regNum = -1;
108 MachineInstr::SetMachineOperandConst(unsigned i,
109 MachineOperand::MachineOperandType opTy,
111 assert(i < getNumOperands()); // must be explicit op
112 assert(TargetInstrDescriptors[Opcode].resultPos != (int) i &&
113 "immed. constant cannot be defined");
115 operands[i].opType = opTy;
116 operands[i].contents.value = NULL;
117 operands[i].contents.immedVal = intValue;
118 operands[i].regNum = -1;
119 operands[i].flags = 0;
122 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
123 assert(i < getNumOperands()); // must be explicit op
125 operands[i].opType = MachineOperand::MO_MachineRegister;
126 operands[i].contents.value = NULL;
127 operands[i].regNum = regNum;
130 // Used only by the SPARC back-end.
131 void MachineInstr::SetRegForOperand(unsigned i, int regNum) {
132 assert(i < getNumOperands()); // must be explicit op
133 operands[i].setRegForValue(regNum);
136 // Used only by the SPARC back-end.
137 void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) {
138 getImplicitOp(i).setRegForValue(regNum);
141 /// substituteValue - Substitute all occurrences of Value* oldVal with newVal
142 /// in all operands and all implicit refs. If defsOnly == true, substitute defs
145 /// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865,
146 /// or make it a static function in that file.
149 MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
150 bool defsOnly, bool notDefsAndUses,
151 bool& someArgsWereIgnored)
153 assert((!defsOnly || !notDefsAndUses) &&
154 "notDefsAndUses is irrelevant if defsOnly == true.");
156 unsigned numSubst = 0;
158 // Substitute operands
159 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
162 notDefsAndUses && (O.isDef() && !O.isUse()) ||
163 !notDefsAndUses && O.isDef())
165 O.getMachineOperand().contents.value = newVal;
169 someArgsWereIgnored = true;
171 // Substitute implicit refs
172 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
173 if (getImplicitRef(i) == oldVal)
175 notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
176 !notDefsAndUses && getImplicitOp(i).isDef())
178 getImplicitOp(i).contents.value = newVal;
182 someArgsWereIgnored = true;
187 void MachineInstr::dump() const {
188 std::cerr << " " << *this;
191 static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
193 os << (void*) val; // print address always
194 if (val && val->hasName())
195 os << " " << val->getName(); // print name also, if available
200 static inline void OutputReg(std::ostream &os, unsigned RegNo,
201 const MRegisterInfo *MRI = 0) {
202 if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
204 os << "%" << MRI->get(RegNo).Name;
206 os << "%mreg(" << RegNo << ")";
208 os << "%reg" << RegNo;
211 static void print(const MachineOperand &MO, std::ostream &OS,
212 const TargetMachine &TM) {
213 const MRegisterInfo *MRI = TM.getRegisterInfo();
214 bool CloseParen = true;
217 else if (MO.isLoBits32())
219 else if (MO.isHiBits64())
221 else if (MO.isLoBits64())
226 switch (MO.getType()) {
227 case MachineOperand::MO_VirtualRegister:
228 if (MO.getVRegValue()) {
230 OutputValue(OS, MO.getVRegValue());
231 if (MO.hasAllocatedReg())
234 if (MO.hasAllocatedReg())
235 OutputReg(OS, MO.getReg(), MRI);
237 case MachineOperand::MO_CCRegister:
239 OutputValue(OS, MO.getVRegValue());
240 if (MO.hasAllocatedReg()) {
242 OutputReg(OS, MO.getReg(), MRI);
245 case MachineOperand::MO_MachineRegister:
246 OutputReg(OS, MO.getMachineRegNum(), MRI);
248 case MachineOperand::MO_SignExtendedImmed:
249 OS << (long)MO.getImmedValue();
251 case MachineOperand::MO_UnextendedImmed:
252 OS << (long)MO.getImmedValue();
254 case MachineOperand::MO_PCRelativeDisp: {
255 const Value* opVal = MO.getVRegValue();
256 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
257 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
258 if (opVal->hasName())
259 OS << opVal->getName();
261 OS << (const void*) opVal;
265 case MachineOperand::MO_MachineBasicBlock:
267 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
268 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
270 case MachineOperand::MO_FrameIndex:
271 OS << "<fi#" << MO.getFrameIndex() << ">";
273 case MachineOperand::MO_ConstantPoolIndex:
274 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
276 case MachineOperand::MO_GlobalAddress:
277 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
279 case MachineOperand::MO_ExternalSymbol:
280 OS << "<es:" << MO.getSymbolName() << ">";
283 assert(0 && "Unrecognized operand type");
290 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
291 unsigned StartOp = 0;
293 // Specialize printing if op#0 is definition
294 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
295 ::print(getOperand(0), OS, TM);
297 ++StartOp; // Don't print this operand again!
299 OS << TM.getInstrInfo().getName(getOpcode());
301 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
302 const MachineOperand& mop = getOperand(i);
306 ::print(mop, OS, TM);
315 // code for printing implicit references
316 if (getNumImplicitRefs()) {
317 OS << "\tImplicitRefs: ";
318 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
320 OutputValue(OS, getImplicitRef(i));
321 if (getImplicitOp(i).isDef())
322 if (getImplicitOp(i).isUse())
333 std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
334 // If the instruction is embedded into a basic block, we can find the target
335 // info for the instruction.
336 if (const MachineBasicBlock *MBB = MI.getParent()) {
337 const MachineFunction *MF = MBB->getParent();
338 MI.print(os, MF->getTarget());
342 // Otherwise, print it out in the "raw" format without symbolic register names
344 os << TargetInstrDescriptors[MI.getOpcode()].Name;
346 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
347 os << "\t" << MI.getOperand(i);
348 if (MI.getOperand(i).isDef())
349 if (MI.getOperand(i).isUse())
355 // code for printing implicit references
356 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
357 if (NumOfImpRefs > 0) {
358 os << "\tImplicit: ";
359 for (unsigned z=0; z < NumOfImpRefs; z++) {
360 OutputValue(os, MI.getImplicitRef(z));
361 if (MI.getImplicitOp(z).isDef())
362 if (MI.getImplicitOp(z).isUse())
373 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
376 else if (MO.isLoBits32())
378 else if (MO.isHiBits64())
380 else if (MO.isLoBits64())
383 switch (MO.getType())
385 case MachineOperand::MO_VirtualRegister:
386 if (MO.hasAllocatedReg())
387 OutputReg(OS, MO.getReg());
389 if (MO.getVRegValue()) {
390 if (MO.hasAllocatedReg()) OS << "==";
392 OutputValue(OS, MO.getVRegValue());
395 case MachineOperand::MO_CCRegister:
397 OutputValue(OS, MO.getVRegValue());
398 if (MO.hasAllocatedReg()) {
400 OutputReg(OS, MO.getReg());
403 case MachineOperand::MO_MachineRegister:
404 OutputReg(OS, MO.getMachineRegNum());
406 case MachineOperand::MO_SignExtendedImmed:
407 OS << (long)MO.getImmedValue();
409 case MachineOperand::MO_UnextendedImmed:
410 OS << (long)MO.getImmedValue();
412 case MachineOperand::MO_PCRelativeDisp:
414 const Value* opVal = MO.getVRegValue();
415 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
416 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
417 if (opVal->hasName())
418 OS << opVal->getName();
420 OS << (const void*) opVal;
424 case MachineOperand::MO_MachineBasicBlock:
426 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
427 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
429 case MachineOperand::MO_FrameIndex:
430 OS << "<fi#" << MO.getFrameIndex() << ">";
432 case MachineOperand::MO_ConstantPoolIndex:
433 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
435 case MachineOperand::MO_GlobalAddress:
436 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
438 case MachineOperand::MO_ExternalSymbol:
439 OS << "<es:" << MO.getSymbolName() << ">";
442 assert(0 && "Unrecognized operand type");
446 if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())