1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Function.h"
17 #include "llvm/InlineAsm.h"
18 #include "llvm/Metadata.h"
19 #include "llvm/Type.h"
20 #include "llvm/Value.h"
21 #include "llvm/Assembly/Writer.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetInstrDesc.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/Analysis/AliasAnalysis.h"
33 #include "llvm/Analysis/DebugInfo.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/LeakDetector.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/ADT/FoldingSet.h"
42 //===----------------------------------------------------------------------===//
43 // MachineOperand Implementation
44 //===----------------------------------------------------------------------===//
46 /// AddRegOperandToRegInfo - Add this register operand to the specified
47 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
48 /// explicitly nulled out.
49 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
50 assert(isReg() && "Can only add reg operand to use lists");
52 // If the reginfo pointer is null, just explicitly null out or next/prev
53 // pointers, to ensure they are not garbage.
55 Contents.Reg.Prev = 0;
56 Contents.Reg.Next = 0;
60 // Otherwise, add this operand to the head of the registers use/def list.
61 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
63 // For SSA values, we prefer to keep the definition at the start of the list.
64 // we do this by skipping over the definition if it is at the head of the
66 if (*Head && (*Head)->isDef())
67 Head = &(*Head)->Contents.Reg.Next;
69 Contents.Reg.Next = *Head;
70 if (Contents.Reg.Next) {
71 assert(getReg() == Contents.Reg.Next->getReg() &&
72 "Different regs on the same list!");
73 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
76 Contents.Reg.Prev = Head;
80 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
81 /// MachineRegisterInfo it is linked with.
82 void MachineOperand::RemoveRegOperandFromRegInfo() {
83 assert(isOnRegUseList() && "Reg operand is not on a use list");
84 // Unlink this from the doubly linked list of operands.
85 MachineOperand *NextOp = Contents.Reg.Next;
86 *Contents.Reg.Prev = NextOp;
88 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
89 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
91 Contents.Reg.Prev = 0;
92 Contents.Reg.Next = 0;
95 void MachineOperand::setReg(unsigned Reg) {
96 if (getReg() == Reg) return; // No change.
98 // Otherwise, we have to change the register. If this operand is embedded
99 // into a machine function, we need to update the old and new register's
101 if (MachineInstr *MI = getParent())
102 if (MachineBasicBlock *MBB = MI->getParent())
103 if (MachineFunction *MF = MBB->getParent()) {
104 RemoveRegOperandFromRegInfo();
105 Contents.Reg.RegNo = Reg;
106 AddRegOperandToRegInfo(&MF->getRegInfo());
110 // Otherwise, just change the register, no problem. :)
111 Contents.Reg.RegNo = Reg;
114 /// ChangeToImmediate - Replace this operand with a new immediate operand of
115 /// the specified value. If an operand is known to be an immediate already,
116 /// the setImm method should be used.
117 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
118 // If this operand is currently a register operand, and if this is in a
119 // function, deregister the operand from the register's use/def list.
120 if (isReg() && getParent() && getParent()->getParent() &&
121 getParent()->getParent()->getParent())
122 RemoveRegOperandFromRegInfo();
124 OpKind = MO_Immediate;
125 Contents.ImmVal = ImmVal;
128 /// ChangeToRegister - Replace this operand with a new register operand of
129 /// the specified value. If an operand is known to be an register already,
130 /// the setReg method should be used.
131 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
132 bool isKill, bool isDead, bool isUndef,
134 // If this operand is already a register operand, use setReg to update the
135 // register's use/def lists.
137 assert(!isEarlyClobber());
140 // Otherwise, change this to a register and set the reg#.
141 OpKind = MO_Register;
142 Contents.Reg.RegNo = Reg;
144 // If this operand is embedded in a function, add the operand to the
145 // register's use/def list.
146 if (MachineInstr *MI = getParent())
147 if (MachineBasicBlock *MBB = MI->getParent())
148 if (MachineFunction *MF = MBB->getParent())
149 AddRegOperandToRegInfo(&MF->getRegInfo());
157 IsEarlyClobber = false;
162 /// isIdenticalTo - Return true if this operand is identical to the specified
164 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
165 if (getType() != Other.getType() ||
166 getTargetFlags() != Other.getTargetFlags())
170 default: llvm_unreachable("Unrecognized operand type");
171 case MachineOperand::MO_Register:
172 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
173 getSubReg() == Other.getSubReg();
174 case MachineOperand::MO_Immediate:
175 return getImm() == Other.getImm();
176 case MachineOperand::MO_FPImmediate:
177 return getFPImm() == Other.getFPImm();
178 case MachineOperand::MO_MachineBasicBlock:
179 return getMBB() == Other.getMBB();
180 case MachineOperand::MO_FrameIndex:
181 return getIndex() == Other.getIndex();
182 case MachineOperand::MO_ConstantPoolIndex:
183 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
184 case MachineOperand::MO_JumpTableIndex:
185 return getIndex() == Other.getIndex();
186 case MachineOperand::MO_GlobalAddress:
187 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
188 case MachineOperand::MO_ExternalSymbol:
189 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
190 getOffset() == Other.getOffset();
191 case MachineOperand::MO_BlockAddress:
192 return getBlockAddress() == Other.getBlockAddress();
193 case MachineOperand::MO_MCSymbol:
194 return getMCSymbol() == Other.getMCSymbol();
198 /// print - Print the specified machine operand.
200 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
201 // If the instruction is embedded into a basic block, we can find the
202 // target info for the instruction.
204 if (const MachineInstr *MI = getParent())
205 if (const MachineBasicBlock *MBB = MI->getParent())
206 if (const MachineFunction *MF = MBB->getParent())
207 TM = &MF->getTarget();
210 case MachineOperand::MO_Register:
211 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
212 OS << "%reg" << getReg();
215 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
217 OS << "%physreg" << getReg();
220 if (getSubReg() != 0)
221 OS << ':' << getSubReg();
223 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
226 bool NeedComma = false;
228 if (NeedComma) OS << ',';
229 if (isEarlyClobber())
230 OS << "earlyclobber,";
235 } else if (isImplicit()) {
240 if (isKill() || isDead() || isUndef()) {
241 if (NeedComma) OS << ',';
242 if (isKill()) OS << "kill";
243 if (isDead()) OS << "dead";
245 if (isKill() || isDead())
253 case MachineOperand::MO_Immediate:
256 case MachineOperand::MO_FPImmediate:
257 if (getFPImm()->getType()->isFloatTy())
258 OS << getFPImm()->getValueAPF().convertToFloat();
260 OS << getFPImm()->getValueAPF().convertToDouble();
262 case MachineOperand::MO_MachineBasicBlock:
263 OS << "<BB#" << getMBB()->getNumber() << ">";
265 case MachineOperand::MO_FrameIndex:
266 OS << "<fi#" << getIndex() << '>';
268 case MachineOperand::MO_ConstantPoolIndex:
269 OS << "<cp#" << getIndex();
270 if (getOffset()) OS << "+" << getOffset();
273 case MachineOperand::MO_JumpTableIndex:
274 OS << "<jt#" << getIndex() << '>';
276 case MachineOperand::MO_GlobalAddress:
278 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
279 if (getOffset()) OS << "+" << getOffset();
282 case MachineOperand::MO_ExternalSymbol:
283 OS << "<es:" << getSymbolName();
284 if (getOffset()) OS << "+" << getOffset();
287 case MachineOperand::MO_BlockAddress:
289 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
292 case MachineOperand::MO_Metadata:
294 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
297 case MachineOperand::MO_MCSymbol:
298 OS << "<MCSym=" << *getMCSymbol() << '>';
301 llvm_unreachable("Unrecognized operand type");
304 if (unsigned TF = getTargetFlags())
305 OS << "[TF=" << TF << ']';
308 //===----------------------------------------------------------------------===//
309 // MachineMemOperand Implementation
310 //===----------------------------------------------------------------------===//
312 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
313 int64_t o, uint64_t s, unsigned int a)
314 : Offset(o), Size(s), V(v),
315 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)) {
316 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
317 assert((isLoad() || isStore()) && "Not a load/store!");
320 /// Profile - Gather unique data for the object.
322 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
323 ID.AddInteger(Offset);
326 ID.AddInteger(Flags);
329 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
330 // The Value and Offset may differ due to CSE. But the flags and size
331 // should be the same.
332 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
333 assert(MMO->getSize() == getSize() && "Size mismatch!");
335 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
336 // Update the alignment value.
337 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
338 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
339 // Also update the base and offset, because the new alignment may
340 // not be applicable with the old ones.
342 Offset = MMO->getOffset();
346 /// getAlignment - Return the minimum known alignment in bytes of the
347 /// actual memory reference.
348 uint64_t MachineMemOperand::getAlignment() const {
349 return MinAlign(getBaseAlignment(), getOffset());
352 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
353 assert((MMO.isLoad() || MMO.isStore()) &&
354 "SV has to be a load, store or both.");
356 if (MMO.isVolatile())
365 // Print the address information.
370 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
372 // If the alignment of the memory reference itself differs from the alignment
373 // of the base pointer, print the base alignment explicitly, next to the base
375 if (MMO.getBaseAlignment() != MMO.getAlignment())
376 OS << "(align=" << MMO.getBaseAlignment() << ")";
378 if (MMO.getOffset() != 0)
379 OS << "+" << MMO.getOffset();
382 // Print the alignment of the reference.
383 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
384 MMO.getBaseAlignment() != MMO.getSize())
385 OS << "(align=" << MMO.getAlignment() << ")";
390 //===----------------------------------------------------------------------===//
391 // MachineInstr Implementation
392 //===----------------------------------------------------------------------===//
394 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
395 /// TID NULL and no operands.
396 MachineInstr::MachineInstr()
397 : TID(0), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
399 // Make sure that we get added to a machine basicblock
400 LeakDetector::addGarbageObject(this);
403 void MachineInstr::addImplicitDefUseOperands() {
404 if (TID->ImplicitDefs)
405 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
406 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
407 if (TID->ImplicitUses)
408 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
409 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
412 /// MachineInstr ctor - This constructor create a MachineInstr and add the
413 /// implicit operands. It reserves space for number of operands specified by
414 /// TargetInstrDesc or the numOperands if it is not zero. (for
415 /// instructions with variable number of operands).
416 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
417 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
418 MemRefs(0), MemRefsEnd(0), Parent(0) {
419 if (!NoImp && TID->getImplicitDefs())
420 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
422 if (!NoImp && TID->getImplicitUses())
423 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
425 Operands.reserve(NumImplicitOps + TID->getNumOperands());
427 addImplicitDefUseOperands();
428 // Make sure that we get added to a machine basicblock
429 LeakDetector::addGarbageObject(this);
432 /// MachineInstr ctor - As above, but with a DebugLoc.
433 MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
435 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
436 Parent(0), debugLoc(dl) {
437 if (!NoImp && TID->getImplicitDefs())
438 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
440 if (!NoImp && TID->getImplicitUses())
441 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
443 Operands.reserve(NumImplicitOps + TID->getNumOperands());
445 addImplicitDefUseOperands();
446 // Make sure that we get added to a machine basicblock
447 LeakDetector::addGarbageObject(this);
450 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
451 /// that the MachineInstr is created and added to the end of the specified
454 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
455 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
456 MemRefs(0), MemRefsEnd(0), Parent(0) {
457 assert(MBB && "Cannot use inserting ctor with null basic block!");
458 if (TID->ImplicitDefs)
459 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
461 if (TID->ImplicitUses)
462 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
464 Operands.reserve(NumImplicitOps + TID->getNumOperands());
465 addImplicitDefUseOperands();
466 // Make sure that we get added to a machine basicblock
467 LeakDetector::addGarbageObject(this);
468 MBB->push_back(this); // Add instruction to end of basic block!
471 /// MachineInstr ctor - As above, but with a DebugLoc.
473 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
474 const TargetInstrDesc &tid)
475 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
476 Parent(0), debugLoc(dl) {
477 assert(MBB && "Cannot use inserting ctor with null basic block!");
478 if (TID->ImplicitDefs)
479 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
481 if (TID->ImplicitUses)
482 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
484 Operands.reserve(NumImplicitOps + TID->getNumOperands());
485 addImplicitDefUseOperands();
486 // Make sure that we get added to a machine basicblock
487 LeakDetector::addGarbageObject(this);
488 MBB->push_back(this); // Add instruction to end of basic block!
491 /// MachineInstr ctor - Copies MachineInstr arg exactly
493 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
494 : TID(&MI.getDesc()), NumImplicitOps(0), AsmPrinterFlags(0),
495 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
496 Parent(0), debugLoc(MI.getDebugLoc()) {
497 Operands.reserve(MI.getNumOperands());
500 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
501 addOperand(MI.getOperand(i));
502 NumImplicitOps = MI.NumImplicitOps;
504 // Set parent to null.
507 LeakDetector::addGarbageObject(this);
510 MachineInstr::~MachineInstr() {
511 LeakDetector::removeGarbageObject(this);
513 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
514 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
515 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
516 "Reg operand def/use list corrupted");
521 /// getRegInfo - If this instruction is embedded into a MachineFunction,
522 /// return the MachineRegisterInfo object for the current function, otherwise
524 MachineRegisterInfo *MachineInstr::getRegInfo() {
525 if (MachineBasicBlock *MBB = getParent())
526 return &MBB->getParent()->getRegInfo();
530 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
531 /// this instruction from their respective use lists. This requires that the
532 /// operands already be on their use lists.
533 void MachineInstr::RemoveRegOperandsFromUseLists() {
534 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
535 if (Operands[i].isReg())
536 Operands[i].RemoveRegOperandFromRegInfo();
540 /// AddRegOperandsToUseLists - Add all of the register operands in
541 /// this instruction from their respective use lists. This requires that the
542 /// operands not be on their use lists yet.
543 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
544 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
545 if (Operands[i].isReg())
546 Operands[i].AddRegOperandToRegInfo(&RegInfo);
551 /// addOperand - Add the specified operand to the instruction. If it is an
552 /// implicit operand, it is added to the end of the operand list. If it is
553 /// an explicit operand it is added at the end of the explicit operand list
554 /// (before the first implicit operand).
555 void MachineInstr::addOperand(const MachineOperand &Op) {
556 bool isImpReg = Op.isReg() && Op.isImplicit();
557 assert((isImpReg || !OperandsComplete()) &&
558 "Trying to add an operand to a machine instr that is already done!");
560 MachineRegisterInfo *RegInfo = getRegInfo();
562 // If we are adding the operand to the end of the list, our job is simpler.
563 // This is true most of the time, so this is a reasonable optimization.
564 if (isImpReg || NumImplicitOps == 0) {
565 // We can only do this optimization if we know that the operand list won't
567 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
568 Operands.push_back(Op);
570 // Set the parent of the operand.
571 Operands.back().ParentMI = this;
573 // If the operand is a register, update the operand's use list.
575 Operands.back().AddRegOperandToRegInfo(RegInfo);
576 // If the register operand is flagged as early, mark the operand as such
577 unsigned OpNo = Operands.size() - 1;
578 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
579 Operands[OpNo].setIsEarlyClobber(true);
585 // Otherwise, we have to insert a real operand before any implicit ones.
586 unsigned OpNo = Operands.size()-NumImplicitOps;
588 // If this instruction isn't embedded into a function, then we don't need to
589 // update any operand lists.
591 // Simple insertion, no reginfo update needed for other register operands.
592 Operands.insert(Operands.begin()+OpNo, Op);
593 Operands[OpNo].ParentMI = this;
595 // Do explicitly set the reginfo for this operand though, to ensure the
596 // next/prev fields are properly nulled out.
597 if (Operands[OpNo].isReg()) {
598 Operands[OpNo].AddRegOperandToRegInfo(0);
599 // If the register operand is flagged as early, mark the operand as such
600 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
601 Operands[OpNo].setIsEarlyClobber(true);
604 } else if (Operands.size()+1 <= Operands.capacity()) {
605 // Otherwise, we have to remove register operands from their register use
606 // list, add the operand, then add the register operands back to their use
607 // list. This also must handle the case when the operand list reallocates
608 // to somewhere else.
610 // If insertion of this operand won't cause reallocation of the operand
611 // list, just remove the implicit operands, add the operand, then re-add all
612 // the rest of the operands.
613 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
614 assert(Operands[i].isReg() && "Should only be an implicit reg!");
615 Operands[i].RemoveRegOperandFromRegInfo();
618 // Add the operand. If it is a register, add it to the reg list.
619 Operands.insert(Operands.begin()+OpNo, Op);
620 Operands[OpNo].ParentMI = this;
622 if (Operands[OpNo].isReg()) {
623 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
624 // If the register operand is flagged as early, mark the operand as such
625 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
626 Operands[OpNo].setIsEarlyClobber(true);
629 // Re-add all the implicit ops.
630 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
631 assert(Operands[i].isReg() && "Should only be an implicit reg!");
632 Operands[i].AddRegOperandToRegInfo(RegInfo);
635 // Otherwise, we will be reallocating the operand list. Remove all reg
636 // operands from their list, then readd them after the operand list is
638 RemoveRegOperandsFromUseLists();
640 Operands.insert(Operands.begin()+OpNo, Op);
641 Operands[OpNo].ParentMI = this;
643 // Re-add all the operands.
644 AddRegOperandsToUseLists(*RegInfo);
646 // If the register operand is flagged as early, mark the operand as such
647 if (Operands[OpNo].isReg()
648 && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
649 Operands[OpNo].setIsEarlyClobber(true);
653 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
654 /// fewer operand than it started with.
656 void MachineInstr::RemoveOperand(unsigned OpNo) {
657 assert(OpNo < Operands.size() && "Invalid operand number");
659 // Special case removing the last one.
660 if (OpNo == Operands.size()-1) {
661 // If needed, remove from the reg def/use list.
662 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
663 Operands.back().RemoveRegOperandFromRegInfo();
669 // Otherwise, we are removing an interior operand. If we have reginfo to
670 // update, remove all operands that will be shifted down from their reg lists,
671 // move everything down, then re-add them.
672 MachineRegisterInfo *RegInfo = getRegInfo();
674 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
675 if (Operands[i].isReg())
676 Operands[i].RemoveRegOperandFromRegInfo();
680 Operands.erase(Operands.begin()+OpNo);
683 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
684 if (Operands[i].isReg())
685 Operands[i].AddRegOperandToRegInfo(RegInfo);
690 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
691 /// This function should be used only occasionally. The setMemRefs function
692 /// is the primary method for setting up a MachineInstr's MemRefs list.
693 void MachineInstr::addMemOperand(MachineFunction &MF,
694 MachineMemOperand *MO) {
695 mmo_iterator OldMemRefs = MemRefs;
696 mmo_iterator OldMemRefsEnd = MemRefsEnd;
698 size_t NewNum = (MemRefsEnd - MemRefs) + 1;
699 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
700 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
702 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
703 NewMemRefs[NewNum - 1] = MO;
705 MemRefs = NewMemRefs;
706 MemRefsEnd = NewMemRefsEnd;
709 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
710 MICheckType Check) const {
711 // If opcodes or number of operands are not the same then the two
712 // instructions are obviously not identical.
713 if (Other->getOpcode() != getOpcode() ||
714 Other->getNumOperands() != getNumOperands())
717 // Check operands to make sure they match.
718 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
719 const MachineOperand &MO = getOperand(i);
720 const MachineOperand &OMO = Other->getOperand(i);
721 // Clients may or may not want to ignore defs when testing for equality.
722 // For example, machine CSE pass only cares about finding common
723 // subexpressions, so it's safe to ignore virtual register defs.
724 if (Check != CheckDefs && MO.isReg() && MO.isDef()) {
725 if (Check == IgnoreDefs)
727 // Check == IgnoreVRegDefs
728 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
729 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
730 if (MO.getReg() != OMO.getReg())
732 } else if (!MO.isIdenticalTo(OMO))
738 /// removeFromParent - This method unlinks 'this' from the containing basic
739 /// block, and returns it, but does not delete it.
740 MachineInstr *MachineInstr::removeFromParent() {
741 assert(getParent() && "Not embedded in a basic block!");
742 getParent()->remove(this);
747 /// eraseFromParent - This method unlinks 'this' from the containing basic
748 /// block, and deletes it.
749 void MachineInstr::eraseFromParent() {
750 assert(getParent() && "Not embedded in a basic block!");
751 getParent()->erase(this);
755 /// OperandComplete - Return true if it's illegal to add a new operand
757 bool MachineInstr::OperandsComplete() const {
758 unsigned short NumOperands = TID->getNumOperands();
759 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
760 return true; // Broken: we have all the operands of this instruction!
764 /// getNumExplicitOperands - Returns the number of non-implicit operands.
766 unsigned MachineInstr::getNumExplicitOperands() const {
767 unsigned NumOperands = TID->getNumOperands();
768 if (!TID->isVariadic())
771 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
772 const MachineOperand &MO = getOperand(i);
773 if (!MO.isReg() || !MO.isImplicit())
780 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
781 /// the specific register or -1 if it is not found. It further tightens
782 /// the search criteria to a use that kills the register if isKill is true.
783 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
784 const TargetRegisterInfo *TRI) const {
785 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
786 const MachineOperand &MO = getOperand(i);
787 if (!MO.isReg() || !MO.isUse())
789 unsigned MOReg = MO.getReg();
794 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
795 TargetRegisterInfo::isPhysicalRegister(Reg) &&
796 TRI->isSubRegister(MOReg, Reg)))
797 if (!isKill || MO.isKill())
803 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
804 /// the specified register or -1 if it is not found. If isDead is true, defs
805 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
806 /// also checks if there is a def of a super-register.
807 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
808 const TargetRegisterInfo *TRI) const {
809 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
810 const MachineOperand &MO = getOperand(i);
811 if (!MO.isReg() || !MO.isDef())
813 unsigned MOReg = MO.getReg();
816 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
817 TargetRegisterInfo::isPhysicalRegister(Reg) &&
818 TRI->isSubRegister(MOReg, Reg)))
819 if (!isDead || MO.isDead())
825 /// findFirstPredOperandIdx() - Find the index of the first operand in the
826 /// operand list that is used to represent the predicate. It returns -1 if
828 int MachineInstr::findFirstPredOperandIdx() const {
829 const TargetInstrDesc &TID = getDesc();
830 if (TID.isPredicable()) {
831 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
832 if (TID.OpInfo[i].isPredicate())
839 /// isRegTiedToUseOperand - Given the index of a register def operand,
840 /// check if the register def is tied to a source operand, due to either
841 /// two-address elimination or inline assembly constraints. Returns the
842 /// first tied use operand index by reference is UseOpIdx is not null.
844 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
846 assert(DefOpIdx >= 2);
847 const MachineOperand &MO = getOperand(DefOpIdx);
848 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
850 // Determine the actual operand index that corresponds to this index.
852 unsigned DefPart = 0;
853 for (unsigned i = 1, e = getNumOperands(); i < e; ) {
854 const MachineOperand &FMO = getOperand(i);
855 // After the normal asm operands there may be additional imp-def regs.
858 // Skip over this def.
859 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
860 unsigned PrevDef = i + 1;
861 i = PrevDef + NumOps;
863 DefPart = DefOpIdx - PrevDef;
868 for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
869 const MachineOperand &FMO = getOperand(i);
872 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
875 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
878 *UseOpIdx = (unsigned)i + 1 + DefPart;
885 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
886 const TargetInstrDesc &TID = getDesc();
887 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
888 const MachineOperand &MO = getOperand(i);
889 if (MO.isReg() && MO.isUse() &&
890 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
892 *UseOpIdx = (unsigned)i;
899 /// isRegTiedToDefOperand - Return true if the operand of the specified index
900 /// is a register use and it is tied to an def operand. It also returns the def
901 /// operand index by reference.
903 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
905 const MachineOperand &MO = getOperand(UseOpIdx);
906 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
909 // Find the flag operand corresponding to UseOpIdx
910 unsigned FlagIdx, NumOps=0;
911 for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
912 const MachineOperand &UFMO = getOperand(FlagIdx);
913 // After the normal asm operands there may be additional imp-def regs.
916 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
917 assert(NumOps < getNumOperands() && "Invalid inline asm flag");
918 if (UseOpIdx < FlagIdx+NumOps+1)
921 if (FlagIdx >= UseOpIdx)
923 const MachineOperand &UFMO = getOperand(FlagIdx);
925 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
930 // Remember to adjust the index. First operand is asm string, then there
931 // is a flag for each.
933 const MachineOperand &FMO = getOperand(DefIdx);
935 // Skip over this def.
936 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
939 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
945 const TargetInstrDesc &TID = getDesc();
946 if (UseOpIdx >= TID.getNumOperands())
948 const MachineOperand &MO = getOperand(UseOpIdx);
949 if (!MO.isReg() || !MO.isUse())
951 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
955 *DefOpIdx = (unsigned)DefIdx;
959 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
961 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
962 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
963 const MachineOperand &MO = MI->getOperand(i);
964 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
966 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
967 MachineOperand &MOp = getOperand(j);
968 if (!MOp.isIdenticalTo(MO))
979 /// copyPredicates - Copies predicate operand(s) from MI.
980 void MachineInstr::copyPredicates(const MachineInstr *MI) {
981 const TargetInstrDesc &TID = MI->getDesc();
982 if (!TID.isPredicable())
984 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
985 if (TID.OpInfo[i].isPredicate()) {
986 // Predicated operands must be last operands.
987 addOperand(MI->getOperand(i));
992 /// isSafeToMove - Return true if it is safe to move this instruction. If
993 /// SawStore is set to true, it means that there is a store (or call) between
994 /// the instruction's location and its intended destination.
995 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
997 bool &SawStore) const {
998 // Ignore stuff that we obviously can't move.
999 if (TID->mayStore() || TID->isCall()) {
1003 if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
1006 // See if this instruction does a load. If so, we have to guarantee that the
1007 // loaded value doesn't change between the load and the its intended
1008 // destination. The check for isInvariantLoad gives the targe the chance to
1009 // classify the load as always returning a constant, e.g. a constant pool
1011 if (TID->mayLoad() && !isInvariantLoad(AA))
1012 // Otherwise, this is a real load. If there is a store between the load and
1013 // end of block, or if the load is volatile, we can't move it.
1014 return !SawStore && !hasVolatileMemoryRef();
1019 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1020 /// instruction which defined the specified register instead of copying it.
1021 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1023 unsigned DstReg) const {
1024 bool SawStore = false;
1025 if (!TII->isTriviallyReMaterializable(this, AA) ||
1026 !isSafeToMove(TII, AA, SawStore))
1028 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1029 const MachineOperand &MO = getOperand(i);
1032 // FIXME: For now, do not remat any instruction with register operands.
1033 // Later on, we can loosen the restriction is the register operands have
1034 // not been modified between the def and use. Note, this is different from
1035 // MachineSink because the code is no longer in two-address form (at least
1039 else if (!MO.isDead() && MO.getReg() != DstReg)
1045 /// hasVolatileMemoryRef - Return true if this instruction may have a
1046 /// volatile memory reference, or if the information describing the
1047 /// memory reference is not available. Return false if it is known to
1048 /// have no volatile memory references.
1049 bool MachineInstr::hasVolatileMemoryRef() const {
1050 // An instruction known never to access memory won't have a volatile access.
1051 if (!TID->mayStore() &&
1054 !TID->hasUnmodeledSideEffects())
1057 // Otherwise, if the instruction has no memory reference information,
1058 // conservatively assume it wasn't preserved.
1059 if (memoperands_empty())
1062 // Check the memory reference information for volatile references.
1063 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1064 if ((*I)->isVolatile())
1070 /// isInvariantLoad - Return true if this instruction is loading from a
1071 /// location whose value is invariant across the function. For example,
1072 /// loading a value from the constant pool or from the argument area
1073 /// of a function if it does not change. This should only return true of
1074 /// *all* loads the instruction does are invariant (if it does multiple loads).
1075 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1076 // If the instruction doesn't load at all, it isn't an invariant load.
1077 if (!TID->mayLoad())
1080 // If the instruction has lost its memoperands, conservatively assume that
1081 // it may not be an invariant load.
1082 if (memoperands_empty())
1085 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1087 for (mmo_iterator I = memoperands_begin(),
1088 E = memoperands_end(); I != E; ++I) {
1089 if ((*I)->isVolatile()) return false;
1090 if ((*I)->isStore()) return false;
1092 if (const Value *V = (*I)->getValue()) {
1093 // A load from a constant PseudoSourceValue is invariant.
1094 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1095 if (PSV->isConstant(MFI))
1097 // If we have an AliasAnalysis, ask it whether the memory is constant.
1098 if (AA && AA->pointsToConstantMemory(V))
1102 // Otherwise assume conservatively.
1106 // Everything checks out.
1110 /// isConstantValuePHI - If the specified instruction is a PHI that always
1111 /// merges together the same virtual register, return the register, otherwise
1113 unsigned MachineInstr::isConstantValuePHI() const {
1116 assert(getNumOperands() >= 3 &&
1117 "It's illegal to have a PHI without source operands");
1119 unsigned Reg = getOperand(1).getReg();
1120 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1121 if (getOperand(i).getReg() != Reg)
1126 void MachineInstr::dump() const {
1127 dbgs() << " " << *this;
1130 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1131 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1132 const MachineFunction *MF = 0;
1133 if (const MachineBasicBlock *MBB = getParent()) {
1134 MF = MBB->getParent();
1136 TM = &MF->getTarget();
1139 // Print explicitly defined operands on the left of an assignment syntax.
1140 unsigned StartOp = 0, e = getNumOperands();
1141 for (; StartOp < e && getOperand(StartOp).isReg() &&
1142 getOperand(StartOp).isDef() &&
1143 !getOperand(StartOp).isImplicit();
1145 if (StartOp != 0) OS << ", ";
1146 getOperand(StartOp).print(OS, TM);
1152 // Print the opcode name.
1153 OS << getDesc().getName();
1155 // Print the rest of the operands.
1156 bool OmittedAnyCallClobbers = false;
1157 bool FirstOp = true;
1158 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1159 const MachineOperand &MO = getOperand(i);
1161 // Omit call-clobbered registers which aren't used anywhere. This makes
1162 // call instructions much less noisy on targets where calls clobber lots
1163 // of registers. Don't rely on MO.isDead() because we may be called before
1164 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1165 if (MF && getDesc().isCall() &&
1166 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1167 unsigned Reg = MO.getReg();
1168 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
1169 const MachineRegisterInfo &MRI = MF->getRegInfo();
1170 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1171 bool HasAliasLive = false;
1172 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1173 unsigned AliasReg = *Alias; ++Alias)
1174 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1175 HasAliasLive = true;
1178 if (!HasAliasLive) {
1179 OmittedAnyCallClobbers = true;
1186 if (FirstOp) FirstOp = false; else OS << ",";
1188 if (i < getDesc().NumOperands) {
1189 const TargetOperandInfo &TOI = getDesc().OpInfo[i];
1190 if (TOI.isPredicate())
1192 if (TOI.isOptionalDef())
1198 // Briefly indicate whether any call clobbers were omitted.
1199 if (OmittedAnyCallClobbers) {
1200 if (!FirstOp) OS << ",";
1204 bool HaveSemi = false;
1205 if (!memoperands_empty()) {
1206 if (!HaveSemi) OS << ";"; HaveSemi = true;
1209 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1217 if (!debugLoc.isUnknown() && MF) {
1218 if (!HaveSemi) OS << ";";
1220 // TODO: print InlinedAtLoc information
1222 DIScope Scope(debugLoc.getScope(MF->getFunction()->getContext()));
1224 // Omit the directory, since it's usually long and uninteresting.
1226 OS << Scope.getFilename();
1229 OS << ':' << debugLoc.getLine();
1230 if (debugLoc.getCol() != 0)
1231 OS << ':' << debugLoc.getCol();
1237 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1238 const TargetRegisterInfo *RegInfo,
1239 bool AddIfNotFound) {
1240 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1241 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1243 SmallVector<unsigned,4> DeadOps;
1244 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1245 MachineOperand &MO = getOperand(i);
1246 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1248 unsigned Reg = MO.getReg();
1252 if (Reg == IncomingReg) {
1255 // The register is already marked kill.
1257 if (isPhysReg && isRegTiedToDefOperand(i))
1258 // Two-address uses of physregs must not be marked kill.
1263 } else if (hasAliases && MO.isKill() &&
1264 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1265 // A super-register kill already exists.
1266 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1268 if (RegInfo->isSubRegister(IncomingReg, Reg))
1269 DeadOps.push_back(i);
1273 // Trim unneeded kill operands.
1274 while (!DeadOps.empty()) {
1275 unsigned OpIdx = DeadOps.back();
1276 if (getOperand(OpIdx).isImplicit())
1277 RemoveOperand(OpIdx);
1279 getOperand(OpIdx).setIsKill(false);
1283 // If not found, this means an alias of one of the operands is killed. Add a
1284 // new implicit operand if required.
1285 if (!Found && AddIfNotFound) {
1286 addOperand(MachineOperand::CreateReg(IncomingReg,
1295 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1296 const TargetRegisterInfo *RegInfo,
1297 bool AddIfNotFound) {
1298 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1299 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1301 SmallVector<unsigned,4> DeadOps;
1302 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1303 MachineOperand &MO = getOperand(i);
1304 if (!MO.isReg() || !MO.isDef())
1306 unsigned Reg = MO.getReg();
1310 if (Reg == IncomingReg) {
1313 // The register is already marked dead.
1318 } else if (hasAliases && MO.isDead() &&
1319 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1320 // There exists a super-register that's marked dead.
1321 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1323 if (RegInfo->getSubRegisters(IncomingReg) &&
1324 RegInfo->getSuperRegisters(Reg) &&
1325 RegInfo->isSubRegister(IncomingReg, Reg))
1326 DeadOps.push_back(i);
1330 // Trim unneeded dead operands.
1331 while (!DeadOps.empty()) {
1332 unsigned OpIdx = DeadOps.back();
1333 if (getOperand(OpIdx).isImplicit())
1334 RemoveOperand(OpIdx);
1336 getOperand(OpIdx).setIsDead(false);
1340 // If not found, this means an alias of one of the operands is dead. Add a
1341 // new implicit operand if required.
1342 if (Found || !AddIfNotFound)
1345 addOperand(MachineOperand::CreateReg(IncomingReg,
1353 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1354 const TargetRegisterInfo *RegInfo) {
1355 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1356 if (!MO || MO->getSubReg())
1357 addOperand(MachineOperand::CreateReg(IncomingReg,
1363 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1364 unsigned Hash = MI->getOpcode() * 37;
1365 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1366 const MachineOperand &MO = MI->getOperand(i);
1367 uint64_t Key = (uint64_t)MO.getType() << 32;
1368 switch (MO.getType()) {
1370 case MachineOperand::MO_Register:
1371 if (MO.isDef() && MO.getReg() &&
1372 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1373 continue; // Skip virtual register defs.
1376 case MachineOperand::MO_Immediate:
1379 case MachineOperand::MO_FrameIndex:
1380 case MachineOperand::MO_ConstantPoolIndex:
1381 case MachineOperand::MO_JumpTableIndex:
1382 Key |= MO.getIndex();
1384 case MachineOperand::MO_MachineBasicBlock:
1385 Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1387 case MachineOperand::MO_GlobalAddress:
1388 Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1390 case MachineOperand::MO_BlockAddress:
1391 Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1393 case MachineOperand::MO_MCSymbol:
1394 Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1397 Key += ~(Key << 32);
1399 Key += ~(Key << 13);
1403 Key += ~(Key << 27);
1405 Hash = (unsigned)Key + Hash * 37;