1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 // FIXME: Now that MachineInstrs have parent pointers, they should always
13 // print themselves using their MachineFunction's TargetMachine.
15 //===----------------------------------------------------------------------===//
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Value.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/MRegisterInfo.h"
23 #include "Support/LeakDetector.h"
26 // Global variable holding an array of descriptors for machine instructions.
27 // The actual object needs to be created separately for each target machine.
28 // This variable is initialized and reset by class TargetInstrInfo.
30 // FIXME: This should be a property of the target so that more than one target
31 // at a time can be active...
34 extern const TargetInstrDescriptor *TargetInstrDescriptors;
37 // Constructor for instructions with variable #operands
38 MachineInstr::MachineInstr(short opcode, unsigned numOperands)
41 operands(numOperands, MachineOperand()),
43 // Make sure that we get added to a machine basicblock
44 LeakDetector::addGarbageObject(this);
47 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
48 /// not a resize for them. It is expected that if you use this that you call
49 /// add* methods below to fill up the operands, instead of the Set methods.
50 /// Eventually, the "resizing" ctors will be phased out.
52 MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY)
53 : Opcode(opcode), numImplicitRefs(0), parent(0) {
54 operands.reserve(numOperands);
55 // Make sure that we get added to a machine basicblock
56 LeakDetector::addGarbageObject(this);
59 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
60 /// MachineInstr is created and added to the end of the specified basic block.
62 MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
64 : Opcode(opcode), numImplicitRefs(0), parent(0) {
65 assert(MBB && "Cannot use inserting ctor with null basic block!");
66 operands.reserve(numOperands);
67 // Make sure that we get added to a machine basicblock
68 LeakDetector::addGarbageObject(this);
69 MBB->push_back(this); // Add instruction to end of basic block!
72 ///MachineInstr ctor - Copies MachineInstr arg exactly
73 MachineInstr::MachineInstr(const MachineInstr &MI) {
74 Opcode = MI.getOpcode();
75 numImplicitRefs = MI.getNumImplicitRefs();
76 operands.reserve(MI.getNumOperands());
79 for(unsigned i=0; i < MI.getNumOperands(); ++i)
80 operands.push_back(MachineOperand(MI.getOperand(i)));
84 MachineInstr::~MachineInstr()
86 LeakDetector::removeGarbageObject(this);
89 ///clone - Create a copy of 'this' instruction that is identical in
90 ///all ways except the following: The instruction has no parent The
91 ///instruction has no name
92 MachineInstr* MachineInstr::clone() {
93 return new MachineInstr(*this);
96 /// OperandComplete - Return true if it's illegal to add a new operand
98 bool MachineInstr::OperandsComplete() const {
99 int NumOperands = TargetInstrDescriptors[Opcode].numOperands;
100 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
101 return true; // Broken: we have all the operands of this instruction!
105 /// replace - Support for replacing opcode and operands of a MachineInstr in
106 /// place. This only resets the size of the operand vector and initializes it.
107 /// The new operands must be set explicitly later.
109 void MachineInstr::replace(short opcode, unsigned numOperands) {
110 assert(getNumImplicitRefs() == 0 &&
111 "This is probably broken because implicit refs are going to be lost.");
114 operands.resize(numOperands, MachineOperand());
118 void MachineInstr::SetMachineOperandVal(unsigned i,
119 MachineOperand::MachineOperandType opTy,
121 assert(i < operands.size()); // may be explicit or implicit op
122 operands[i].opType = opTy;
123 operands[i].contents.value = V;
124 operands[i].regNum = -1;
128 MachineInstr::SetMachineOperandConst(unsigned i,
129 MachineOperand::MachineOperandType opTy,
131 assert(i < getNumOperands()); // must be explicit op
132 assert(TargetInstrDescriptors[Opcode].resultPos != (int) i &&
133 "immed. constant cannot be defined");
135 operands[i].opType = opTy;
136 operands[i].contents.value = NULL;
137 operands[i].contents.immedVal = intValue;
138 operands[i].regNum = -1;
139 operands[i].flags = 0;
142 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
143 assert(i < getNumOperands()); // must be explicit op
145 operands[i].opType = MachineOperand::MO_MachineRegister;
146 operands[i].contents.value = NULL;
147 operands[i].regNum = regNum;
150 // Used only by the SPARC back-end.
151 void MachineInstr::SetRegForOperand(unsigned i, int regNum) {
152 assert(i < getNumOperands()); // must be explicit op
153 operands[i].setRegForValue(regNum);
156 // Used only by the SPARC back-end.
157 void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) {
158 getImplicitOp(i).setRegForValue(regNum);
161 /// substituteValue - Substitute all occurrences of Value* oldVal with newVal
162 /// in all operands and all implicit refs. If defsOnly == true, substitute defs
165 /// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865,
166 /// or make it a static function in that file.
169 MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
170 bool defsOnly, bool notDefsAndUses,
171 bool& someArgsWereIgnored)
173 assert((!defsOnly || !notDefsAndUses) &&
174 "notDefsAndUses is irrelevant if defsOnly == true.");
176 unsigned numSubst = 0;
178 // Substitute operands
179 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
182 notDefsAndUses && (O.isDef() && !O.isUse()) ||
183 !notDefsAndUses && O.isDef())
185 O.getMachineOperand().contents.value = newVal;
189 someArgsWereIgnored = true;
191 // Substitute implicit refs
192 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
193 if (getImplicitRef(i) == oldVal)
195 notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
196 !notDefsAndUses && getImplicitOp(i).isDef())
198 getImplicitOp(i).contents.value = newVal;
202 someArgsWereIgnored = true;
207 void MachineInstr::dump() const {
208 std::cerr << " " << *this;
211 static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
213 os << (void*) val; // print address always
214 if (val && val->hasName())
215 os << " " << val->getName(); // print name also, if available
220 static inline void OutputReg(std::ostream &os, unsigned RegNo,
221 const MRegisterInfo *MRI = 0) {
222 if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
224 os << "%" << MRI->get(RegNo).Name;
226 os << "%mreg(" << RegNo << ")";
228 os << "%reg" << RegNo;
231 static void print(const MachineOperand &MO, std::ostream &OS,
232 const TargetMachine &TM) {
233 const MRegisterInfo *MRI = TM.getRegisterInfo();
234 bool CloseParen = true;
237 else if (MO.isLoBits32())
239 else if (MO.isHiBits64())
241 else if (MO.isLoBits64())
246 switch (MO.getType()) {
247 case MachineOperand::MO_VirtualRegister:
248 if (MO.getVRegValue()) {
250 OutputValue(OS, MO.getVRegValue());
251 if (MO.hasAllocatedReg())
254 if (MO.hasAllocatedReg())
255 OutputReg(OS, MO.getReg(), MRI);
257 case MachineOperand::MO_CCRegister:
259 OutputValue(OS, MO.getVRegValue());
260 if (MO.hasAllocatedReg()) {
262 OutputReg(OS, MO.getReg(), MRI);
265 case MachineOperand::MO_MachineRegister:
266 OutputReg(OS, MO.getMachineRegNum(), MRI);
268 case MachineOperand::MO_SignExtendedImmed:
269 OS << (long)MO.getImmedValue();
271 case MachineOperand::MO_UnextendedImmed:
272 OS << (long)MO.getImmedValue();
274 case MachineOperand::MO_PCRelativeDisp: {
275 const Value* opVal = MO.getVRegValue();
276 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
277 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
278 if (opVal->hasName())
279 OS << opVal->getName();
281 OS << (const void*) opVal;
285 case MachineOperand::MO_MachineBasicBlock:
287 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
288 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
290 case MachineOperand::MO_FrameIndex:
291 OS << "<fi#" << MO.getFrameIndex() << ">";
293 case MachineOperand::MO_ConstantPoolIndex:
294 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
296 case MachineOperand::MO_GlobalAddress:
297 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
299 case MachineOperand::MO_ExternalSymbol:
300 OS << "<es:" << MO.getSymbolName() << ">";
303 assert(0 && "Unrecognized operand type");
310 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
311 unsigned StartOp = 0;
313 // Specialize printing if op#0 is definition
314 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
315 ::print(getOperand(0), OS, TM);
317 ++StartOp; // Don't print this operand again!
319 OS << TM.getInstrInfo().getName(getOpcode());
321 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
322 const MachineOperand& mop = getOperand(i);
326 ::print(mop, OS, TM);
335 // code for printing implicit references
336 if (getNumImplicitRefs()) {
337 OS << "\tImplicitRefs: ";
338 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
340 OutputValue(OS, getImplicitRef(i));
341 if (getImplicitOp(i).isDef())
342 if (getImplicitOp(i).isUse())
353 std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
354 // If the instruction is embedded into a basic block, we can find the target
355 // info for the instruction.
356 if (const MachineBasicBlock *MBB = MI.getParent()) {
357 const MachineFunction *MF = MBB->getParent();
358 MI.print(os, MF->getTarget());
362 // Otherwise, print it out in the "raw" format without symbolic register names
364 os << TargetInstrDescriptors[MI.getOpcode()].Name;
366 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
367 os << "\t" << MI.getOperand(i);
368 if (MI.getOperand(i).isDef())
369 if (MI.getOperand(i).isUse())
375 // code for printing implicit references
376 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
377 if (NumOfImpRefs > 0) {
378 os << "\tImplicit: ";
379 for (unsigned z=0; z < NumOfImpRefs; z++) {
380 OutputValue(os, MI.getImplicitRef(z));
381 if (MI.getImplicitOp(z).isDef())
382 if (MI.getImplicitOp(z).isUse())
393 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
396 else if (MO.isLoBits32())
398 else if (MO.isHiBits64())
400 else if (MO.isLoBits64())
403 switch (MO.getType())
405 case MachineOperand::MO_VirtualRegister:
406 if (MO.hasAllocatedReg())
407 OutputReg(OS, MO.getReg());
409 if (MO.getVRegValue()) {
410 if (MO.hasAllocatedReg()) OS << "==";
412 OutputValue(OS, MO.getVRegValue());
415 case MachineOperand::MO_CCRegister:
417 OutputValue(OS, MO.getVRegValue());
418 if (MO.hasAllocatedReg()) {
420 OutputReg(OS, MO.getReg());
423 case MachineOperand::MO_MachineRegister:
424 OutputReg(OS, MO.getMachineRegNum());
426 case MachineOperand::MO_SignExtendedImmed:
427 OS << (long)MO.getImmedValue();
429 case MachineOperand::MO_UnextendedImmed:
430 OS << (long)MO.getImmedValue();
432 case MachineOperand::MO_PCRelativeDisp:
434 const Value* opVal = MO.getVRegValue();
435 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
436 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
437 if (opVal->hasName())
438 OS << opVal->getName();
440 OS << (const void*) opVal;
444 case MachineOperand::MO_MachineBasicBlock:
446 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
447 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
449 case MachineOperand::MO_FrameIndex:
450 OS << "<fi#" << MO.getFrameIndex() << ">";
452 case MachineOperand::MO_ConstantPoolIndex:
453 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
455 case MachineOperand::MO_GlobalAddress:
456 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
458 case MachineOperand::MO_ExternalSymbol:
459 OS << "<es:" << MO.getSymbolName() << ">";
462 assert(0 && "Unrecognized operand type");
466 if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())