1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Function.h"
17 #include "llvm/InlineAsm.h"
18 #include "llvm/Metadata.h"
19 #include "llvm/Type.h"
20 #include "llvm/Value.h"
21 #include "llvm/Assembly/Writer.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetInstrDesc.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/Analysis/AliasAnalysis.h"
33 #include "llvm/Analysis/DebugInfo.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/LeakDetector.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/ADT/FoldingSet.h"
42 //===----------------------------------------------------------------------===//
43 // MachineOperand Implementation
44 //===----------------------------------------------------------------------===//
46 /// AddRegOperandToRegInfo - Add this register operand to the specified
47 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
48 /// explicitly nulled out.
49 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
50 assert(isReg() && "Can only add reg operand to use lists");
52 // If the reginfo pointer is null, just explicitly null out or next/prev
53 // pointers, to ensure they are not garbage.
55 Contents.Reg.Prev = 0;
56 Contents.Reg.Next = 0;
60 // Otherwise, add this operand to the head of the registers use/def list.
61 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
63 // For SSA values, we prefer to keep the definition at the start of the list.
64 // we do this by skipping over the definition if it is at the head of the
66 if (*Head && (*Head)->isDef())
67 Head = &(*Head)->Contents.Reg.Next;
69 Contents.Reg.Next = *Head;
70 if (Contents.Reg.Next) {
71 assert(getReg() == Contents.Reg.Next->getReg() &&
72 "Different regs on the same list!");
73 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
76 Contents.Reg.Prev = Head;
80 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
81 /// MachineRegisterInfo it is linked with.
82 void MachineOperand::RemoveRegOperandFromRegInfo() {
83 assert(isOnRegUseList() && "Reg operand is not on a use list");
84 // Unlink this from the doubly linked list of operands.
85 MachineOperand *NextOp = Contents.Reg.Next;
86 *Contents.Reg.Prev = NextOp;
88 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
89 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
91 Contents.Reg.Prev = 0;
92 Contents.Reg.Next = 0;
95 void MachineOperand::setReg(unsigned Reg) {
96 if (getReg() == Reg) return; // No change.
98 // Otherwise, we have to change the register. If this operand is embedded
99 // into a machine function, we need to update the old and new register's
101 if (MachineInstr *MI = getParent())
102 if (MachineBasicBlock *MBB = MI->getParent())
103 if (MachineFunction *MF = MBB->getParent()) {
104 RemoveRegOperandFromRegInfo();
105 Contents.Reg.RegNo = Reg;
106 AddRegOperandToRegInfo(&MF->getRegInfo());
110 // Otherwise, just change the register, no problem. :)
111 Contents.Reg.RegNo = Reg;
114 /// ChangeToImmediate - Replace this operand with a new immediate operand of
115 /// the specified value. If an operand is known to be an immediate already,
116 /// the setImm method should be used.
117 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
118 // If this operand is currently a register operand, and if this is in a
119 // function, deregister the operand from the register's use/def list.
120 if (isReg() && getParent() && getParent()->getParent() &&
121 getParent()->getParent()->getParent())
122 RemoveRegOperandFromRegInfo();
124 OpKind = MO_Immediate;
125 Contents.ImmVal = ImmVal;
128 /// ChangeToRegister - Replace this operand with a new register operand of
129 /// the specified value. If an operand is known to be an register already,
130 /// the setReg method should be used.
131 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
132 bool isKill, bool isDead, bool isUndef,
134 // If this operand is already a register operand, use setReg to update the
135 // register's use/def lists.
137 assert(!isEarlyClobber());
140 // Otherwise, change this to a register and set the reg#.
141 OpKind = MO_Register;
142 Contents.Reg.RegNo = Reg;
144 // If this operand is embedded in a function, add the operand to the
145 // register's use/def list.
146 if (MachineInstr *MI = getParent())
147 if (MachineBasicBlock *MBB = MI->getParent())
148 if (MachineFunction *MF = MBB->getParent())
149 AddRegOperandToRegInfo(&MF->getRegInfo());
157 IsEarlyClobber = false;
162 /// isIdenticalTo - Return true if this operand is identical to the specified
164 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
165 if (getType() != Other.getType() ||
166 getTargetFlags() != Other.getTargetFlags())
170 default: llvm_unreachable("Unrecognized operand type");
171 case MachineOperand::MO_Register:
172 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
173 getSubReg() == Other.getSubReg();
174 case MachineOperand::MO_Immediate:
175 return getImm() == Other.getImm();
176 case MachineOperand::MO_FPImmediate:
177 return getFPImm() == Other.getFPImm();
178 case MachineOperand::MO_MachineBasicBlock:
179 return getMBB() == Other.getMBB();
180 case MachineOperand::MO_FrameIndex:
181 return getIndex() == Other.getIndex();
182 case MachineOperand::MO_ConstantPoolIndex:
183 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
184 case MachineOperand::MO_JumpTableIndex:
185 return getIndex() == Other.getIndex();
186 case MachineOperand::MO_GlobalAddress:
187 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
188 case MachineOperand::MO_ExternalSymbol:
189 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
190 getOffset() == Other.getOffset();
191 case MachineOperand::MO_BlockAddress:
192 return getBlockAddress() == Other.getBlockAddress();
193 case MachineOperand::MO_MCSymbol:
194 return getMCSymbol() == Other.getMCSymbol();
198 /// print - Print the specified machine operand.
200 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
201 // If the instruction is embedded into a basic block, we can find the
202 // target info for the instruction.
204 if (const MachineInstr *MI = getParent())
205 if (const MachineBasicBlock *MBB = MI->getParent())
206 if (const MachineFunction *MF = MBB->getParent())
207 TM = &MF->getTarget();
210 case MachineOperand::MO_Register:
211 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
212 OS << "%reg" << getReg();
215 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
217 OS << "%physreg" << getReg();
220 if (getSubReg() != 0)
221 OS << ':' << getSubReg();
223 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
226 bool NeedComma = false;
228 if (NeedComma) OS << ',';
229 if (isEarlyClobber())
230 OS << "earlyclobber,";
235 } else if (isImplicit()) {
240 if (isKill() || isDead() || isUndef()) {
241 if (NeedComma) OS << ',';
242 if (isKill()) OS << "kill";
243 if (isDead()) OS << "dead";
245 if (isKill() || isDead())
253 case MachineOperand::MO_Immediate:
256 case MachineOperand::MO_FPImmediate:
257 if (getFPImm()->getType()->isFloatTy())
258 OS << getFPImm()->getValueAPF().convertToFloat();
260 OS << getFPImm()->getValueAPF().convertToDouble();
262 case MachineOperand::MO_MachineBasicBlock:
263 OS << "<BB#" << getMBB()->getNumber() << ">";
265 case MachineOperand::MO_FrameIndex:
266 OS << "<fi#" << getIndex() << '>';
268 case MachineOperand::MO_ConstantPoolIndex:
269 OS << "<cp#" << getIndex();
270 if (getOffset()) OS << "+" << getOffset();
273 case MachineOperand::MO_JumpTableIndex:
274 OS << "<jt#" << getIndex() << '>';
276 case MachineOperand::MO_GlobalAddress:
278 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
279 if (getOffset()) OS << "+" << getOffset();
282 case MachineOperand::MO_ExternalSymbol:
283 OS << "<es:" << getSymbolName();
284 if (getOffset()) OS << "+" << getOffset();
287 case MachineOperand::MO_BlockAddress:
289 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
292 case MachineOperand::MO_Metadata:
294 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
297 case MachineOperand::MO_MCSymbol:
298 OS << "<MCSym=" << *getMCSymbol() << '>';
301 llvm_unreachable("Unrecognized operand type");
304 if (unsigned TF = getTargetFlags())
305 OS << "[TF=" << TF << ']';
308 //===----------------------------------------------------------------------===//
309 // MachineMemOperand Implementation
310 //===----------------------------------------------------------------------===//
312 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
313 int64_t o, uint64_t s, unsigned int a)
314 : Offset(o), Size(s), V(v),
315 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)) {
316 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
317 assert((isLoad() || isStore()) && "Not a load/store!");
320 /// Profile - Gather unique data for the object.
322 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
323 ID.AddInteger(Offset);
326 ID.AddInteger(Flags);
329 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
330 // The Value and Offset may differ due to CSE. But the flags and size
331 // should be the same.
332 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
333 assert(MMO->getSize() == getSize() && "Size mismatch!");
335 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
336 // Update the alignment value.
337 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
338 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
339 // Also update the base and offset, because the new alignment may
340 // not be applicable with the old ones.
342 Offset = MMO->getOffset();
346 /// getAlignment - Return the minimum known alignment in bytes of the
347 /// actual memory reference.
348 uint64_t MachineMemOperand::getAlignment() const {
349 return MinAlign(getBaseAlignment(), getOffset());
352 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
353 assert((MMO.isLoad() || MMO.isStore()) &&
354 "SV has to be a load, store or both.");
356 if (MMO.isVolatile())
365 // Print the address information.
370 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
372 // If the alignment of the memory reference itself differs from the alignment
373 // of the base pointer, print the base alignment explicitly, next to the base
375 if (MMO.getBaseAlignment() != MMO.getAlignment())
376 OS << "(align=" << MMO.getBaseAlignment() << ")";
378 if (MMO.getOffset() != 0)
379 OS << "+" << MMO.getOffset();
382 // Print the alignment of the reference.
383 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
384 MMO.getBaseAlignment() != MMO.getSize())
385 OS << "(align=" << MMO.getAlignment() << ")";
390 //===----------------------------------------------------------------------===//
391 // MachineInstr Implementation
392 //===----------------------------------------------------------------------===//
394 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
395 /// TID NULL and no operands.
396 MachineInstr::MachineInstr()
397 : TID(0), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
398 Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
399 // Make sure that we get added to a machine basicblock
400 LeakDetector::addGarbageObject(this);
403 void MachineInstr::addImplicitDefUseOperands() {
404 if (TID->ImplicitDefs)
405 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
406 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
407 if (TID->ImplicitUses)
408 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
409 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
412 /// MachineInstr ctor - This constructor create a MachineInstr and add the
413 /// implicit operands. It reserves space for number of operands specified by
414 /// TargetInstrDesc or the numOperands if it is not zero. (for
415 /// instructions with variable number of operands).
416 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
417 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
418 MemRefs(0), MemRefsEnd(0), Parent(0),
419 debugLoc(DebugLoc::getUnknownLoc()) {
420 if (!NoImp && TID->getImplicitDefs())
421 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
423 if (!NoImp && TID->getImplicitUses())
424 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
426 Operands.reserve(NumImplicitOps + TID->getNumOperands());
428 addImplicitDefUseOperands();
429 // Make sure that we get added to a machine basicblock
430 LeakDetector::addGarbageObject(this);
433 /// MachineInstr ctor - As above, but with a DebugLoc.
434 MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
436 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
437 Parent(0), debugLoc(dl) {
438 if (!NoImp && TID->getImplicitDefs())
439 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
441 if (!NoImp && TID->getImplicitUses())
442 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
444 Operands.reserve(NumImplicitOps + TID->getNumOperands());
446 addImplicitDefUseOperands();
447 // Make sure that we get added to a machine basicblock
448 LeakDetector::addGarbageObject(this);
451 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
452 /// that the MachineInstr is created and added to the end of the specified
455 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
456 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
457 MemRefs(0), MemRefsEnd(0), Parent(0),
458 debugLoc(DebugLoc::getUnknownLoc()) {
459 assert(MBB && "Cannot use inserting ctor with null basic block!");
460 if (TID->ImplicitDefs)
461 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
463 if (TID->ImplicitUses)
464 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
466 Operands.reserve(NumImplicitOps + TID->getNumOperands());
467 addImplicitDefUseOperands();
468 // Make sure that we get added to a machine basicblock
469 LeakDetector::addGarbageObject(this);
470 MBB->push_back(this); // Add instruction to end of basic block!
473 /// MachineInstr ctor - As above, but with a DebugLoc.
475 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
476 const TargetInstrDesc &tid)
477 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
478 Parent(0), debugLoc(dl) {
479 assert(MBB && "Cannot use inserting ctor with null basic block!");
480 if (TID->ImplicitDefs)
481 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
483 if (TID->ImplicitUses)
484 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
486 Operands.reserve(NumImplicitOps + TID->getNumOperands());
487 addImplicitDefUseOperands();
488 // Make sure that we get added to a machine basicblock
489 LeakDetector::addGarbageObject(this);
490 MBB->push_back(this); // Add instruction to end of basic block!
493 /// MachineInstr ctor - Copies MachineInstr arg exactly
495 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
496 : TID(&MI.getDesc()), NumImplicitOps(0), AsmPrinterFlags(0),
497 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
498 Parent(0), debugLoc(MI.getDebugLoc()) {
499 Operands.reserve(MI.getNumOperands());
502 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
503 addOperand(MI.getOperand(i));
504 NumImplicitOps = MI.NumImplicitOps;
506 // Set parent to null.
509 LeakDetector::addGarbageObject(this);
512 MachineInstr::~MachineInstr() {
513 LeakDetector::removeGarbageObject(this);
515 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
516 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
517 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
518 "Reg operand def/use list corrupted");
523 /// getRegInfo - If this instruction is embedded into a MachineFunction,
524 /// return the MachineRegisterInfo object for the current function, otherwise
526 MachineRegisterInfo *MachineInstr::getRegInfo() {
527 if (MachineBasicBlock *MBB = getParent())
528 return &MBB->getParent()->getRegInfo();
532 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
533 /// this instruction from their respective use lists. This requires that the
534 /// operands already be on their use lists.
535 void MachineInstr::RemoveRegOperandsFromUseLists() {
536 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
537 if (Operands[i].isReg())
538 Operands[i].RemoveRegOperandFromRegInfo();
542 /// AddRegOperandsToUseLists - Add all of the register operands in
543 /// this instruction from their respective use lists. This requires that the
544 /// operands not be on their use lists yet.
545 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
546 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
547 if (Operands[i].isReg())
548 Operands[i].AddRegOperandToRegInfo(&RegInfo);
553 /// addOperand - Add the specified operand to the instruction. If it is an
554 /// implicit operand, it is added to the end of the operand list. If it is
555 /// an explicit operand it is added at the end of the explicit operand list
556 /// (before the first implicit operand).
557 void MachineInstr::addOperand(const MachineOperand &Op) {
558 bool isImpReg = Op.isReg() && Op.isImplicit();
559 assert((isImpReg || !OperandsComplete()) &&
560 "Trying to add an operand to a machine instr that is already done!");
562 MachineRegisterInfo *RegInfo = getRegInfo();
564 // If we are adding the operand to the end of the list, our job is simpler.
565 // This is true most of the time, so this is a reasonable optimization.
566 if (isImpReg || NumImplicitOps == 0) {
567 // We can only do this optimization if we know that the operand list won't
569 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
570 Operands.push_back(Op);
572 // Set the parent of the operand.
573 Operands.back().ParentMI = this;
575 // If the operand is a register, update the operand's use list.
577 Operands.back().AddRegOperandToRegInfo(RegInfo);
578 // If the register operand is flagged as early, mark the operand as such
579 unsigned OpNo = Operands.size() - 1;
580 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
581 Operands[OpNo].setIsEarlyClobber(true);
587 // Otherwise, we have to insert a real operand before any implicit ones.
588 unsigned OpNo = Operands.size()-NumImplicitOps;
590 // If this instruction isn't embedded into a function, then we don't need to
591 // update any operand lists.
593 // Simple insertion, no reginfo update needed for other register operands.
594 Operands.insert(Operands.begin()+OpNo, Op);
595 Operands[OpNo].ParentMI = this;
597 // Do explicitly set the reginfo for this operand though, to ensure the
598 // next/prev fields are properly nulled out.
599 if (Operands[OpNo].isReg()) {
600 Operands[OpNo].AddRegOperandToRegInfo(0);
601 // If the register operand is flagged as early, mark the operand as such
602 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
603 Operands[OpNo].setIsEarlyClobber(true);
606 } else if (Operands.size()+1 <= Operands.capacity()) {
607 // Otherwise, we have to remove register operands from their register use
608 // list, add the operand, then add the register operands back to their use
609 // list. This also must handle the case when the operand list reallocates
610 // to somewhere else.
612 // If insertion of this operand won't cause reallocation of the operand
613 // list, just remove the implicit operands, add the operand, then re-add all
614 // the rest of the operands.
615 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
616 assert(Operands[i].isReg() && "Should only be an implicit reg!");
617 Operands[i].RemoveRegOperandFromRegInfo();
620 // Add the operand. If it is a register, add it to the reg list.
621 Operands.insert(Operands.begin()+OpNo, Op);
622 Operands[OpNo].ParentMI = this;
624 if (Operands[OpNo].isReg()) {
625 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
626 // If the register operand is flagged as early, mark the operand as such
627 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
628 Operands[OpNo].setIsEarlyClobber(true);
631 // Re-add all the implicit ops.
632 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
633 assert(Operands[i].isReg() && "Should only be an implicit reg!");
634 Operands[i].AddRegOperandToRegInfo(RegInfo);
637 // Otherwise, we will be reallocating the operand list. Remove all reg
638 // operands from their list, then readd them after the operand list is
640 RemoveRegOperandsFromUseLists();
642 Operands.insert(Operands.begin()+OpNo, Op);
643 Operands[OpNo].ParentMI = this;
645 // Re-add all the operands.
646 AddRegOperandsToUseLists(*RegInfo);
648 // If the register operand is flagged as early, mark the operand as such
649 if (Operands[OpNo].isReg()
650 && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
651 Operands[OpNo].setIsEarlyClobber(true);
655 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
656 /// fewer operand than it started with.
658 void MachineInstr::RemoveOperand(unsigned OpNo) {
659 assert(OpNo < Operands.size() && "Invalid operand number");
661 // Special case removing the last one.
662 if (OpNo == Operands.size()-1) {
663 // If needed, remove from the reg def/use list.
664 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
665 Operands.back().RemoveRegOperandFromRegInfo();
671 // Otherwise, we are removing an interior operand. If we have reginfo to
672 // update, remove all operands that will be shifted down from their reg lists,
673 // move everything down, then re-add them.
674 MachineRegisterInfo *RegInfo = getRegInfo();
676 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
677 if (Operands[i].isReg())
678 Operands[i].RemoveRegOperandFromRegInfo();
682 Operands.erase(Operands.begin()+OpNo);
685 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
686 if (Operands[i].isReg())
687 Operands[i].AddRegOperandToRegInfo(RegInfo);
692 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
693 /// This function should be used only occasionally. The setMemRefs function
694 /// is the primary method for setting up a MachineInstr's MemRefs list.
695 void MachineInstr::addMemOperand(MachineFunction &MF,
696 MachineMemOperand *MO) {
697 mmo_iterator OldMemRefs = MemRefs;
698 mmo_iterator OldMemRefsEnd = MemRefsEnd;
700 size_t NewNum = (MemRefsEnd - MemRefs) + 1;
701 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
702 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
704 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
705 NewMemRefs[NewNum - 1] = MO;
707 MemRefs = NewMemRefs;
708 MemRefsEnd = NewMemRefsEnd;
711 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
712 MICheckType Check) const {
713 // If opcodes or number of operands are not the same then the two
714 // instructions are obviously not identical.
715 if (Other->getOpcode() != getOpcode() ||
716 Other->getNumOperands() != getNumOperands())
719 // Check operands to make sure they match.
720 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
721 const MachineOperand &MO = getOperand(i);
722 const MachineOperand &OMO = Other->getOperand(i);
723 // Clients may or may not want to ignore defs when testing for equality.
724 // For example, machine CSE pass only cares about finding common
725 // subexpressions, so it's safe to ignore virtual register defs.
726 if (Check != CheckDefs && MO.isReg() && MO.isDef()) {
727 if (Check == IgnoreDefs)
729 // Check == IgnoreVRegDefs
730 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
731 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
732 if (MO.getReg() != OMO.getReg())
734 } else if (!MO.isIdenticalTo(OMO))
740 /// removeFromParent - This method unlinks 'this' from the containing basic
741 /// block, and returns it, but does not delete it.
742 MachineInstr *MachineInstr::removeFromParent() {
743 assert(getParent() && "Not embedded in a basic block!");
744 getParent()->remove(this);
749 /// eraseFromParent - This method unlinks 'this' from the containing basic
750 /// block, and deletes it.
751 void MachineInstr::eraseFromParent() {
752 assert(getParent() && "Not embedded in a basic block!");
753 getParent()->erase(this);
757 /// OperandComplete - Return true if it's illegal to add a new operand
759 bool MachineInstr::OperandsComplete() const {
760 unsigned short NumOperands = TID->getNumOperands();
761 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
762 return true; // Broken: we have all the operands of this instruction!
766 /// getNumExplicitOperands - Returns the number of non-implicit operands.
768 unsigned MachineInstr::getNumExplicitOperands() const {
769 unsigned NumOperands = TID->getNumOperands();
770 if (!TID->isVariadic())
773 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
774 const MachineOperand &MO = getOperand(i);
775 if (!MO.isReg() || !MO.isImplicit())
782 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
783 /// the specific register or -1 if it is not found. It further tightens
784 /// the search criteria to a use that kills the register if isKill is true.
785 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
786 const TargetRegisterInfo *TRI) const {
787 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
788 const MachineOperand &MO = getOperand(i);
789 if (!MO.isReg() || !MO.isUse())
791 unsigned MOReg = MO.getReg();
796 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
797 TargetRegisterInfo::isPhysicalRegister(Reg) &&
798 TRI->isSubRegister(MOReg, Reg)))
799 if (!isKill || MO.isKill())
805 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
806 /// the specified register or -1 if it is not found. If isDead is true, defs
807 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
808 /// also checks if there is a def of a super-register.
809 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
810 const TargetRegisterInfo *TRI) const {
811 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
812 const MachineOperand &MO = getOperand(i);
813 if (!MO.isReg() || !MO.isDef())
815 unsigned MOReg = MO.getReg();
818 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
819 TargetRegisterInfo::isPhysicalRegister(Reg) &&
820 TRI->isSubRegister(MOReg, Reg)))
821 if (!isDead || MO.isDead())
827 /// findFirstPredOperandIdx() - Find the index of the first operand in the
828 /// operand list that is used to represent the predicate. It returns -1 if
830 int MachineInstr::findFirstPredOperandIdx() const {
831 const TargetInstrDesc &TID = getDesc();
832 if (TID.isPredicable()) {
833 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
834 if (TID.OpInfo[i].isPredicate())
841 /// isRegTiedToUseOperand - Given the index of a register def operand,
842 /// check if the register def is tied to a source operand, due to either
843 /// two-address elimination or inline assembly constraints. Returns the
844 /// first tied use operand index by reference is UseOpIdx is not null.
846 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
848 assert(DefOpIdx >= 2);
849 const MachineOperand &MO = getOperand(DefOpIdx);
850 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
852 // Determine the actual operand index that corresponds to this index.
854 unsigned DefPart = 0;
855 for (unsigned i = 1, e = getNumOperands(); i < e; ) {
856 const MachineOperand &FMO = getOperand(i);
857 // After the normal asm operands there may be additional imp-def regs.
860 // Skip over this def.
861 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
862 unsigned PrevDef = i + 1;
863 i = PrevDef + NumOps;
865 DefPart = DefOpIdx - PrevDef;
870 for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
871 const MachineOperand &FMO = getOperand(i);
874 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
877 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
880 *UseOpIdx = (unsigned)i + 1 + DefPart;
887 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
888 const TargetInstrDesc &TID = getDesc();
889 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
890 const MachineOperand &MO = getOperand(i);
891 if (MO.isReg() && MO.isUse() &&
892 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
894 *UseOpIdx = (unsigned)i;
901 /// isRegTiedToDefOperand - Return true if the operand of the specified index
902 /// is a register use and it is tied to an def operand. It also returns the def
903 /// operand index by reference.
905 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
907 const MachineOperand &MO = getOperand(UseOpIdx);
908 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
911 // Find the flag operand corresponding to UseOpIdx
912 unsigned FlagIdx, NumOps=0;
913 for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
914 const MachineOperand &UFMO = getOperand(FlagIdx);
915 // After the normal asm operands there may be additional imp-def regs.
918 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
919 assert(NumOps < getNumOperands() && "Invalid inline asm flag");
920 if (UseOpIdx < FlagIdx+NumOps+1)
923 if (FlagIdx >= UseOpIdx)
925 const MachineOperand &UFMO = getOperand(FlagIdx);
927 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
932 // Remember to adjust the index. First operand is asm string, then there
933 // is a flag for each.
935 const MachineOperand &FMO = getOperand(DefIdx);
937 // Skip over this def.
938 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
941 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
947 const TargetInstrDesc &TID = getDesc();
948 if (UseOpIdx >= TID.getNumOperands())
950 const MachineOperand &MO = getOperand(UseOpIdx);
951 if (!MO.isReg() || !MO.isUse())
953 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
957 *DefOpIdx = (unsigned)DefIdx;
961 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
963 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
964 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
965 const MachineOperand &MO = MI->getOperand(i);
966 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
968 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
969 MachineOperand &MOp = getOperand(j);
970 if (!MOp.isIdenticalTo(MO))
981 /// copyPredicates - Copies predicate operand(s) from MI.
982 void MachineInstr::copyPredicates(const MachineInstr *MI) {
983 const TargetInstrDesc &TID = MI->getDesc();
984 if (!TID.isPredicable())
986 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
987 if (TID.OpInfo[i].isPredicate()) {
988 // Predicated operands must be last operands.
989 addOperand(MI->getOperand(i));
994 /// isSafeToMove - Return true if it is safe to move this instruction. If
995 /// SawStore is set to true, it means that there is a store (or call) between
996 /// the instruction's location and its intended destination.
997 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
999 bool &SawStore) const {
1000 // Ignore stuff that we obviously can't move.
1001 if (TID->mayStore() || TID->isCall()) {
1005 if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
1008 // See if this instruction does a load. If so, we have to guarantee that the
1009 // loaded value doesn't change between the load and the its intended
1010 // destination. The check for isInvariantLoad gives the targe the chance to
1011 // classify the load as always returning a constant, e.g. a constant pool
1013 if (TID->mayLoad() && !isInvariantLoad(AA))
1014 // Otherwise, this is a real load. If there is a store between the load and
1015 // end of block, or if the load is volatile, we can't move it.
1016 return !SawStore && !hasVolatileMemoryRef();
1021 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1022 /// instruction which defined the specified register instead of copying it.
1023 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1025 unsigned DstReg) const {
1026 bool SawStore = false;
1027 if (!TII->isTriviallyReMaterializable(this, AA) ||
1028 !isSafeToMove(TII, AA, SawStore))
1030 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1031 const MachineOperand &MO = getOperand(i);
1034 // FIXME: For now, do not remat any instruction with register operands.
1035 // Later on, we can loosen the restriction is the register operands have
1036 // not been modified between the def and use. Note, this is different from
1037 // MachineSink because the code is no longer in two-address form (at least
1041 else if (!MO.isDead() && MO.getReg() != DstReg)
1047 /// hasVolatileMemoryRef - Return true if this instruction may have a
1048 /// volatile memory reference, or if the information describing the
1049 /// memory reference is not available. Return false if it is known to
1050 /// have no volatile memory references.
1051 bool MachineInstr::hasVolatileMemoryRef() const {
1052 // An instruction known never to access memory won't have a volatile access.
1053 if (!TID->mayStore() &&
1056 !TID->hasUnmodeledSideEffects())
1059 // Otherwise, if the instruction has no memory reference information,
1060 // conservatively assume it wasn't preserved.
1061 if (memoperands_empty())
1064 // Check the memory reference information for volatile references.
1065 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1066 if ((*I)->isVolatile())
1072 /// isInvariantLoad - Return true if this instruction is loading from a
1073 /// location whose value is invariant across the function. For example,
1074 /// loading a value from the constant pool or from the argument area
1075 /// of a function if it does not change. This should only return true of
1076 /// *all* loads the instruction does are invariant (if it does multiple loads).
1077 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1078 // If the instruction doesn't load at all, it isn't an invariant load.
1079 if (!TID->mayLoad())
1082 // If the instruction has lost its memoperands, conservatively assume that
1083 // it may not be an invariant load.
1084 if (memoperands_empty())
1087 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1089 for (mmo_iterator I = memoperands_begin(),
1090 E = memoperands_end(); I != E; ++I) {
1091 if ((*I)->isVolatile()) return false;
1092 if ((*I)->isStore()) return false;
1094 if (const Value *V = (*I)->getValue()) {
1095 // A load from a constant PseudoSourceValue is invariant.
1096 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1097 if (PSV->isConstant(MFI))
1099 // If we have an AliasAnalysis, ask it whether the memory is constant.
1100 if (AA && AA->pointsToConstantMemory(V))
1104 // Otherwise assume conservatively.
1108 // Everything checks out.
1112 /// isConstantValuePHI - If the specified instruction is a PHI that always
1113 /// merges together the same virtual register, return the register, otherwise
1115 unsigned MachineInstr::isConstantValuePHI() const {
1118 assert(getNumOperands() >= 3 &&
1119 "It's illegal to have a PHI without source operands");
1121 unsigned Reg = getOperand(1).getReg();
1122 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1123 if (getOperand(i).getReg() != Reg)
1128 void MachineInstr::dump() const {
1129 dbgs() << " " << *this;
1132 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1133 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1134 const MachineFunction *MF = 0;
1135 if (const MachineBasicBlock *MBB = getParent()) {
1136 MF = MBB->getParent();
1138 TM = &MF->getTarget();
1141 // Print explicitly defined operands on the left of an assignment syntax.
1142 unsigned StartOp = 0, e = getNumOperands();
1143 for (; StartOp < e && getOperand(StartOp).isReg() &&
1144 getOperand(StartOp).isDef() &&
1145 !getOperand(StartOp).isImplicit();
1147 if (StartOp != 0) OS << ", ";
1148 getOperand(StartOp).print(OS, TM);
1154 // Print the opcode name.
1155 OS << getDesc().getName();
1157 // Print the rest of the operands.
1158 bool OmittedAnyCallClobbers = false;
1159 bool FirstOp = true;
1160 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1161 const MachineOperand &MO = getOperand(i);
1163 // Omit call-clobbered registers which aren't used anywhere. This makes
1164 // call instructions much less noisy on targets where calls clobber lots
1165 // of registers. Don't rely on MO.isDead() because we may be called before
1166 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1167 if (MF && getDesc().isCall() &&
1168 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1169 unsigned Reg = MO.getReg();
1170 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
1171 const MachineRegisterInfo &MRI = MF->getRegInfo();
1172 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1173 bool HasAliasLive = false;
1174 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1175 unsigned AliasReg = *Alias; ++Alias)
1176 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1177 HasAliasLive = true;
1180 if (!HasAliasLive) {
1181 OmittedAnyCallClobbers = true;
1188 if (FirstOp) FirstOp = false; else OS << ",";
1190 if (i < getDesc().NumOperands) {
1191 const TargetOperandInfo &TOI = getDesc().OpInfo[i];
1192 if (TOI.isPredicate())
1194 if (TOI.isOptionalDef())
1200 // Briefly indicate whether any call clobbers were omitted.
1201 if (OmittedAnyCallClobbers) {
1202 if (!FirstOp) OS << ",";
1206 bool HaveSemi = false;
1207 if (!memoperands_empty()) {
1208 if (!HaveSemi) OS << ";"; HaveSemi = true;
1211 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1219 if (!debugLoc.isUnknown() && MF) {
1220 if (!HaveSemi) OS << ";";
1222 // TODO: print InlinedAtLoc information
1224 DILocation DLT = MF->getDILocation(debugLoc);
1225 DIScope Scope = DLT.getScope();
1227 // Omit the directory, since it's usually long and uninteresting.
1229 OS << Scope.getFilename();
1232 OS << ':' << DLT.getLineNumber();
1233 if (DLT.getColumnNumber() != 0)
1234 OS << ':' << DLT.getColumnNumber();
1240 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1241 const TargetRegisterInfo *RegInfo,
1242 bool AddIfNotFound) {
1243 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1244 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1246 SmallVector<unsigned,4> DeadOps;
1247 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1248 MachineOperand &MO = getOperand(i);
1249 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1251 unsigned Reg = MO.getReg();
1255 if (Reg == IncomingReg) {
1258 // The register is already marked kill.
1260 if (isPhysReg && isRegTiedToDefOperand(i))
1261 // Two-address uses of physregs must not be marked kill.
1266 } else if (hasAliases && MO.isKill() &&
1267 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1268 // A super-register kill already exists.
1269 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1271 if (RegInfo->isSubRegister(IncomingReg, Reg))
1272 DeadOps.push_back(i);
1276 // Trim unneeded kill operands.
1277 while (!DeadOps.empty()) {
1278 unsigned OpIdx = DeadOps.back();
1279 if (getOperand(OpIdx).isImplicit())
1280 RemoveOperand(OpIdx);
1282 getOperand(OpIdx).setIsKill(false);
1286 // If not found, this means an alias of one of the operands is killed. Add a
1287 // new implicit operand if required.
1288 if (!Found && AddIfNotFound) {
1289 addOperand(MachineOperand::CreateReg(IncomingReg,
1298 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1299 const TargetRegisterInfo *RegInfo,
1300 bool AddIfNotFound) {
1301 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1302 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1304 SmallVector<unsigned,4> DeadOps;
1305 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1306 MachineOperand &MO = getOperand(i);
1307 if (!MO.isReg() || !MO.isDef())
1309 unsigned Reg = MO.getReg();
1313 if (Reg == IncomingReg) {
1316 // The register is already marked dead.
1321 } else if (hasAliases && MO.isDead() &&
1322 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1323 // There exists a super-register that's marked dead.
1324 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1326 if (RegInfo->getSubRegisters(IncomingReg) &&
1327 RegInfo->getSuperRegisters(Reg) &&
1328 RegInfo->isSubRegister(IncomingReg, Reg))
1329 DeadOps.push_back(i);
1333 // Trim unneeded dead operands.
1334 while (!DeadOps.empty()) {
1335 unsigned OpIdx = DeadOps.back();
1336 if (getOperand(OpIdx).isImplicit())
1337 RemoveOperand(OpIdx);
1339 getOperand(OpIdx).setIsDead(false);
1343 // If not found, this means an alias of one of the operands is dead. Add a
1344 // new implicit operand if required.
1345 if (Found || !AddIfNotFound)
1348 addOperand(MachineOperand::CreateReg(IncomingReg,
1356 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1357 const TargetRegisterInfo *RegInfo) {
1358 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1359 if (!MO || MO->getSubReg())
1360 addOperand(MachineOperand::CreateReg(IncomingReg,
1366 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1367 unsigned Hash = MI->getOpcode() * 37;
1368 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1369 const MachineOperand &MO = MI->getOperand(i);
1370 uint64_t Key = (uint64_t)MO.getType() << 32;
1371 switch (MO.getType()) {
1373 case MachineOperand::MO_Register:
1374 if (MO.isDef() && MO.getReg() &&
1375 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1376 continue; // Skip virtual register defs.
1379 case MachineOperand::MO_Immediate:
1382 case MachineOperand::MO_FrameIndex:
1383 case MachineOperand::MO_ConstantPoolIndex:
1384 case MachineOperand::MO_JumpTableIndex:
1385 Key |= MO.getIndex();
1387 case MachineOperand::MO_MachineBasicBlock:
1388 Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1390 case MachineOperand::MO_GlobalAddress:
1391 Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1393 case MachineOperand::MO_BlockAddress:
1394 Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1396 case MachineOperand::MO_MCSymbol:
1397 Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1400 Key += ~(Key << 32);
1402 Key += ~(Key << 13);
1406 Key += ~(Key << 27);
1408 Hash = (unsigned)Key + Hash * 37;