1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Value.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/MRegisterInfo.h"
21 #include "llvm/Support/LeakDetector.h"
22 #include "llvm/Support/Streams.h"
26 //===----------------------------------------------------------------------===//
27 // MachineOperand Implementation
28 //===----------------------------------------------------------------------===//
30 /// AddRegOperandToRegInfo - Add this register operand to the specified
31 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
32 /// explicitly nulled out.
33 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
34 assert(isReg() && "Can only add reg operand to use lists");
36 // If the reginfo pointer is null, just explicitly null out or next/prev
37 // pointers, to ensure they are not garbage.
39 Contents.Reg.Prev = 0;
40 Contents.Reg.Next = 0;
44 // Otherwise, add this operand to the head of the registers use/def list.
45 MachineOperand *&Head = RegInfo->getRegUseDefListHead(getReg());
47 Contents.Reg.Next = Head;
48 if (Contents.Reg.Next) {
49 assert(getReg() == Contents.Reg.Next->getReg() &&
50 "Different regs on the same list!");
51 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
54 Contents.Reg.Prev = &Head;
58 void MachineOperand::setReg(unsigned Reg) {
59 if (getReg() == Reg) return; // No change.
61 // Otherwise, we have to change the register. If this operand is embedded
62 // into a machine function, we need to update the old and new register's
64 if (MachineInstr *MI = getParent())
65 if (MachineBasicBlock *MBB = MI->getParent())
66 if (MachineFunction *MF = MBB->getParent()) {
67 RemoveRegOperandFromRegInfo();
68 Contents.Reg.RegNo = Reg;
69 AddRegOperandToRegInfo(&MF->getRegInfo());
73 // Otherwise, just change the register, no problem. :)
74 Contents.Reg.RegNo = Reg;
77 /// ChangeToImmediate - Replace this operand with a new immediate operand of
78 /// the specified value. If an operand is known to be an immediate already,
79 /// the setImm method should be used.
80 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
81 // If this operand is currently a register operand, and if this is in a
82 // function, deregister the operand from the register's use/def list.
83 if (isReg() && getParent() && getParent()->getParent() &&
84 getParent()->getParent()->getParent())
85 RemoveRegOperandFromRegInfo();
87 OpKind = MO_Immediate;
88 Contents.ImmVal = ImmVal;
91 /// ChangeToRegister - Replace this operand with a new register operand of
92 /// the specified value. If an operand is known to be an register already,
93 /// the setReg method should be used.
94 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
95 bool isKill, bool isDead) {
96 // If this operand is already a register operand, use setReg to update the
97 // register's use/def lists.
101 // Otherwise, change this to a register and set the reg#.
102 OpKind = MO_Register;
103 Contents.Reg.RegNo = Reg;
105 // If this operand is embedded in a function, add the operand to the
106 // register's use/def list.
107 if (MachineInstr *MI = getParent())
108 if (MachineBasicBlock *MBB = MI->getParent())
109 if (MachineFunction *MF = MBB->getParent())
110 AddRegOperandToRegInfo(&MF->getRegInfo());
120 /// isIdenticalTo - Return true if this operand is identical to the specified
122 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
123 if (getType() != Other.getType()) return false;
126 default: assert(0 && "Unrecognized operand type");
127 case MachineOperand::MO_Register:
128 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
129 getSubReg() == Other.getSubReg();
130 case MachineOperand::MO_Immediate:
131 return getImm() == Other.getImm();
132 case MachineOperand::MO_MachineBasicBlock:
133 return getMBB() == Other.getMBB();
134 case MachineOperand::MO_FrameIndex:
135 return getIndex() == Other.getIndex();
136 case MachineOperand::MO_ConstantPoolIndex:
137 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
138 case MachineOperand::MO_JumpTableIndex:
139 return getIndex() == Other.getIndex();
140 case MachineOperand::MO_GlobalAddress:
141 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
142 case MachineOperand::MO_ExternalSymbol:
143 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
144 getOffset() == Other.getOffset();
148 /// print - Print the specified machine operand.
150 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
152 case MachineOperand::MO_Register:
153 if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) {
154 OS << "%reg" << getReg();
156 // If the instruction is embedded into a basic block, we can find the
157 // target info for the instruction.
159 if (const MachineInstr *MI = getParent())
160 if (const MachineBasicBlock *MBB = MI->getParent())
161 if (const MachineFunction *MF = MBB->getParent())
162 TM = &MF->getTarget();
165 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
167 OS << "%mreg" << getReg();
170 if (isDef() || isKill() || isDead() || isImplicit()) {
172 bool NeedComma = false;
174 OS << (isDef() ? "imp-def" : "imp-use");
176 } else if (isDef()) {
180 if (isKill() || isDead()) {
181 if (NeedComma) OS << ",";
182 if (isKill()) OS << "kill";
183 if (isDead()) OS << "dead";
188 case MachineOperand::MO_Immediate:
191 case MachineOperand::MO_MachineBasicBlock:
193 << ((Value*)getMBB()->getBasicBlock())->getName()
194 << "," << (void*)getMBB() << ">";
196 case MachineOperand::MO_FrameIndex:
197 OS << "<fi#" << getIndex() << ">";
199 case MachineOperand::MO_ConstantPoolIndex:
200 OS << "<cp#" << getIndex();
201 if (getOffset()) OS << "+" << getOffset();
204 case MachineOperand::MO_JumpTableIndex:
205 OS << "<jt#" << getIndex() << ">";
207 case MachineOperand::MO_GlobalAddress:
208 OS << "<ga:" << ((Value*)getGlobal())->getName();
209 if (getOffset()) OS << "+" << getOffset();
212 case MachineOperand::MO_ExternalSymbol:
213 OS << "<es:" << getSymbolName();
214 if (getOffset()) OS << "+" << getOffset();
218 assert(0 && "Unrecognized operand type");
222 //===----------------------------------------------------------------------===//
223 // MachineInstr Implementation
224 //===----------------------------------------------------------------------===//
226 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
227 /// TID NULL and no operands.
228 MachineInstr::MachineInstr()
229 : TID(0), NumImplicitOps(0), Parent(0) {
230 // Make sure that we get added to a machine basicblock
231 LeakDetector::addGarbageObject(this);
234 void MachineInstr::addImplicitDefUseOperands() {
235 if (TID->ImplicitDefs)
236 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
237 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
238 if (TID->ImplicitUses)
239 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
240 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
243 /// MachineInstr ctor - This constructor create a MachineInstr and add the
244 /// implicit operands. It reserves space for number of operands specified by
245 /// TargetInstrDescriptor or the numOperands if it is not zero. (for
246 /// instructions with variable number of operands).
247 MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
248 : TID(&tid), NumImplicitOps(0), Parent(0) {
249 if (!NoImp && TID->ImplicitDefs)
250 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
252 if (!NoImp && TID->ImplicitUses)
253 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
255 Operands.reserve(NumImplicitOps + TID->numOperands);
257 addImplicitDefUseOperands();
258 // Make sure that we get added to a machine basicblock
259 LeakDetector::addGarbageObject(this);
262 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
263 /// MachineInstr is created and added to the end of the specified basic block.
265 MachineInstr::MachineInstr(MachineBasicBlock *MBB,
266 const TargetInstrDescriptor &tid)
267 : TID(&tid), NumImplicitOps(0), Parent(0) {
268 assert(MBB && "Cannot use inserting ctor with null basic block!");
269 if (TID->ImplicitDefs)
270 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
272 if (TID->ImplicitUses)
273 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
275 Operands.reserve(NumImplicitOps + TID->numOperands);
276 addImplicitDefUseOperands();
277 // Make sure that we get added to a machine basicblock
278 LeakDetector::addGarbageObject(this);
279 MBB->push_back(this); // Add instruction to end of basic block!
282 /// MachineInstr ctor - Copies MachineInstr arg exactly
284 MachineInstr::MachineInstr(const MachineInstr &MI) {
285 TID = MI.getInstrDescriptor();
286 NumImplicitOps = MI.NumImplicitOps;
287 Operands.reserve(MI.getNumOperands());
290 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
291 Operands.push_back(MI.getOperand(i));
292 Operands.back().ParentMI = this;
295 // Set parent, next, and prev to null
302 MachineInstr::~MachineInstr() {
303 LeakDetector::removeGarbageObject(this);
305 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
306 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
307 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
308 "Reg operand def/use list corrupted");
313 /// getOpcode - Returns the opcode of this MachineInstr.
315 int MachineInstr::getOpcode() const {
319 /// getRegInfo - If this instruction is embedded into a MachineFunction,
320 /// return the MachineRegisterInfo object for the current function, otherwise
322 MachineRegisterInfo *MachineInstr::getRegInfo() {
323 if (MachineBasicBlock *MBB = getParent())
324 if (MachineFunction *MF = MBB->getParent())
325 return &MF->getRegInfo();
329 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
330 /// this instruction from their respective use lists. This requires that the
331 /// operands already be on their use lists.
332 void MachineInstr::RemoveRegOperandsFromUseLists() {
333 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
334 if (Operands[i].isReg())
335 Operands[i].RemoveRegOperandFromRegInfo();
339 /// AddRegOperandsToUseLists - Add all of the register operands in
340 /// this instruction from their respective use lists. This requires that the
341 /// operands not be on their use lists yet.
342 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
343 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
344 if (Operands[i].isReg())
345 Operands[i].AddRegOperandToRegInfo(&RegInfo);
350 /// addOperand - Add the specified operand to the instruction. If it is an
351 /// implicit operand, it is added to the end of the operand list. If it is
352 /// an explicit operand it is added at the end of the explicit operand list
353 /// (before the first implicit operand).
354 void MachineInstr::addOperand(const MachineOperand &Op) {
355 bool isImpReg = Op.isReg() && Op.isImplicit();
356 assert((isImpReg || !OperandsComplete()) &&
357 "Trying to add an operand to a machine instr that is already done!");
359 // If we are adding the operand to the end of the list, our job is simpler.
360 // This is true most of the time, so this is a reasonable optimization.
361 if (isImpReg || NumImplicitOps == 0) {
362 // We can only do this optimization if we know that the operand list won't
364 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
365 Operands.push_back(Op);
367 // Set the parent of the operand.
368 Operands.back().ParentMI = this;
370 // If the operand is a register, update the operand's use list.
372 Operands.back().AddRegOperandToRegInfo(getRegInfo());
377 // Otherwise, we have to insert a real operand before any implicit ones.
378 unsigned OpNo = Operands.size()-NumImplicitOps;
380 MachineRegisterInfo *RegInfo = getRegInfo();
382 // If this instruction isn't embedded into a function, then we don't need to
383 // update any operand lists.
385 // Simple insertion, no reginfo update needed for other register operands.
386 Operands.insert(Operands.begin()+OpNo, Op);
387 Operands[OpNo].ParentMI = this;
389 // Do explicitly set the reginfo for this operand though, to ensure the
390 // next/prev fields are properly nulled out.
391 if (Operands[OpNo].isReg())
392 Operands[OpNo].AddRegOperandToRegInfo(0);
394 } else if (Operands.size()+1 <= Operands.capacity()) {
395 // Otherwise, we have to remove register operands from their register use
396 // list, add the operand, then add the register operands back to their use
397 // list. This also must handle the case when the operand list reallocates
398 // to somewhere else.
400 // If insertion of this operand won't cause reallocation of the operand
401 // list, just remove the implicit operands, add the operand, then re-add all
402 // the rest of the operands.
403 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
404 assert(Operands[i].isReg() && "Should only be an implicit reg!");
405 Operands[i].RemoveRegOperandFromRegInfo();
408 // Add the operand. If it is a register, add it to the reg list.
409 Operands.insert(Operands.begin()+OpNo, Op);
410 Operands[OpNo].ParentMI = this;
412 if (Operands[OpNo].isReg())
413 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
415 // Re-add all the implicit ops.
416 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
417 assert(Operands[i].isReg() && "Should only be an implicit reg!");
418 Operands[i].AddRegOperandToRegInfo(RegInfo);
421 // Otherwise, we will be reallocating the operand list. Remove all reg
422 // operands from their list, then readd them after the operand list is
424 RemoveRegOperandsFromUseLists();
426 Operands.insert(Operands.begin()+OpNo, Op);
427 Operands[OpNo].ParentMI = this;
429 // Re-add all the operands.
430 AddRegOperandsToUseLists(*RegInfo);
434 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
435 /// fewer operand than it started with.
437 void MachineInstr::RemoveOperand(unsigned OpNo) {
438 assert(OpNo < Operands.size() && "Invalid operand number");
440 // Special case removing the last one.
441 if (OpNo == Operands.size()-1) {
442 // If needed, remove from the reg def/use list.
443 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
444 Operands.back().RemoveRegOperandFromRegInfo();
450 // Otherwise, we are removing an interior operand. If we have reginfo to
451 // update, remove all operands that will be shifted down from their reg lists,
452 // move everything down, then re-add them.
453 MachineRegisterInfo *RegInfo = getRegInfo();
455 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
456 if (Operands[i].isReg())
457 Operands[i].RemoveRegOperandFromRegInfo();
461 Operands.erase(Operands.begin()+OpNo);
464 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
465 if (Operands[i].isReg())
466 Operands[i].AddRegOperandToRegInfo(RegInfo);
472 /// removeFromParent - This method unlinks 'this' from the containing basic
473 /// block, and returns it, but does not delete it.
474 MachineInstr *MachineInstr::removeFromParent() {
475 assert(getParent() && "Not embedded in a basic block!");
476 getParent()->remove(this);
481 /// OperandComplete - Return true if it's illegal to add a new operand
483 bool MachineInstr::OperandsComplete() const {
484 unsigned short NumOperands = TID->numOperands;
485 if ((TID->Flags & M_VARIABLE_OPS) == 0 &&
486 getNumOperands()-NumImplicitOps >= NumOperands)
487 return true; // Broken: we have all the operands of this instruction!
491 /// getNumExplicitOperands - Returns the number of non-implicit operands.
493 unsigned MachineInstr::getNumExplicitOperands() const {
494 unsigned NumOperands = TID->numOperands;
495 if ((TID->Flags & M_VARIABLE_OPS) == 0)
498 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
499 const MachineOperand &MO = getOperand(NumOperands);
500 if (!MO.isRegister() || !MO.isImplicit())
507 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
508 /// the specific register or -1 if it is not found. It further tightening
509 /// the search criteria to a use that kills the register if isKill is true.
510 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
511 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
512 const MachineOperand &MO = getOperand(i);
513 if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
514 if (!isKill || MO.isKill())
520 /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
521 /// the specific register or NULL if it is not found.
522 MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
523 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
524 MachineOperand &MO = getOperand(i);
525 if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
531 /// findFirstPredOperandIdx() - Find the index of the first operand in the
532 /// operand list that is used to represent the predicate. It returns -1 if
534 int MachineInstr::findFirstPredOperandIdx() const {
535 const TargetInstrDescriptor *TID = getInstrDescriptor();
536 if (TID->Flags & M_PREDICABLE) {
537 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
538 if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
545 /// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
546 /// to two addr elimination.
547 bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
548 const TargetInstrDescriptor *TID = getInstrDescriptor();
549 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
550 const MachineOperand &MO1 = getOperand(i);
551 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
552 for (unsigned j = i+1; j < e; ++j) {
553 const MachineOperand &MO2 = getOperand(j);
554 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
555 TID->getOperandConstraint(j, TOI::TIED_TO) == (int)i)
563 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
565 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
566 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
567 const MachineOperand &MO = MI->getOperand(i);
568 if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
570 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
571 MachineOperand &MOp = getOperand(j);
572 if (!MOp.isIdenticalTo(MO))
583 /// copyPredicates - Copies predicate operand(s) from MI.
584 void MachineInstr::copyPredicates(const MachineInstr *MI) {
585 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
586 if (TID->Flags & M_PREDICABLE) {
587 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
588 if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
589 // Predicated operands must be last operands.
590 addOperand(MI->getOperand(i));
596 void MachineInstr::dump() const {
597 cerr << " " << *this;
600 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
601 // Specialize printing if op#0 is definition
602 unsigned StartOp = 0;
603 if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
604 getOperand(0).print(OS, TM);
606 ++StartOp; // Don't print this operand again!
609 OS << getInstrDescriptor()->Name;
611 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
615 getOperand(i).print(OS, TM);