1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Function.h"
17 #include "llvm/InlineAsm.h"
18 #include "llvm/Type.h"
19 #include "llvm/Value.h"
20 #include "llvm/Assembly/Writer.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetInstrDesc.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 #include "llvm/Analysis/AliasAnalysis.h"
31 #include "llvm/Analysis/DebugInfo.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/LeakDetector.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/ADT/FoldingSet.h"
38 #include "llvm/Metadata.h"
41 //===----------------------------------------------------------------------===//
42 // MachineOperand Implementation
43 //===----------------------------------------------------------------------===//
45 /// AddRegOperandToRegInfo - Add this register operand to the specified
46 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
47 /// explicitly nulled out.
48 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
49 assert(isReg() && "Can only add reg operand to use lists");
51 // If the reginfo pointer is null, just explicitly null out or next/prev
52 // pointers, to ensure they are not garbage.
54 Contents.Reg.Prev = 0;
55 Contents.Reg.Next = 0;
59 // Otherwise, add this operand to the head of the registers use/def list.
60 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
62 // For SSA values, we prefer to keep the definition at the start of the list.
63 // we do this by skipping over the definition if it is at the head of the
65 if (*Head && (*Head)->isDef())
66 Head = &(*Head)->Contents.Reg.Next;
68 Contents.Reg.Next = *Head;
69 if (Contents.Reg.Next) {
70 assert(getReg() == Contents.Reg.Next->getReg() &&
71 "Different regs on the same list!");
72 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
75 Contents.Reg.Prev = Head;
79 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
80 /// MachineRegisterInfo it is linked with.
81 void MachineOperand::RemoveRegOperandFromRegInfo() {
82 assert(isOnRegUseList() && "Reg operand is not on a use list");
83 // Unlink this from the doubly linked list of operands.
84 MachineOperand *NextOp = Contents.Reg.Next;
85 *Contents.Reg.Prev = NextOp;
87 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
88 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
90 Contents.Reg.Prev = 0;
91 Contents.Reg.Next = 0;
94 void MachineOperand::setReg(unsigned Reg) {
95 if (getReg() == Reg) return; // No change.
97 // Otherwise, we have to change the register. If this operand is embedded
98 // into a machine function, we need to update the old and new register's
100 if (MachineInstr *MI = getParent())
101 if (MachineBasicBlock *MBB = MI->getParent())
102 if (MachineFunction *MF = MBB->getParent()) {
103 RemoveRegOperandFromRegInfo();
104 Contents.Reg.RegNo = Reg;
105 AddRegOperandToRegInfo(&MF->getRegInfo());
109 // Otherwise, just change the register, no problem. :)
110 Contents.Reg.RegNo = Reg;
113 /// ChangeToImmediate - Replace this operand with a new immediate operand of
114 /// the specified value. If an operand is known to be an immediate already,
115 /// the setImm method should be used.
116 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
117 // If this operand is currently a register operand, and if this is in a
118 // function, deregister the operand from the register's use/def list.
119 if (isReg() && getParent() && getParent()->getParent() &&
120 getParent()->getParent()->getParent())
121 RemoveRegOperandFromRegInfo();
123 OpKind = MO_Immediate;
124 Contents.ImmVal = ImmVal;
127 /// ChangeToRegister - Replace this operand with a new register operand of
128 /// the specified value. If an operand is known to be an register already,
129 /// the setReg method should be used.
130 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
131 bool isKill, bool isDead, bool isUndef,
133 // If this operand is already a register operand, use setReg to update the
134 // register's use/def lists.
136 assert(!isEarlyClobber());
139 // Otherwise, change this to a register and set the reg#.
140 OpKind = MO_Register;
141 Contents.Reg.RegNo = Reg;
143 // If this operand is embedded in a function, add the operand to the
144 // register's use/def list.
145 if (MachineInstr *MI = getParent())
146 if (MachineBasicBlock *MBB = MI->getParent())
147 if (MachineFunction *MF = MBB->getParent())
148 AddRegOperandToRegInfo(&MF->getRegInfo());
156 IsEarlyClobber = false;
161 /// isIdenticalTo - Return true if this operand is identical to the specified
163 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
164 if (getType() != Other.getType() ||
165 getTargetFlags() != Other.getTargetFlags())
169 default: llvm_unreachable("Unrecognized operand type");
170 case MachineOperand::MO_Register:
171 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
172 getSubReg() == Other.getSubReg();
173 case MachineOperand::MO_Immediate:
174 return getImm() == Other.getImm();
175 case MachineOperand::MO_FPImmediate:
176 return getFPImm() == Other.getFPImm();
177 case MachineOperand::MO_MachineBasicBlock:
178 return getMBB() == Other.getMBB();
179 case MachineOperand::MO_FrameIndex:
180 return getIndex() == Other.getIndex();
181 case MachineOperand::MO_ConstantPoolIndex:
182 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
183 case MachineOperand::MO_JumpTableIndex:
184 return getIndex() == Other.getIndex();
185 case MachineOperand::MO_GlobalAddress:
186 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
187 case MachineOperand::MO_ExternalSymbol:
188 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
189 getOffset() == Other.getOffset();
190 case MachineOperand::MO_BlockAddress:
191 return getBlockAddress() == Other.getBlockAddress();
195 /// print - Print the specified machine operand.
197 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
198 // If the instruction is embedded into a basic block, we can find the
199 // target info for the instruction.
201 if (const MachineInstr *MI = getParent())
202 if (const MachineBasicBlock *MBB = MI->getParent())
203 if (const MachineFunction *MF = MBB->getParent())
204 TM = &MF->getTarget();
207 case MachineOperand::MO_Register:
208 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
209 OS << "%reg" << getReg();
212 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
214 OS << "%physreg" << getReg();
217 if (getSubReg() != 0)
218 OS << ':' << getSubReg();
220 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
223 bool NeedComma = false;
225 if (NeedComma) OS << ',';
226 if (isEarlyClobber())
227 OS << "earlyclobber,";
232 } else if (isImplicit()) {
237 if (isKill() || isDead() || isUndef()) {
238 if (NeedComma) OS << ',';
239 if (isKill()) OS << "kill";
240 if (isDead()) OS << "dead";
242 if (isKill() || isDead())
250 case MachineOperand::MO_Immediate:
253 case MachineOperand::MO_FPImmediate:
254 if (getFPImm()->getType()->isFloatTy())
255 OS << getFPImm()->getValueAPF().convertToFloat();
257 OS << getFPImm()->getValueAPF().convertToDouble();
259 case MachineOperand::MO_MachineBasicBlock:
260 OS << "<BB#" << getMBB()->getNumber() << ">";
262 case MachineOperand::MO_FrameIndex:
263 OS << "<fi#" << getIndex() << '>';
265 case MachineOperand::MO_ConstantPoolIndex:
266 OS << "<cp#" << getIndex();
267 if (getOffset()) OS << "+" << getOffset();
270 case MachineOperand::MO_JumpTableIndex:
271 OS << "<jt#" << getIndex() << '>';
273 case MachineOperand::MO_GlobalAddress:
275 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
276 if (getOffset()) OS << "+" << getOffset();
279 case MachineOperand::MO_ExternalSymbol:
280 OS << "<es:" << getSymbolName();
281 if (getOffset()) OS << "+" << getOffset();
284 case MachineOperand::MO_BlockAddress:
286 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
289 case MachineOperand::MO_Metadata:
291 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
295 llvm_unreachable("Unrecognized operand type");
298 if (unsigned TF = getTargetFlags())
299 OS << "[TF=" << TF << ']';
302 //===----------------------------------------------------------------------===//
303 // MachineMemOperand Implementation
304 //===----------------------------------------------------------------------===//
306 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
307 int64_t o, uint64_t s, unsigned int a)
308 : Offset(o), Size(s), V(v),
309 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)) {
310 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
311 assert((isLoad() || isStore()) && "Not a load/store!");
314 /// Profile - Gather unique data for the object.
316 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
317 ID.AddInteger(Offset);
320 ID.AddInteger(Flags);
323 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
324 // The Value and Offset may differ due to CSE. But the flags and size
325 // should be the same.
326 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
327 assert(MMO->getSize() == getSize() && "Size mismatch!");
329 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
330 // Update the alignment value.
331 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
332 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
333 // Also update the base and offset, because the new alignment may
334 // not be applicable with the old ones.
336 Offset = MMO->getOffset();
340 /// getAlignment - Return the minimum known alignment in bytes of the
341 /// actual memory reference.
342 uint64_t MachineMemOperand::getAlignment() const {
343 return MinAlign(getBaseAlignment(), getOffset());
346 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
347 assert((MMO.isLoad() || MMO.isStore()) &&
348 "SV has to be a load, store or both.");
350 if (MMO.isVolatile())
359 // Print the address information.
364 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
366 // If the alignment of the memory reference itself differs from the alignment
367 // of the base pointer, print the base alignment explicitly, next to the base
369 if (MMO.getBaseAlignment() != MMO.getAlignment())
370 OS << "(align=" << MMO.getBaseAlignment() << ")";
372 if (MMO.getOffset() != 0)
373 OS << "+" << MMO.getOffset();
376 // Print the alignment of the reference.
377 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
378 MMO.getBaseAlignment() != MMO.getSize())
379 OS << "(align=" << MMO.getAlignment() << ")";
384 //===----------------------------------------------------------------------===//
385 // MachineInstr Implementation
386 //===----------------------------------------------------------------------===//
388 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
389 /// TID NULL and no operands.
390 MachineInstr::MachineInstr()
391 : TID(0), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
392 Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
393 // Make sure that we get added to a machine basicblock
394 LeakDetector::addGarbageObject(this);
397 void MachineInstr::addImplicitDefUseOperands() {
398 if (TID->ImplicitDefs)
399 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
400 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
401 if (TID->ImplicitUses)
402 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
403 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
406 /// MachineInstr ctor - This constructor create a MachineInstr and add the
407 /// implicit operands. It reserves space for number of operands specified by
408 /// TargetInstrDesc or the numOperands if it is not zero. (for
409 /// instructions with variable number of operands).
410 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
411 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
412 MemRefs(0), MemRefsEnd(0), Parent(0),
413 debugLoc(DebugLoc::getUnknownLoc()) {
414 if (!NoImp && TID->getImplicitDefs())
415 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
417 if (!NoImp && TID->getImplicitUses())
418 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
420 Operands.reserve(NumImplicitOps + TID->getNumOperands());
422 addImplicitDefUseOperands();
423 // Make sure that we get added to a machine basicblock
424 LeakDetector::addGarbageObject(this);
427 /// MachineInstr ctor - As above, but with a DebugLoc.
428 MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
430 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
431 Parent(0), debugLoc(dl) {
432 if (!NoImp && TID->getImplicitDefs())
433 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
435 if (!NoImp && TID->getImplicitUses())
436 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
438 Operands.reserve(NumImplicitOps + TID->getNumOperands());
440 addImplicitDefUseOperands();
441 // Make sure that we get added to a machine basicblock
442 LeakDetector::addGarbageObject(this);
445 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
446 /// that the MachineInstr is created and added to the end of the specified
449 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
450 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
451 MemRefs(0), MemRefsEnd(0), Parent(0),
452 debugLoc(DebugLoc::getUnknownLoc()) {
453 assert(MBB && "Cannot use inserting ctor with null basic block!");
454 if (TID->ImplicitDefs)
455 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
457 if (TID->ImplicitUses)
458 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
460 Operands.reserve(NumImplicitOps + TID->getNumOperands());
461 addImplicitDefUseOperands();
462 // Make sure that we get added to a machine basicblock
463 LeakDetector::addGarbageObject(this);
464 MBB->push_back(this); // Add instruction to end of basic block!
467 /// MachineInstr ctor - As above, but with a DebugLoc.
469 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
470 const TargetInstrDesc &tid)
471 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
472 Parent(0), debugLoc(dl) {
473 assert(MBB && "Cannot use inserting ctor with null basic block!");
474 if (TID->ImplicitDefs)
475 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
477 if (TID->ImplicitUses)
478 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
480 Operands.reserve(NumImplicitOps + TID->getNumOperands());
481 addImplicitDefUseOperands();
482 // Make sure that we get added to a machine basicblock
483 LeakDetector::addGarbageObject(this);
484 MBB->push_back(this); // Add instruction to end of basic block!
487 /// MachineInstr ctor - Copies MachineInstr arg exactly
489 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
490 : TID(&MI.getDesc()), NumImplicitOps(0), AsmPrinterFlags(0),
491 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
492 Parent(0), debugLoc(MI.getDebugLoc()) {
493 Operands.reserve(MI.getNumOperands());
496 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
497 addOperand(MI.getOperand(i));
498 NumImplicitOps = MI.NumImplicitOps;
500 // Set parent to null.
503 LeakDetector::addGarbageObject(this);
506 MachineInstr::~MachineInstr() {
507 LeakDetector::removeGarbageObject(this);
509 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
510 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
511 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
512 "Reg operand def/use list corrupted");
517 /// getRegInfo - If this instruction is embedded into a MachineFunction,
518 /// return the MachineRegisterInfo object for the current function, otherwise
520 MachineRegisterInfo *MachineInstr::getRegInfo() {
521 if (MachineBasicBlock *MBB = getParent())
522 return &MBB->getParent()->getRegInfo();
526 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
527 /// this instruction from their respective use lists. This requires that the
528 /// operands already be on their use lists.
529 void MachineInstr::RemoveRegOperandsFromUseLists() {
530 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
531 if (Operands[i].isReg())
532 Operands[i].RemoveRegOperandFromRegInfo();
536 /// AddRegOperandsToUseLists - Add all of the register operands in
537 /// this instruction from their respective use lists. This requires that the
538 /// operands not be on their use lists yet.
539 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
540 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
541 if (Operands[i].isReg())
542 Operands[i].AddRegOperandToRegInfo(&RegInfo);
547 /// addOperand - Add the specified operand to the instruction. If it is an
548 /// implicit operand, it is added to the end of the operand list. If it is
549 /// an explicit operand it is added at the end of the explicit operand list
550 /// (before the first implicit operand).
551 void MachineInstr::addOperand(const MachineOperand &Op) {
552 bool isImpReg = Op.isReg() && Op.isImplicit();
553 assert((isImpReg || !OperandsComplete()) &&
554 "Trying to add an operand to a machine instr that is already done!");
556 MachineRegisterInfo *RegInfo = getRegInfo();
558 // If we are adding the operand to the end of the list, our job is simpler.
559 // This is true most of the time, so this is a reasonable optimization.
560 if (isImpReg || NumImplicitOps == 0) {
561 // We can only do this optimization if we know that the operand list won't
563 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
564 Operands.push_back(Op);
566 // Set the parent of the operand.
567 Operands.back().ParentMI = this;
569 // If the operand is a register, update the operand's use list.
571 Operands.back().AddRegOperandToRegInfo(RegInfo);
572 // If the register operand is flagged as early, mark the operand as such
573 unsigned OpNo = Operands.size() - 1;
574 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
575 Operands[OpNo].setIsEarlyClobber(true);
581 // Otherwise, we have to insert a real operand before any implicit ones.
582 unsigned OpNo = Operands.size()-NumImplicitOps;
584 // If this instruction isn't embedded into a function, then we don't need to
585 // update any operand lists.
587 // Simple insertion, no reginfo update needed for other register operands.
588 Operands.insert(Operands.begin()+OpNo, Op);
589 Operands[OpNo].ParentMI = this;
591 // Do explicitly set the reginfo for this operand though, to ensure the
592 // next/prev fields are properly nulled out.
593 if (Operands[OpNo].isReg()) {
594 Operands[OpNo].AddRegOperandToRegInfo(0);
595 // If the register operand is flagged as early, mark the operand as such
596 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
597 Operands[OpNo].setIsEarlyClobber(true);
600 } else if (Operands.size()+1 <= Operands.capacity()) {
601 // Otherwise, we have to remove register operands from their register use
602 // list, add the operand, then add the register operands back to their use
603 // list. This also must handle the case when the operand list reallocates
604 // to somewhere else.
606 // If insertion of this operand won't cause reallocation of the operand
607 // list, just remove the implicit operands, add the operand, then re-add all
608 // the rest of the operands.
609 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
610 assert(Operands[i].isReg() && "Should only be an implicit reg!");
611 Operands[i].RemoveRegOperandFromRegInfo();
614 // Add the operand. If it is a register, add it to the reg list.
615 Operands.insert(Operands.begin()+OpNo, Op);
616 Operands[OpNo].ParentMI = this;
618 if (Operands[OpNo].isReg()) {
619 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
620 // If the register operand is flagged as early, mark the operand as such
621 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
622 Operands[OpNo].setIsEarlyClobber(true);
625 // Re-add all the implicit ops.
626 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
627 assert(Operands[i].isReg() && "Should only be an implicit reg!");
628 Operands[i].AddRegOperandToRegInfo(RegInfo);
631 // Otherwise, we will be reallocating the operand list. Remove all reg
632 // operands from their list, then readd them after the operand list is
634 RemoveRegOperandsFromUseLists();
636 Operands.insert(Operands.begin()+OpNo, Op);
637 Operands[OpNo].ParentMI = this;
639 // Re-add all the operands.
640 AddRegOperandsToUseLists(*RegInfo);
642 // If the register operand is flagged as early, mark the operand as such
643 if (Operands[OpNo].isReg()
644 && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
645 Operands[OpNo].setIsEarlyClobber(true);
649 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
650 /// fewer operand than it started with.
652 void MachineInstr::RemoveOperand(unsigned OpNo) {
653 assert(OpNo < Operands.size() && "Invalid operand number");
655 // Special case removing the last one.
656 if (OpNo == Operands.size()-1) {
657 // If needed, remove from the reg def/use list.
658 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
659 Operands.back().RemoveRegOperandFromRegInfo();
665 // Otherwise, we are removing an interior operand. If we have reginfo to
666 // update, remove all operands that will be shifted down from their reg lists,
667 // move everything down, then re-add them.
668 MachineRegisterInfo *RegInfo = getRegInfo();
670 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
671 if (Operands[i].isReg())
672 Operands[i].RemoveRegOperandFromRegInfo();
676 Operands.erase(Operands.begin()+OpNo);
679 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
680 if (Operands[i].isReg())
681 Operands[i].AddRegOperandToRegInfo(RegInfo);
686 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
687 /// This function should be used only occasionally. The setMemRefs function
688 /// is the primary method for setting up a MachineInstr's MemRefs list.
689 void MachineInstr::addMemOperand(MachineFunction &MF,
690 MachineMemOperand *MO) {
691 mmo_iterator OldMemRefs = MemRefs;
692 mmo_iterator OldMemRefsEnd = MemRefsEnd;
694 size_t NewNum = (MemRefsEnd - MemRefs) + 1;
695 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
696 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
698 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
699 NewMemRefs[NewNum - 1] = MO;
701 MemRefs = NewMemRefs;
702 MemRefsEnd = NewMemRefsEnd;
705 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
706 MICheckType Check) const {
707 // If opcodes or number of operands are not the same then the two
708 // instructions are obviously not identical.
709 if (Other->getOpcode() != getOpcode() ||
710 Other->getNumOperands() != getNumOperands())
713 // Check operands to make sure they match.
714 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
715 const MachineOperand &MO = getOperand(i);
716 const MachineOperand &OMO = Other->getOperand(i);
717 // Clients may or may not want to ignore defs when testing for equality.
718 // For example, machine CSE pass only cares about finding common
719 // subexpressions, so it's safe to ignore virtual register defs.
720 if (Check != CheckDefs && MO.isReg() && MO.isDef()) {
721 if (Check == IgnoreDefs)
723 // Check == IgnoreVRegDefs
724 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
725 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
726 if (MO.getReg() != OMO.getReg())
728 } else if (!MO.isIdenticalTo(OMO))
734 /// removeFromParent - This method unlinks 'this' from the containing basic
735 /// block, and returns it, but does not delete it.
736 MachineInstr *MachineInstr::removeFromParent() {
737 assert(getParent() && "Not embedded in a basic block!");
738 getParent()->remove(this);
743 /// eraseFromParent - This method unlinks 'this' from the containing basic
744 /// block, and deletes it.
745 void MachineInstr::eraseFromParent() {
746 assert(getParent() && "Not embedded in a basic block!");
747 getParent()->erase(this);
751 /// OperandComplete - Return true if it's illegal to add a new operand
753 bool MachineInstr::OperandsComplete() const {
754 unsigned short NumOperands = TID->getNumOperands();
755 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
756 return true; // Broken: we have all the operands of this instruction!
760 /// getNumExplicitOperands - Returns the number of non-implicit operands.
762 unsigned MachineInstr::getNumExplicitOperands() const {
763 unsigned NumOperands = TID->getNumOperands();
764 if (!TID->isVariadic())
767 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
768 const MachineOperand &MO = getOperand(i);
769 if (!MO.isReg() || !MO.isImplicit())
776 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
777 /// the specific register or -1 if it is not found. It further tightens
778 /// the search criteria to a use that kills the register if isKill is true.
779 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
780 const TargetRegisterInfo *TRI) const {
781 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
782 const MachineOperand &MO = getOperand(i);
783 if (!MO.isReg() || !MO.isUse())
785 unsigned MOReg = MO.getReg();
790 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
791 TargetRegisterInfo::isPhysicalRegister(Reg) &&
792 TRI->isSubRegister(MOReg, Reg)))
793 if (!isKill || MO.isKill())
799 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
800 /// the specified register or -1 if it is not found. If isDead is true, defs
801 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
802 /// also checks if there is a def of a super-register.
803 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
804 const TargetRegisterInfo *TRI) const {
805 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
806 const MachineOperand &MO = getOperand(i);
807 if (!MO.isReg() || !MO.isDef())
809 unsigned MOReg = MO.getReg();
812 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
813 TargetRegisterInfo::isPhysicalRegister(Reg) &&
814 TRI->isSubRegister(MOReg, Reg)))
815 if (!isDead || MO.isDead())
821 /// findFirstPredOperandIdx() - Find the index of the first operand in the
822 /// operand list that is used to represent the predicate. It returns -1 if
824 int MachineInstr::findFirstPredOperandIdx() const {
825 const TargetInstrDesc &TID = getDesc();
826 if (TID.isPredicable()) {
827 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
828 if (TID.OpInfo[i].isPredicate())
835 /// isRegTiedToUseOperand - Given the index of a register def operand,
836 /// check if the register def is tied to a source operand, due to either
837 /// two-address elimination or inline assembly constraints. Returns the
838 /// first tied use operand index by reference is UseOpIdx is not null.
840 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
842 assert(DefOpIdx >= 2);
843 const MachineOperand &MO = getOperand(DefOpIdx);
844 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
846 // Determine the actual operand index that corresponds to this index.
848 unsigned DefPart = 0;
849 for (unsigned i = 1, e = getNumOperands(); i < e; ) {
850 const MachineOperand &FMO = getOperand(i);
851 // After the normal asm operands there may be additional imp-def regs.
854 // Skip over this def.
855 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
856 unsigned PrevDef = i + 1;
857 i = PrevDef + NumOps;
859 DefPart = DefOpIdx - PrevDef;
864 for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
865 const MachineOperand &FMO = getOperand(i);
868 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
871 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
874 *UseOpIdx = (unsigned)i + 1 + DefPart;
881 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
882 const TargetInstrDesc &TID = getDesc();
883 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
884 const MachineOperand &MO = getOperand(i);
885 if (MO.isReg() && MO.isUse() &&
886 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
888 *UseOpIdx = (unsigned)i;
895 /// isRegTiedToDefOperand - Return true if the operand of the specified index
896 /// is a register use and it is tied to an def operand. It also returns the def
897 /// operand index by reference.
899 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
901 const MachineOperand &MO = getOperand(UseOpIdx);
902 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
905 // Find the flag operand corresponding to UseOpIdx
906 unsigned FlagIdx, NumOps=0;
907 for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
908 const MachineOperand &UFMO = getOperand(FlagIdx);
909 // After the normal asm operands there may be additional imp-def regs.
912 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
913 assert(NumOps < getNumOperands() && "Invalid inline asm flag");
914 if (UseOpIdx < FlagIdx+NumOps+1)
917 if (FlagIdx >= UseOpIdx)
919 const MachineOperand &UFMO = getOperand(FlagIdx);
921 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
926 // Remember to adjust the index. First operand is asm string, then there
927 // is a flag for each.
929 const MachineOperand &FMO = getOperand(DefIdx);
931 // Skip over this def.
932 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
935 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
941 const TargetInstrDesc &TID = getDesc();
942 if (UseOpIdx >= TID.getNumOperands())
944 const MachineOperand &MO = getOperand(UseOpIdx);
945 if (!MO.isReg() || !MO.isUse())
947 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
951 *DefOpIdx = (unsigned)DefIdx;
955 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
957 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
958 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
959 const MachineOperand &MO = MI->getOperand(i);
960 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
962 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
963 MachineOperand &MOp = getOperand(j);
964 if (!MOp.isIdenticalTo(MO))
975 /// copyPredicates - Copies predicate operand(s) from MI.
976 void MachineInstr::copyPredicates(const MachineInstr *MI) {
977 const TargetInstrDesc &TID = MI->getDesc();
978 if (!TID.isPredicable())
980 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
981 if (TID.OpInfo[i].isPredicate()) {
982 // Predicated operands must be last operands.
983 addOperand(MI->getOperand(i));
988 /// isSafeToMove - Return true if it is safe to move this instruction. If
989 /// SawStore is set to true, it means that there is a store (or call) between
990 /// the instruction's location and its intended destination.
991 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
993 bool &SawStore) const {
994 // Ignore stuff that we obviously can't move.
995 if (TID->mayStore() || TID->isCall()) {
999 if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
1002 // See if this instruction does a load. If so, we have to guarantee that the
1003 // loaded value doesn't change between the load and the its intended
1004 // destination. The check for isInvariantLoad gives the targe the chance to
1005 // classify the load as always returning a constant, e.g. a constant pool
1007 if (TID->mayLoad() && !isInvariantLoad(AA))
1008 // Otherwise, this is a real load. If there is a store between the load and
1009 // end of block, or if the load is volatile, we can't move it.
1010 return !SawStore && !hasVolatileMemoryRef();
1015 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1016 /// instruction which defined the specified register instead of copying it.
1017 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1019 unsigned DstReg) const {
1020 bool SawStore = false;
1021 if (!TII->isTriviallyReMaterializable(this, AA) ||
1022 !isSafeToMove(TII, AA, SawStore))
1024 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1025 const MachineOperand &MO = getOperand(i);
1028 // FIXME: For now, do not remat any instruction with register operands.
1029 // Later on, we can loosen the restriction is the register operands have
1030 // not been modified between the def and use. Note, this is different from
1031 // MachineSink because the code is no longer in two-address form (at least
1035 else if (!MO.isDead() && MO.getReg() != DstReg)
1041 /// hasVolatileMemoryRef - Return true if this instruction may have a
1042 /// volatile memory reference, or if the information describing the
1043 /// memory reference is not available. Return false if it is known to
1044 /// have no volatile memory references.
1045 bool MachineInstr::hasVolatileMemoryRef() const {
1046 // An instruction known never to access memory won't have a volatile access.
1047 if (!TID->mayStore() &&
1050 !TID->hasUnmodeledSideEffects())
1053 // Otherwise, if the instruction has no memory reference information,
1054 // conservatively assume it wasn't preserved.
1055 if (memoperands_empty())
1058 // Check the memory reference information for volatile references.
1059 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1060 if ((*I)->isVolatile())
1066 /// isInvariantLoad - Return true if this instruction is loading from a
1067 /// location whose value is invariant across the function. For example,
1068 /// loading a value from the constant pool or from the argument area
1069 /// of a function if it does not change. This should only return true of
1070 /// *all* loads the instruction does are invariant (if it does multiple loads).
1071 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1072 // If the instruction doesn't load at all, it isn't an invariant load.
1073 if (!TID->mayLoad())
1076 // If the instruction has lost its memoperands, conservatively assume that
1077 // it may not be an invariant load.
1078 if (memoperands_empty())
1081 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1083 for (mmo_iterator I = memoperands_begin(),
1084 E = memoperands_end(); I != E; ++I) {
1085 if ((*I)->isVolatile()) return false;
1086 if ((*I)->isStore()) return false;
1088 if (const Value *V = (*I)->getValue()) {
1089 // A load from a constant PseudoSourceValue is invariant.
1090 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1091 if (PSV->isConstant(MFI))
1093 // If we have an AliasAnalysis, ask it whether the memory is constant.
1094 if (AA && AA->pointsToConstantMemory(V))
1098 // Otherwise assume conservatively.
1102 // Everything checks out.
1106 /// isConstantValuePHI - If the specified instruction is a PHI that always
1107 /// merges together the same virtual register, return the register, otherwise
1109 unsigned MachineInstr::isConstantValuePHI() const {
1112 assert(getNumOperands() >= 3 &&
1113 "It's illegal to have a PHI without source operands");
1115 unsigned Reg = getOperand(1).getReg();
1116 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1117 if (getOperand(i).getReg() != Reg)
1122 void MachineInstr::dump() const {
1123 dbgs() << " " << *this;
1126 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1127 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1128 const MachineFunction *MF = 0;
1129 if (const MachineBasicBlock *MBB = getParent()) {
1130 MF = MBB->getParent();
1132 TM = &MF->getTarget();
1135 // Print explicitly defined operands on the left of an assignment syntax.
1136 unsigned StartOp = 0, e = getNumOperands();
1137 for (; StartOp < e && getOperand(StartOp).isReg() &&
1138 getOperand(StartOp).isDef() &&
1139 !getOperand(StartOp).isImplicit();
1141 if (StartOp != 0) OS << ", ";
1142 getOperand(StartOp).print(OS, TM);
1148 // Print the opcode name.
1149 OS << getDesc().getName();
1151 // Print the rest of the operands.
1152 bool OmittedAnyCallClobbers = false;
1153 bool FirstOp = true;
1154 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1155 const MachineOperand &MO = getOperand(i);
1157 // Omit call-clobbered registers which aren't used anywhere. This makes
1158 // call instructions much less noisy on targets where calls clobber lots
1159 // of registers. Don't rely on MO.isDead() because we may be called before
1160 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1161 if (MF && getDesc().isCall() &&
1162 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1163 unsigned Reg = MO.getReg();
1164 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
1165 const MachineRegisterInfo &MRI = MF->getRegInfo();
1166 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1167 bool HasAliasLive = false;
1168 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1169 unsigned AliasReg = *Alias; ++Alias)
1170 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1171 HasAliasLive = true;
1174 if (!HasAliasLive) {
1175 OmittedAnyCallClobbers = true;
1182 if (FirstOp) FirstOp = false; else OS << ",";
1184 if (i < getDesc().NumOperands) {
1185 const TargetOperandInfo &TOI = getDesc().OpInfo[i];
1186 if (TOI.isPredicate())
1188 if (TOI.isOptionalDef())
1194 // Briefly indicate whether any call clobbers were omitted.
1195 if (OmittedAnyCallClobbers) {
1196 if (!FirstOp) OS << ",";
1200 bool HaveSemi = false;
1201 if (!memoperands_empty()) {
1202 if (!HaveSemi) OS << ";"; HaveSemi = true;
1205 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1213 if (!debugLoc.isUnknown() && MF) {
1214 if (!HaveSemi) OS << ";";
1216 // TODO: print InlinedAtLoc information
1218 DILocation DLT = MF->getDILocation(debugLoc);
1219 DIScope Scope = DLT.getScope();
1221 // Omit the directory, since it's usually long and uninteresting.
1223 OS << Scope.getFilename();
1226 OS << ':' << DLT.getLineNumber();
1227 if (DLT.getColumnNumber() != 0)
1228 OS << ':' << DLT.getColumnNumber();
1234 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1235 const TargetRegisterInfo *RegInfo,
1236 bool AddIfNotFound) {
1237 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1238 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1240 SmallVector<unsigned,4> DeadOps;
1241 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1242 MachineOperand &MO = getOperand(i);
1243 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1245 unsigned Reg = MO.getReg();
1249 if (Reg == IncomingReg) {
1252 // The register is already marked kill.
1254 if (isPhysReg && isRegTiedToDefOperand(i))
1255 // Two-address uses of physregs must not be marked kill.
1260 } else if (hasAliases && MO.isKill() &&
1261 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1262 // A super-register kill already exists.
1263 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1265 if (RegInfo->isSubRegister(IncomingReg, Reg))
1266 DeadOps.push_back(i);
1270 // Trim unneeded kill operands.
1271 while (!DeadOps.empty()) {
1272 unsigned OpIdx = DeadOps.back();
1273 if (getOperand(OpIdx).isImplicit())
1274 RemoveOperand(OpIdx);
1276 getOperand(OpIdx).setIsKill(false);
1280 // If not found, this means an alias of one of the operands is killed. Add a
1281 // new implicit operand if required.
1282 if (!Found && AddIfNotFound) {
1283 addOperand(MachineOperand::CreateReg(IncomingReg,
1292 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1293 const TargetRegisterInfo *RegInfo,
1294 bool AddIfNotFound) {
1295 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1296 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1298 SmallVector<unsigned,4> DeadOps;
1299 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1300 MachineOperand &MO = getOperand(i);
1301 if (!MO.isReg() || !MO.isDef())
1303 unsigned Reg = MO.getReg();
1307 if (Reg == IncomingReg) {
1310 // The register is already marked dead.
1315 } else if (hasAliases && MO.isDead() &&
1316 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1317 // There exists a super-register that's marked dead.
1318 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1320 if (RegInfo->getSubRegisters(IncomingReg) &&
1321 RegInfo->getSuperRegisters(Reg) &&
1322 RegInfo->isSubRegister(IncomingReg, Reg))
1323 DeadOps.push_back(i);
1327 // Trim unneeded dead operands.
1328 while (!DeadOps.empty()) {
1329 unsigned OpIdx = DeadOps.back();
1330 if (getOperand(OpIdx).isImplicit())
1331 RemoveOperand(OpIdx);
1333 getOperand(OpIdx).setIsDead(false);
1337 // If not found, this means an alias of one of the operands is dead. Add a
1338 // new implicit operand if required.
1339 if (Found || !AddIfNotFound)
1342 addOperand(MachineOperand::CreateReg(IncomingReg,
1350 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1351 const TargetRegisterInfo *RegInfo) {
1352 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1353 if (!MO || MO->getSubReg())
1354 addOperand(MachineOperand::CreateReg(IncomingReg,
1360 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1361 unsigned Hash = MI->getOpcode() * 37;
1362 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1363 const MachineOperand &MO = MI->getOperand(i);
1364 uint64_t Key = (uint64_t)MO.getType() << 32;
1365 switch (MO.getType()) {
1367 case MachineOperand::MO_Register:
1368 if (MO.isDef() && MO.getReg() &&
1369 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1370 continue; // Skip virtual register defs.
1373 case MachineOperand::MO_Immediate:
1376 case MachineOperand::MO_FrameIndex:
1377 case MachineOperand::MO_ConstantPoolIndex:
1378 case MachineOperand::MO_JumpTableIndex:
1379 Key |= MO.getIndex();
1381 case MachineOperand::MO_MachineBasicBlock:
1382 Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1384 case MachineOperand::MO_GlobalAddress:
1385 Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1387 case MachineOperand::MO_BlockAddress:
1388 Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1391 Key += ~(Key << 32);
1393 Key += ~(Key << 13);
1397 Key += ~(Key << 27);
1399 Hash = (unsigned)Key + Hash * 37;