1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Constants.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/Value.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetInstrDesc.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Support/LeakDetector.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/Streams.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/ADT/FoldingSet.h"
32 //===----------------------------------------------------------------------===//
33 // MachineOperand Implementation
34 //===----------------------------------------------------------------------===//
36 /// AddRegOperandToRegInfo - Add this register operand to the specified
37 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
38 /// explicitly nulled out.
39 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
40 assert(isRegister() && "Can only add reg operand to use lists");
42 // If the reginfo pointer is null, just explicitly null out or next/prev
43 // pointers, to ensure they are not garbage.
45 Contents.Reg.Prev = 0;
46 Contents.Reg.Next = 0;
50 // Otherwise, add this operand to the head of the registers use/def list.
51 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
53 // For SSA values, we prefer to keep the definition at the start of the list.
54 // we do this by skipping over the definition if it is at the head of the
56 if (*Head && (*Head)->isDef())
57 Head = &(*Head)->Contents.Reg.Next;
59 Contents.Reg.Next = *Head;
60 if (Contents.Reg.Next) {
61 assert(getReg() == Contents.Reg.Next->getReg() &&
62 "Different regs on the same list!");
63 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
66 Contents.Reg.Prev = Head;
70 void MachineOperand::setReg(unsigned Reg) {
71 if (getReg() == Reg) return; // No change.
73 // Otherwise, we have to change the register. If this operand is embedded
74 // into a machine function, we need to update the old and new register's
76 if (MachineInstr *MI = getParent())
77 if (MachineBasicBlock *MBB = MI->getParent())
78 if (MachineFunction *MF = MBB->getParent()) {
79 RemoveRegOperandFromRegInfo();
80 Contents.Reg.RegNo = Reg;
81 AddRegOperandToRegInfo(&MF->getRegInfo());
85 // Otherwise, just change the register, no problem. :)
86 Contents.Reg.RegNo = Reg;
89 /// ChangeToImmediate - Replace this operand with a new immediate operand of
90 /// the specified value. If an operand is known to be an immediate already,
91 /// the setImm method should be used.
92 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
93 // If this operand is currently a register operand, and if this is in a
94 // function, deregister the operand from the register's use/def list.
95 if (isRegister() && getParent() && getParent()->getParent() &&
96 getParent()->getParent()->getParent())
97 RemoveRegOperandFromRegInfo();
99 OpKind = MO_Immediate;
100 Contents.ImmVal = ImmVal;
103 /// ChangeToRegister - Replace this operand with a new register operand of
104 /// the specified value. If an operand is known to be an register already,
105 /// the setReg method should be used.
106 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
107 bool isKill, bool isDead) {
108 // If this operand is already a register operand, use setReg to update the
109 // register's use/def lists.
111 assert(!isEarlyClobber());
114 // Otherwise, change this to a register and set the reg#.
115 OpKind = MO_Register;
116 Contents.Reg.RegNo = Reg;
118 // If this operand is embedded in a function, add the operand to the
119 // register's use/def list.
120 if (MachineInstr *MI = getParent())
121 if (MachineBasicBlock *MBB = MI->getParent())
122 if (MachineFunction *MF = MBB->getParent())
123 AddRegOperandToRegInfo(&MF->getRegInfo());
130 IsEarlyClobber = false;
134 /// isIdenticalTo - Return true if this operand is identical to the specified
136 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
137 if (getType() != Other.getType()) return false;
140 default: assert(0 && "Unrecognized operand type");
141 case MachineOperand::MO_Register:
142 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
143 getSubReg() == Other.getSubReg();
144 case MachineOperand::MO_Immediate:
145 return getImm() == Other.getImm();
146 case MachineOperand::MO_FPImmediate:
147 return getFPImm() == Other.getFPImm();
148 case MachineOperand::MO_MachineBasicBlock:
149 return getMBB() == Other.getMBB();
150 case MachineOperand::MO_FrameIndex:
151 return getIndex() == Other.getIndex();
152 case MachineOperand::MO_ConstantPoolIndex:
153 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
154 case MachineOperand::MO_JumpTableIndex:
155 return getIndex() == Other.getIndex();
156 case MachineOperand::MO_GlobalAddress:
157 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
158 case MachineOperand::MO_ExternalSymbol:
159 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
160 getOffset() == Other.getOffset();
164 /// print - Print the specified machine operand.
166 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
168 case MachineOperand::MO_Register:
169 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
170 OS << "%reg" << getReg();
172 // If the instruction is embedded into a basic block, we can find the
173 // target info for the instruction.
175 if (const MachineInstr *MI = getParent())
176 if (const MachineBasicBlock *MBB = MI->getParent())
177 if (const MachineFunction *MF = MBB->getParent())
178 TM = &MF->getTarget();
181 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
183 OS << "%mreg" << getReg();
186 if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) {
188 bool NeedComma = false;
190 if (NeedComma) OS << ",";
191 OS << (isDef() ? "imp-def" : "imp-use");
193 } else if (isDef()) {
194 if (NeedComma) OS << ",";
195 if (isEarlyClobber())
196 OS << "earlyclobber,";
200 if (isKill() || isDead()) {
201 if (NeedComma) OS << ",";
202 if (isKill()) OS << "kill";
203 if (isDead()) OS << "dead";
208 case MachineOperand::MO_Immediate:
211 case MachineOperand::MO_FPImmediate:
212 if (getFPImm()->getType() == Type::FloatTy) {
213 OS << getFPImm()->getValueAPF().convertToFloat();
215 OS << getFPImm()->getValueAPF().convertToDouble();
218 case MachineOperand::MO_MachineBasicBlock:
220 << ((Value*)getMBB()->getBasicBlock())->getName()
221 << "," << (void*)getMBB() << ">";
223 case MachineOperand::MO_FrameIndex:
224 OS << "<fi#" << getIndex() << ">";
226 case MachineOperand::MO_ConstantPoolIndex:
227 OS << "<cp#" << getIndex();
228 if (getOffset()) OS << "+" << getOffset();
231 case MachineOperand::MO_JumpTableIndex:
232 OS << "<jt#" << getIndex() << ">";
234 case MachineOperand::MO_GlobalAddress:
235 OS << "<ga:" << ((Value*)getGlobal())->getName();
236 if (getOffset()) OS << "+" << getOffset();
239 case MachineOperand::MO_ExternalSymbol:
240 OS << "<es:" << getSymbolName();
241 if (getOffset()) OS << "+" << getOffset();
245 assert(0 && "Unrecognized operand type");
249 //===----------------------------------------------------------------------===//
250 // MachineMemOperand Implementation
251 //===----------------------------------------------------------------------===//
253 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
254 int64_t o, uint64_t s, unsigned int a)
255 : Offset(o), Size(s), V(v),
256 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
257 assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
258 assert((isLoad() || isStore()) && "Not a load/store!");
261 /// Profile - Gather unique data for the object.
263 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
264 ID.AddInteger(Offset);
267 ID.AddInteger(Flags);
270 //===----------------------------------------------------------------------===//
271 // MachineInstr Implementation
272 //===----------------------------------------------------------------------===//
274 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
275 /// TID NULL and no operands.
276 MachineInstr::MachineInstr()
277 : TID(0), NumImplicitOps(0), Parent(0) {
278 // Make sure that we get added to a machine basicblock
279 LeakDetector::addGarbageObject(this);
282 void MachineInstr::addImplicitDefUseOperands() {
283 if (TID->ImplicitDefs)
284 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
285 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
286 if (TID->ImplicitUses)
287 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
288 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
291 /// MachineInstr ctor - This constructor create a MachineInstr and add the
292 /// implicit operands. It reserves space for number of operands specified by
293 /// TargetInstrDesc or the numOperands if it is not zero. (for
294 /// instructions with variable number of operands).
295 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
296 : TID(&tid), NumImplicitOps(0), Parent(0) {
297 if (!NoImp && TID->getImplicitDefs())
298 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
300 if (!NoImp && TID->getImplicitUses())
301 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
303 Operands.reserve(NumImplicitOps + TID->getNumOperands());
305 addImplicitDefUseOperands();
306 // Make sure that we get added to a machine basicblock
307 LeakDetector::addGarbageObject(this);
310 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
311 /// MachineInstr is created and added to the end of the specified basic block.
313 MachineInstr::MachineInstr(MachineBasicBlock *MBB,
314 const TargetInstrDesc &tid)
315 : TID(&tid), NumImplicitOps(0), Parent(0) {
316 assert(MBB && "Cannot use inserting ctor with null basic block!");
317 if (TID->ImplicitDefs)
318 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
320 if (TID->ImplicitUses)
321 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
323 Operands.reserve(NumImplicitOps + TID->getNumOperands());
324 addImplicitDefUseOperands();
325 // Make sure that we get added to a machine basicblock
326 LeakDetector::addGarbageObject(this);
327 MBB->push_back(this); // Add instruction to end of basic block!
330 /// MachineInstr ctor - Copies MachineInstr arg exactly
332 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
333 : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0) {
334 Operands.reserve(MI.getNumOperands());
337 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
338 addOperand(MI.getOperand(i));
339 NumImplicitOps = MI.NumImplicitOps;
341 // Add memory operands.
342 for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
343 j = MI.memoperands_end(); i != j; ++i)
344 addMemOperand(MF, *i);
346 // Set parent to null.
349 LeakDetector::addGarbageObject(this);
352 MachineInstr::~MachineInstr() {
353 LeakDetector::removeGarbageObject(this);
354 assert(MemOperands.empty() &&
355 "MachineInstr being deleted with live memoperands!");
357 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
358 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
359 assert((!Operands[i].isRegister() || !Operands[i].isOnRegUseList()) &&
360 "Reg operand def/use list corrupted");
365 /// getRegInfo - If this instruction is embedded into a MachineFunction,
366 /// return the MachineRegisterInfo object for the current function, otherwise
368 MachineRegisterInfo *MachineInstr::getRegInfo() {
369 if (MachineBasicBlock *MBB = getParent())
370 return &MBB->getParent()->getRegInfo();
374 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
375 /// this instruction from their respective use lists. This requires that the
376 /// operands already be on their use lists.
377 void MachineInstr::RemoveRegOperandsFromUseLists() {
378 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
379 if (Operands[i].isRegister())
380 Operands[i].RemoveRegOperandFromRegInfo();
384 /// AddRegOperandsToUseLists - Add all of the register operands in
385 /// this instruction from their respective use lists. This requires that the
386 /// operands not be on their use lists yet.
387 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
388 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
389 if (Operands[i].isRegister())
390 Operands[i].AddRegOperandToRegInfo(&RegInfo);
395 /// addOperand - Add the specified operand to the instruction. If it is an
396 /// implicit operand, it is added to the end of the operand list. If it is
397 /// an explicit operand it is added at the end of the explicit operand list
398 /// (before the first implicit operand).
399 void MachineInstr::addOperand(const MachineOperand &Op) {
400 bool isImpReg = Op.isRegister() && Op.isImplicit();
401 assert((isImpReg || !OperandsComplete()) &&
402 "Trying to add an operand to a machine instr that is already done!");
404 // If we are adding the operand to the end of the list, our job is simpler.
405 // This is true most of the time, so this is a reasonable optimization.
406 if (isImpReg || NumImplicitOps == 0) {
407 // We can only do this optimization if we know that the operand list won't
409 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
410 Operands.push_back(Op);
412 // Set the parent of the operand.
413 Operands.back().ParentMI = this;
415 // If the operand is a register, update the operand's use list.
417 Operands.back().AddRegOperandToRegInfo(getRegInfo());
422 // Otherwise, we have to insert a real operand before any implicit ones.
423 unsigned OpNo = Operands.size()-NumImplicitOps;
425 MachineRegisterInfo *RegInfo = getRegInfo();
427 // If this instruction isn't embedded into a function, then we don't need to
428 // update any operand lists.
430 // Simple insertion, no reginfo update needed for other register operands.
431 Operands.insert(Operands.begin()+OpNo, Op);
432 Operands[OpNo].ParentMI = this;
434 // Do explicitly set the reginfo for this operand though, to ensure the
435 // next/prev fields are properly nulled out.
436 if (Operands[OpNo].isRegister())
437 Operands[OpNo].AddRegOperandToRegInfo(0);
439 } else if (Operands.size()+1 <= Operands.capacity()) {
440 // Otherwise, we have to remove register operands from their register use
441 // list, add the operand, then add the register operands back to their use
442 // list. This also must handle the case when the operand list reallocates
443 // to somewhere else.
445 // If insertion of this operand won't cause reallocation of the operand
446 // list, just remove the implicit operands, add the operand, then re-add all
447 // the rest of the operands.
448 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
449 assert(Operands[i].isRegister() && "Should only be an implicit reg!");
450 Operands[i].RemoveRegOperandFromRegInfo();
453 // Add the operand. If it is a register, add it to the reg list.
454 Operands.insert(Operands.begin()+OpNo, Op);
455 Operands[OpNo].ParentMI = this;
457 if (Operands[OpNo].isRegister())
458 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
460 // Re-add all the implicit ops.
461 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
462 assert(Operands[i].isRegister() && "Should only be an implicit reg!");
463 Operands[i].AddRegOperandToRegInfo(RegInfo);
466 // Otherwise, we will be reallocating the operand list. Remove all reg
467 // operands from their list, then readd them after the operand list is
469 RemoveRegOperandsFromUseLists();
471 Operands.insert(Operands.begin()+OpNo, Op);
472 Operands[OpNo].ParentMI = this;
474 // Re-add all the operands.
475 AddRegOperandsToUseLists(*RegInfo);
479 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
480 /// fewer operand than it started with.
482 void MachineInstr::RemoveOperand(unsigned OpNo) {
483 assert(OpNo < Operands.size() && "Invalid operand number");
485 // Special case removing the last one.
486 if (OpNo == Operands.size()-1) {
487 // If needed, remove from the reg def/use list.
488 if (Operands.back().isRegister() && Operands.back().isOnRegUseList())
489 Operands.back().RemoveRegOperandFromRegInfo();
495 // Otherwise, we are removing an interior operand. If we have reginfo to
496 // update, remove all operands that will be shifted down from their reg lists,
497 // move everything down, then re-add them.
498 MachineRegisterInfo *RegInfo = getRegInfo();
500 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
501 if (Operands[i].isRegister())
502 Operands[i].RemoveRegOperandFromRegInfo();
506 Operands.erase(Operands.begin()+OpNo);
509 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
510 if (Operands[i].isRegister())
511 Operands[i].AddRegOperandToRegInfo(RegInfo);
516 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
517 /// referencing arbitrary storage.
518 void MachineInstr::addMemOperand(MachineFunction &MF,
519 const MachineMemOperand &MO) {
520 MemOperands.push_back(MO);
523 /// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
524 void MachineInstr::clearMemOperands(MachineFunction &MF) {
529 /// removeFromParent - This method unlinks 'this' from the containing basic
530 /// block, and returns it, but does not delete it.
531 MachineInstr *MachineInstr::removeFromParent() {
532 assert(getParent() && "Not embedded in a basic block!");
533 getParent()->remove(this);
538 /// eraseFromParent - This method unlinks 'this' from the containing basic
539 /// block, and deletes it.
540 void MachineInstr::eraseFromParent() {
541 assert(getParent() && "Not embedded in a basic block!");
542 getParent()->erase(this);
546 /// OperandComplete - Return true if it's illegal to add a new operand
548 bool MachineInstr::OperandsComplete() const {
549 unsigned short NumOperands = TID->getNumOperands();
550 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
551 return true; // Broken: we have all the operands of this instruction!
555 /// getNumExplicitOperands - Returns the number of non-implicit operands.
557 unsigned MachineInstr::getNumExplicitOperands() const {
558 unsigned NumOperands = TID->getNumOperands();
559 if (!TID->isVariadic())
562 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
563 const MachineOperand &MO = getOperand(NumOperands);
564 if (!MO.isRegister() || !MO.isImplicit())
571 /// isLabel - Returns true if the MachineInstr represents a label.
573 bool MachineInstr::isLabel() const {
574 return getOpcode() == TargetInstrInfo::DBG_LABEL ||
575 getOpcode() == TargetInstrInfo::EH_LABEL ||
576 getOpcode() == TargetInstrInfo::GC_LABEL;
579 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
581 bool MachineInstr::isDebugLabel() const {
582 return getOpcode() == TargetInstrInfo::DBG_LABEL;
585 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
586 /// the specific register or -1 if it is not found. It further tightening
587 /// the search criteria to a use that kills the register if isKill is true.
588 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
589 const TargetRegisterInfo *TRI) const {
590 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
591 const MachineOperand &MO = getOperand(i);
592 if (!MO.isRegister() || !MO.isUse())
594 unsigned MOReg = MO.getReg();
599 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
600 TargetRegisterInfo::isPhysicalRegister(Reg) &&
601 TRI->isSubRegister(MOReg, Reg)))
602 if (!isKill || MO.isKill())
608 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
609 /// the specified register or -1 if it is not found. If isDead is true, defs
610 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
611 /// also checks if there is a def of a super-register.
612 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
613 const TargetRegisterInfo *TRI) const {
614 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
615 const MachineOperand &MO = getOperand(i);
616 if (!MO.isRegister() || !MO.isDef())
618 unsigned MOReg = MO.getReg();
621 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
622 TargetRegisterInfo::isPhysicalRegister(Reg) &&
623 TRI->isSubRegister(MOReg, Reg)))
624 if (!isDead || MO.isDead())
630 /// findFirstPredOperandIdx() - Find the index of the first operand in the
631 /// operand list that is used to represent the predicate. It returns -1 if
633 int MachineInstr::findFirstPredOperandIdx() const {
634 const TargetInstrDesc &TID = getDesc();
635 if (TID.isPredicable()) {
636 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
637 if (TID.OpInfo[i].isPredicate())
644 /// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
645 /// check if the register def is a re-definition due to two addr elimination.
646 bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const{
647 const TargetInstrDesc &TID = getDesc();
648 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
649 const MachineOperand &MO = getOperand(i);
650 if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg &&
651 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
657 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
659 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
660 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
661 const MachineOperand &MO = MI->getOperand(i);
662 if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
664 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
665 MachineOperand &MOp = getOperand(j);
666 if (!MOp.isIdenticalTo(MO))
677 /// copyPredicates - Copies predicate operand(s) from MI.
678 void MachineInstr::copyPredicates(const MachineInstr *MI) {
679 const TargetInstrDesc &TID = MI->getDesc();
680 if (!TID.isPredicable())
682 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
683 if (TID.OpInfo[i].isPredicate()) {
684 // Predicated operands must be last operands.
685 addOperand(MI->getOperand(i));
690 /// isSafeToMove - Return true if it is safe to move this instruction. If
691 /// SawStore is set to true, it means that there is a store (or call) between
692 /// the instruction's location and its intended destination.
693 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) {
694 // Ignore stuff that we obviously can't move.
695 if (TID->mayStore() || TID->isCall()) {
699 if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects())
702 // See if this instruction does a load. If so, we have to guarantee that the
703 // loaded value doesn't change between the load and the its intended
704 // destination. The check for isInvariantLoad gives the targe the chance to
705 // classify the load as always returning a constant, e.g. a constant pool
707 if (TID->mayLoad() && !TII->isInvariantLoad(this))
708 // Otherwise, this is a real load. If there is a store between the load and
709 // end of block, or if the laod is volatile, we can't move it.
710 return SawStore || hasVolatileMemoryRef();
715 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
716 /// instruction which defined the specified register instead of copying it.
717 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, unsigned DstReg) {
718 bool SawStore = false;
719 if (!getDesc().isRematerializable() ||
720 !TII->isTriviallyReMaterializable(this) ||
721 !isSafeToMove(TII, SawStore))
723 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
724 MachineOperand &MO = getOperand(i);
725 if (!MO.isRegister())
727 // FIXME: For now, do not remat any instruction with register operands.
728 // Later on, we can loosen the restriction is the register operands have
729 // not been modified between the def and use. Note, this is different from
730 // MachineSink because the code is no longer in two-address form (at least
734 else if (!MO.isDead() && MO.getReg() != DstReg)
740 /// hasVolatileMemoryRef - Return true if this instruction may have a
741 /// volatile memory reference, or if the information describing the
742 /// memory reference is not available. Return false if it is known to
743 /// have no volatile memory references.
744 bool MachineInstr::hasVolatileMemoryRef() const {
745 // An instruction known never to access memory won't have a volatile access.
746 if (!TID->mayStore() &&
749 !TID->hasUnmodeledSideEffects())
752 // Otherwise, if the instruction has no memory reference information,
753 // conservatively assume it wasn't preserved.
754 if (memoperands_empty())
757 // Check the memory reference information for volatile references.
758 for (std::list<MachineMemOperand>::const_iterator I = memoperands_begin(),
759 E = memoperands_end(); I != E; ++I)
766 void MachineInstr::dump() const {
767 cerr << " " << *this;
770 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
771 // Specialize printing if op#0 is definition
772 unsigned StartOp = 0;
773 if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
774 getOperand(0).print(OS, TM);
776 ++StartOp; // Don't print this operand again!
779 OS << getDesc().getName();
781 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
785 getOperand(i).print(OS, TM);
788 if (!memoperands_empty()) {
790 for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(),
791 e = memoperands_end(); i != e; ++i) {
792 const MachineMemOperand &MRO = *i;
793 const Value *V = MRO.getValue();
795 assert((MRO.isLoad() || MRO.isStore()) &&
796 "SV has to be a load, store or both.");
798 if (MRO.isVolatile())
806 OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
810 else if (!V->getName().empty())
812 else if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
813 raw_os_ostream OSS(OS);
818 OS << " + " << MRO.getOffset() << "]";
825 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
826 const TargetRegisterInfo *RegInfo,
827 bool AddIfNotFound) {
828 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
829 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
831 SmallVector<unsigned,4> DeadOps;
832 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
833 MachineOperand &MO = getOperand(i);
834 if (!MO.isRegister() || !MO.isUse())
836 unsigned Reg = MO.getReg();
840 if (Reg == IncomingReg) {
843 // The register is already marked kill.
848 } else if (hasAliases && MO.isKill() &&
849 TargetRegisterInfo::isPhysicalRegister(Reg)) {
850 // A super-register kill already exists.
851 if (RegInfo->isSuperRegister(IncomingReg, Reg))
853 if (RegInfo->isSubRegister(IncomingReg, Reg))
854 DeadOps.push_back(i);
858 // Trim unneeded kill operands.
859 while (!DeadOps.empty()) {
860 unsigned OpIdx = DeadOps.back();
861 if (getOperand(OpIdx).isImplicit())
862 RemoveOperand(OpIdx);
864 getOperand(OpIdx).setIsKill(false);
868 // If not found, this means an alias of one of the operands is killed. Add a
869 // new implicit operand if required.
870 if (!Found && AddIfNotFound) {
871 addOperand(MachineOperand::CreateReg(IncomingReg,
880 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
881 const TargetRegisterInfo *RegInfo,
882 bool AddIfNotFound) {
883 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
884 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
886 SmallVector<unsigned,4> DeadOps;
887 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
888 MachineOperand &MO = getOperand(i);
889 if (!MO.isRegister() || !MO.isDef())
891 unsigned Reg = MO.getReg();
895 if (Reg == IncomingReg) {
898 // The register is already marked dead.
903 } else if (hasAliases && MO.isDead() &&
904 TargetRegisterInfo::isPhysicalRegister(Reg)) {
905 // There exists a super-register that's marked dead.
906 if (RegInfo->isSuperRegister(IncomingReg, Reg))
908 if (RegInfo->getSubRegisters(IncomingReg) &&
909 RegInfo->getSuperRegisters(Reg) &&
910 RegInfo->isSubRegister(IncomingReg, Reg))
911 DeadOps.push_back(i);
915 // Trim unneeded dead operands.
916 while (!DeadOps.empty()) {
917 unsigned OpIdx = DeadOps.back();
918 if (getOperand(OpIdx).isImplicit())
919 RemoveOperand(OpIdx);
921 getOperand(OpIdx).setIsDead(false);
925 // If not found, this means an alias of one of the operands is dead. Add a
926 // new implicit operand if required.
927 if (!Found && AddIfNotFound) {
928 addOperand(MachineOperand::CreateReg(IncomingReg,