1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Value.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetInstrDesc.h"
20 #include "llvm/Target/MRegisterInfo.h"
21 #include "llvm/Support/LeakDetector.h"
22 #include "llvm/Support/Streams.h"
26 //===----------------------------------------------------------------------===//
27 // MachineOperand Implementation
28 //===----------------------------------------------------------------------===//
30 /// AddRegOperandToRegInfo - Add this register operand to the specified
31 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
32 /// explicitly nulled out.
33 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
34 assert(isReg() && "Can only add reg operand to use lists");
36 // If the reginfo pointer is null, just explicitly null out or next/prev
37 // pointers, to ensure they are not garbage.
39 Contents.Reg.Prev = 0;
40 Contents.Reg.Next = 0;
44 // Otherwise, add this operand to the head of the registers use/def list.
45 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
47 // For SSA values, we prefer to keep the definition at the start of the list.
48 // we do this by skipping over the definition if it is at the head of the
50 if (*Head && (*Head)->isDef())
51 Head = &(*Head)->Contents.Reg.Next;
53 Contents.Reg.Next = *Head;
54 if (Contents.Reg.Next) {
55 assert(getReg() == Contents.Reg.Next->getReg() &&
56 "Different regs on the same list!");
57 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
60 Contents.Reg.Prev = Head;
64 void MachineOperand::setReg(unsigned Reg) {
65 if (getReg() == Reg) return; // No change.
67 // Otherwise, we have to change the register. If this operand is embedded
68 // into a machine function, we need to update the old and new register's
70 if (MachineInstr *MI = getParent())
71 if (MachineBasicBlock *MBB = MI->getParent())
72 if (MachineFunction *MF = MBB->getParent()) {
73 RemoveRegOperandFromRegInfo();
74 Contents.Reg.RegNo = Reg;
75 AddRegOperandToRegInfo(&MF->getRegInfo());
79 // Otherwise, just change the register, no problem. :)
80 Contents.Reg.RegNo = Reg;
83 /// ChangeToImmediate - Replace this operand with a new immediate operand of
84 /// the specified value. If an operand is known to be an immediate already,
85 /// the setImm method should be used.
86 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
87 // If this operand is currently a register operand, and if this is in a
88 // function, deregister the operand from the register's use/def list.
89 if (isReg() && getParent() && getParent()->getParent() &&
90 getParent()->getParent()->getParent())
91 RemoveRegOperandFromRegInfo();
93 OpKind = MO_Immediate;
94 Contents.ImmVal = ImmVal;
97 /// ChangeToRegister - Replace this operand with a new register operand of
98 /// the specified value. If an operand is known to be an register already,
99 /// the setReg method should be used.
100 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
101 bool isKill, bool isDead) {
102 // If this operand is already a register operand, use setReg to update the
103 // register's use/def lists.
107 // Otherwise, change this to a register and set the reg#.
108 OpKind = MO_Register;
109 Contents.Reg.RegNo = Reg;
111 // If this operand is embedded in a function, add the operand to the
112 // register's use/def list.
113 if (MachineInstr *MI = getParent())
114 if (MachineBasicBlock *MBB = MI->getParent())
115 if (MachineFunction *MF = MBB->getParent())
116 AddRegOperandToRegInfo(&MF->getRegInfo());
126 /// isIdenticalTo - Return true if this operand is identical to the specified
128 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
129 if (getType() != Other.getType()) return false;
132 default: assert(0 && "Unrecognized operand type");
133 case MachineOperand::MO_Register:
134 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
135 getSubReg() == Other.getSubReg();
136 case MachineOperand::MO_Immediate:
137 return getImm() == Other.getImm();
138 case MachineOperand::MO_MachineBasicBlock:
139 return getMBB() == Other.getMBB();
140 case MachineOperand::MO_FrameIndex:
141 return getIndex() == Other.getIndex();
142 case MachineOperand::MO_ConstantPoolIndex:
143 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
144 case MachineOperand::MO_JumpTableIndex:
145 return getIndex() == Other.getIndex();
146 case MachineOperand::MO_GlobalAddress:
147 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
148 case MachineOperand::MO_ExternalSymbol:
149 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
150 getOffset() == Other.getOffset();
154 /// print - Print the specified machine operand.
156 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
158 case MachineOperand::MO_Register:
159 if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) {
160 OS << "%reg" << getReg();
162 // If the instruction is embedded into a basic block, we can find the
163 // target info for the instruction.
165 if (const MachineInstr *MI = getParent())
166 if (const MachineBasicBlock *MBB = MI->getParent())
167 if (const MachineFunction *MF = MBB->getParent())
168 TM = &MF->getTarget();
171 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
173 OS << "%mreg" << getReg();
176 if (isDef() || isKill() || isDead() || isImplicit()) {
178 bool NeedComma = false;
180 OS << (isDef() ? "imp-def" : "imp-use");
182 } else if (isDef()) {
186 if (isKill() || isDead()) {
187 if (NeedComma) OS << ",";
188 if (isKill()) OS << "kill";
189 if (isDead()) OS << "dead";
194 case MachineOperand::MO_Immediate:
197 case MachineOperand::MO_MachineBasicBlock:
199 << ((Value*)getMBB()->getBasicBlock())->getName()
200 << "," << (void*)getMBB() << ">";
202 case MachineOperand::MO_FrameIndex:
203 OS << "<fi#" << getIndex() << ">";
205 case MachineOperand::MO_ConstantPoolIndex:
206 OS << "<cp#" << getIndex();
207 if (getOffset()) OS << "+" << getOffset();
210 case MachineOperand::MO_JumpTableIndex:
211 OS << "<jt#" << getIndex() << ">";
213 case MachineOperand::MO_GlobalAddress:
214 OS << "<ga:" << ((Value*)getGlobal())->getName();
215 if (getOffset()) OS << "+" << getOffset();
218 case MachineOperand::MO_ExternalSymbol:
219 OS << "<es:" << getSymbolName();
220 if (getOffset()) OS << "+" << getOffset();
224 assert(0 && "Unrecognized operand type");
228 //===----------------------------------------------------------------------===//
229 // MachineInstr Implementation
230 //===----------------------------------------------------------------------===//
232 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
233 /// TID NULL and no operands.
234 MachineInstr::MachineInstr()
235 : TID(0), NumImplicitOps(0), Parent(0) {
236 // Make sure that we get added to a machine basicblock
237 LeakDetector::addGarbageObject(this);
240 void MachineInstr::addImplicitDefUseOperands() {
241 if (TID->ImplicitDefs)
242 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
243 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
244 if (TID->ImplicitUses)
245 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
246 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
249 /// MachineInstr ctor - This constructor create a MachineInstr and add the
250 /// implicit operands. It reserves space for number of operands specified by
251 /// TargetInstrDesc or the numOperands if it is not zero. (for
252 /// instructions with variable number of operands).
253 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
254 : TID(&tid), NumImplicitOps(0), Parent(0) {
255 if (!NoImp && TID->getImplicitDefs())
256 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
258 if (!NoImp && TID->getImplicitUses())
259 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
261 Operands.reserve(NumImplicitOps + TID->getNumOperands());
263 addImplicitDefUseOperands();
264 // Make sure that we get added to a machine basicblock
265 LeakDetector::addGarbageObject(this);
268 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
269 /// MachineInstr is created and added to the end of the specified basic block.
271 MachineInstr::MachineInstr(MachineBasicBlock *MBB,
272 const TargetInstrDesc &tid)
273 : TID(&tid), NumImplicitOps(0), Parent(0) {
274 assert(MBB && "Cannot use inserting ctor with null basic block!");
275 if (TID->ImplicitDefs)
276 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
278 if (TID->ImplicitUses)
279 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
281 Operands.reserve(NumImplicitOps + TID->getNumOperands());
282 addImplicitDefUseOperands();
283 // Make sure that we get added to a machine basicblock
284 LeakDetector::addGarbageObject(this);
285 MBB->push_back(this); // Add instruction to end of basic block!
288 /// MachineInstr ctor - Copies MachineInstr arg exactly
290 MachineInstr::MachineInstr(const MachineInstr &MI) {
292 NumImplicitOps = MI.NumImplicitOps;
293 Operands.reserve(MI.getNumOperands());
296 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
297 Operands.push_back(MI.getOperand(i));
298 Operands.back().ParentMI = this;
301 // Set parent, next, and prev to null
308 MachineInstr::~MachineInstr() {
309 LeakDetector::removeGarbageObject(this);
311 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
312 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
313 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
314 "Reg operand def/use list corrupted");
319 /// getOpcode - Returns the opcode of this MachineInstr.
321 int MachineInstr::getOpcode() const {
325 /// getRegInfo - If this instruction is embedded into a MachineFunction,
326 /// return the MachineRegisterInfo object for the current function, otherwise
328 MachineRegisterInfo *MachineInstr::getRegInfo() {
329 if (MachineBasicBlock *MBB = getParent())
330 if (MachineFunction *MF = MBB->getParent())
331 return &MF->getRegInfo();
335 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
336 /// this instruction from their respective use lists. This requires that the
337 /// operands already be on their use lists.
338 void MachineInstr::RemoveRegOperandsFromUseLists() {
339 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
340 if (Operands[i].isReg())
341 Operands[i].RemoveRegOperandFromRegInfo();
345 /// AddRegOperandsToUseLists - Add all of the register operands in
346 /// this instruction from their respective use lists. This requires that the
347 /// operands not be on their use lists yet.
348 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
349 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
350 if (Operands[i].isReg())
351 Operands[i].AddRegOperandToRegInfo(&RegInfo);
356 /// addOperand - Add the specified operand to the instruction. If it is an
357 /// implicit operand, it is added to the end of the operand list. If it is
358 /// an explicit operand it is added at the end of the explicit operand list
359 /// (before the first implicit operand).
360 void MachineInstr::addOperand(const MachineOperand &Op) {
361 bool isImpReg = Op.isReg() && Op.isImplicit();
362 assert((isImpReg || !OperandsComplete()) &&
363 "Trying to add an operand to a machine instr that is already done!");
365 // If we are adding the operand to the end of the list, our job is simpler.
366 // This is true most of the time, so this is a reasonable optimization.
367 if (isImpReg || NumImplicitOps == 0) {
368 // We can only do this optimization if we know that the operand list won't
370 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
371 Operands.push_back(Op);
373 // Set the parent of the operand.
374 Operands.back().ParentMI = this;
376 // If the operand is a register, update the operand's use list.
378 Operands.back().AddRegOperandToRegInfo(getRegInfo());
383 // Otherwise, we have to insert a real operand before any implicit ones.
384 unsigned OpNo = Operands.size()-NumImplicitOps;
386 MachineRegisterInfo *RegInfo = getRegInfo();
388 // If this instruction isn't embedded into a function, then we don't need to
389 // update any operand lists.
391 // Simple insertion, no reginfo update needed for other register operands.
392 Operands.insert(Operands.begin()+OpNo, Op);
393 Operands[OpNo].ParentMI = this;
395 // Do explicitly set the reginfo for this operand though, to ensure the
396 // next/prev fields are properly nulled out.
397 if (Operands[OpNo].isReg())
398 Operands[OpNo].AddRegOperandToRegInfo(0);
400 } else if (Operands.size()+1 <= Operands.capacity()) {
401 // Otherwise, we have to remove register operands from their register use
402 // list, add the operand, then add the register operands back to their use
403 // list. This also must handle the case when the operand list reallocates
404 // to somewhere else.
406 // If insertion of this operand won't cause reallocation of the operand
407 // list, just remove the implicit operands, add the operand, then re-add all
408 // the rest of the operands.
409 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
410 assert(Operands[i].isReg() && "Should only be an implicit reg!");
411 Operands[i].RemoveRegOperandFromRegInfo();
414 // Add the operand. If it is a register, add it to the reg list.
415 Operands.insert(Operands.begin()+OpNo, Op);
416 Operands[OpNo].ParentMI = this;
418 if (Operands[OpNo].isReg())
419 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
421 // Re-add all the implicit ops.
422 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
423 assert(Operands[i].isReg() && "Should only be an implicit reg!");
424 Operands[i].AddRegOperandToRegInfo(RegInfo);
427 // Otherwise, we will be reallocating the operand list. Remove all reg
428 // operands from their list, then readd them after the operand list is
430 RemoveRegOperandsFromUseLists();
432 Operands.insert(Operands.begin()+OpNo, Op);
433 Operands[OpNo].ParentMI = this;
435 // Re-add all the operands.
436 AddRegOperandsToUseLists(*RegInfo);
440 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
441 /// fewer operand than it started with.
443 void MachineInstr::RemoveOperand(unsigned OpNo) {
444 assert(OpNo < Operands.size() && "Invalid operand number");
446 // Special case removing the last one.
447 if (OpNo == Operands.size()-1) {
448 // If needed, remove from the reg def/use list.
449 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
450 Operands.back().RemoveRegOperandFromRegInfo();
456 // Otherwise, we are removing an interior operand. If we have reginfo to
457 // update, remove all operands that will be shifted down from their reg lists,
458 // move everything down, then re-add them.
459 MachineRegisterInfo *RegInfo = getRegInfo();
461 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
462 if (Operands[i].isReg())
463 Operands[i].RemoveRegOperandFromRegInfo();
467 Operands.erase(Operands.begin()+OpNo);
470 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
471 if (Operands[i].isReg())
472 Operands[i].AddRegOperandToRegInfo(RegInfo);
478 /// removeFromParent - This method unlinks 'this' from the containing basic
479 /// block, and returns it, but does not delete it.
480 MachineInstr *MachineInstr::removeFromParent() {
481 assert(getParent() && "Not embedded in a basic block!");
482 getParent()->remove(this);
487 /// OperandComplete - Return true if it's illegal to add a new operand
489 bool MachineInstr::OperandsComplete() const {
490 unsigned short NumOperands = TID->getNumOperands();
491 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
492 return true; // Broken: we have all the operands of this instruction!
496 /// getNumExplicitOperands - Returns the number of non-implicit operands.
498 unsigned MachineInstr::getNumExplicitOperands() const {
499 unsigned NumOperands = TID->getNumOperands();
500 if (!TID->isVariadic())
503 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
504 const MachineOperand &MO = getOperand(NumOperands);
505 if (!MO.isRegister() || !MO.isImplicit())
512 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
513 /// the specific register or -1 if it is not found. It further tightening
514 /// the search criteria to a use that kills the register if isKill is true.
515 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
516 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
517 const MachineOperand &MO = getOperand(i);
518 if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
519 if (!isKill || MO.isKill())
525 /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
526 /// the specific register or NULL if it is not found.
527 MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
528 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
529 MachineOperand &MO = getOperand(i);
530 if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
536 /// findFirstPredOperandIdx() - Find the index of the first operand in the
537 /// operand list that is used to represent the predicate. It returns -1 if
539 int MachineInstr::findFirstPredOperandIdx() const {
540 const TargetInstrDesc &TID = getDesc();
541 if (TID.isPredicable()) {
542 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
543 if (TID.OpInfo[i].isPredicate())
550 /// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
551 /// to two addr elimination.
552 bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
553 const TargetInstrDesc &TID = getDesc();
554 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
555 const MachineOperand &MO1 = getOperand(i);
556 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
557 for (unsigned j = i+1; j < e; ++j) {
558 const MachineOperand &MO2 = getOperand(j);
559 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
560 TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i)
568 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
570 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
571 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
572 const MachineOperand &MO = MI->getOperand(i);
573 if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
575 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
576 MachineOperand &MOp = getOperand(j);
577 if (!MOp.isIdenticalTo(MO))
588 /// copyPredicates - Copies predicate operand(s) from MI.
589 void MachineInstr::copyPredicates(const MachineInstr *MI) {
590 const TargetInstrDesc &TID = MI->getDesc();
591 if (TID.isPredicable()) {
592 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
593 if (TID.OpInfo[i].isPredicate()) {
594 // Predicated operands must be last operands.
595 addOperand(MI->getOperand(i));
601 void MachineInstr::dump() const {
602 cerr << " " << *this;
605 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
606 // Specialize printing if op#0 is definition
607 unsigned StartOp = 0;
608 if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
609 getOperand(0).print(OS, TM);
611 ++StartOp; // Don't print this operand again!
614 OS << getDesc().getName();
616 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
620 getOperand(i).print(OS, TM);
626 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
627 const MRegisterInfo *RegInfo,
628 bool AddIfNotFound) {
630 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
631 MachineOperand &MO = getOperand(i);
632 if (MO.isRegister() && MO.isUse()) {
633 unsigned Reg = MO.getReg();
636 if (Reg == IncomingReg) {
640 } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
641 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
642 RegInfo->isSuperRegister(IncomingReg, Reg) &&
644 // A super-register kill already exists.
649 // If not found, this means an alias of one of the operand is killed. Add a
650 // new implicit operand if required.
651 if (!Found && AddIfNotFound) {
652 addOperand(MachineOperand::CreateReg(IncomingReg, false/*IsDef*/,
653 true/*IsImp*/,true/*IsKill*/));
659 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
660 const MRegisterInfo *RegInfo,
661 bool AddIfNotFound) {
663 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
664 MachineOperand &MO = getOperand(i);
665 if (MO.isRegister() && MO.isDef()) {
666 unsigned Reg = MO.getReg();
669 if (Reg == IncomingReg) {
673 } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
674 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
675 RegInfo->isSuperRegister(IncomingReg, Reg) &&
677 // There exists a super-register that's marked dead.
682 // If not found, this means an alias of one of the operand is dead. Add a
683 // new implicit operand.
684 if (!Found && AddIfNotFound) {
685 addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/,
686 true/*IsImp*/,false/*IsKill*/,
693 /// copyKillDeadInfo - copies killed/dead information from one instr to another
694 void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI,
695 const MRegisterInfo *RegInfo) {
696 // If the instruction defines any virtual registers, update the VarInfo,
697 // kill and dead information for the instruction.
698 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
699 MachineOperand &MO = OldMI->getOperand(i);
700 if (MO.isRegister() && MO.getReg() &&
701 MRegisterInfo::isVirtualRegister(MO.getReg())) {
702 unsigned Reg = MO.getReg();
706 addRegisterDead(Reg, RegInfo);
711 addRegisterKilled(Reg, RegInfo);