1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Constants.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/Value.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/CodeGen/SelectionDAGNodes.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetInstrDesc.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Support/LeakDetector.h"
26 #include "llvm/Support/Streams.h"
30 //===----------------------------------------------------------------------===//
31 // MachineOperand Implementation
32 //===----------------------------------------------------------------------===//
34 /// AddRegOperandToRegInfo - Add this register operand to the specified
35 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
36 /// explicitly nulled out.
37 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
38 assert(isReg() && "Can only add reg operand to use lists");
40 // If the reginfo pointer is null, just explicitly null out or next/prev
41 // pointers, to ensure they are not garbage.
43 Contents.Reg.Prev = 0;
44 Contents.Reg.Next = 0;
48 // Otherwise, add this operand to the head of the registers use/def list.
49 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
51 // For SSA values, we prefer to keep the definition at the start of the list.
52 // we do this by skipping over the definition if it is at the head of the
54 if (*Head && (*Head)->isDef())
55 Head = &(*Head)->Contents.Reg.Next;
57 Contents.Reg.Next = *Head;
58 if (Contents.Reg.Next) {
59 assert(getReg() == Contents.Reg.Next->getReg() &&
60 "Different regs on the same list!");
61 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
64 Contents.Reg.Prev = Head;
68 void MachineOperand::setReg(unsigned Reg) {
69 if (getReg() == Reg) return; // No change.
71 // Otherwise, we have to change the register. If this operand is embedded
72 // into a machine function, we need to update the old and new register's
74 if (MachineInstr *MI = getParent())
75 if (MachineBasicBlock *MBB = MI->getParent())
76 if (MachineFunction *MF = MBB->getParent()) {
77 RemoveRegOperandFromRegInfo();
78 Contents.Reg.RegNo = Reg;
79 AddRegOperandToRegInfo(&MF->getRegInfo());
83 // Otherwise, just change the register, no problem. :)
84 Contents.Reg.RegNo = Reg;
87 /// ChangeToImmediate - Replace this operand with a new immediate operand of
88 /// the specified value. If an operand is known to be an immediate already,
89 /// the setImm method should be used.
90 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
91 // If this operand is currently a register operand, and if this is in a
92 // function, deregister the operand from the register's use/def list.
93 if (isReg() && getParent() && getParent()->getParent() &&
94 getParent()->getParent()->getParent())
95 RemoveRegOperandFromRegInfo();
97 OpKind = MO_Immediate;
98 Contents.ImmVal = ImmVal;
101 /// ChangeToRegister - Replace this operand with a new register operand of
102 /// the specified value. If an operand is known to be an register already,
103 /// the setReg method should be used.
104 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
105 bool isKill, bool isDead) {
106 // If this operand is already a register operand, use setReg to update the
107 // register's use/def lists.
111 // Otherwise, change this to a register and set the reg#.
112 OpKind = MO_Register;
113 Contents.Reg.RegNo = Reg;
115 // If this operand is embedded in a function, add the operand to the
116 // register's use/def list.
117 if (MachineInstr *MI = getParent())
118 if (MachineBasicBlock *MBB = MI->getParent())
119 if (MachineFunction *MF = MBB->getParent())
120 AddRegOperandToRegInfo(&MF->getRegInfo());
130 /// isIdenticalTo - Return true if this operand is identical to the specified
132 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
133 if (getType() != Other.getType()) return false;
136 default: assert(0 && "Unrecognized operand type");
137 case MachineOperand::MO_Register:
138 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
139 getSubReg() == Other.getSubReg();
140 case MachineOperand::MO_Immediate:
141 return getImm() == Other.getImm();
142 case MachineOperand::MO_FPImmediate:
143 return getFPImm() == Other.getFPImm();
144 case MachineOperand::MO_MachineBasicBlock:
145 return getMBB() == Other.getMBB();
146 case MachineOperand::MO_FrameIndex:
147 return getIndex() == Other.getIndex();
148 case MachineOperand::MO_ConstantPoolIndex:
149 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
150 case MachineOperand::MO_JumpTableIndex:
151 return getIndex() == Other.getIndex();
152 case MachineOperand::MO_GlobalAddress:
153 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
154 case MachineOperand::MO_ExternalSymbol:
155 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
156 getOffset() == Other.getOffset();
160 /// print - Print the specified machine operand.
162 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
164 case MachineOperand::MO_Register:
165 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
166 OS << "%reg" << getReg();
168 // If the instruction is embedded into a basic block, we can find the
169 // target info for the instruction.
171 if (const MachineInstr *MI = getParent())
172 if (const MachineBasicBlock *MBB = MI->getParent())
173 if (const MachineFunction *MF = MBB->getParent())
174 TM = &MF->getTarget();
177 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
179 OS << "%mreg" << getReg();
182 if (isDef() || isKill() || isDead() || isImplicit()) {
184 bool NeedComma = false;
186 OS << (isDef() ? "imp-def" : "imp-use");
188 } else if (isDef()) {
192 if (isKill() || isDead()) {
193 if (NeedComma) OS << ",";
194 if (isKill()) OS << "kill";
195 if (isDead()) OS << "dead";
200 case MachineOperand::MO_Immediate:
203 case MachineOperand::MO_FPImmediate:
204 if (getFPImm()->getType() == Type::FloatTy) {
205 OS << getFPImm()->getValueAPF().convertToFloat();
207 OS << getFPImm()->getValueAPF().convertToDouble();
210 case MachineOperand::MO_MachineBasicBlock:
212 << ((Value*)getMBB()->getBasicBlock())->getName()
213 << "," << (void*)getMBB() << ">";
215 case MachineOperand::MO_FrameIndex:
216 OS << "<fi#" << getIndex() << ">";
218 case MachineOperand::MO_ConstantPoolIndex:
219 OS << "<cp#" << getIndex();
220 if (getOffset()) OS << "+" << getOffset();
223 case MachineOperand::MO_JumpTableIndex:
224 OS << "<jt#" << getIndex() << ">";
226 case MachineOperand::MO_GlobalAddress:
227 OS << "<ga:" << ((Value*)getGlobal())->getName();
228 if (getOffset()) OS << "+" << getOffset();
231 case MachineOperand::MO_ExternalSymbol:
232 OS << "<es:" << getSymbolName();
233 if (getOffset()) OS << "+" << getOffset();
237 assert(0 && "Unrecognized operand type");
241 //===----------------------------------------------------------------------===//
242 // MachineInstr Implementation
243 //===----------------------------------------------------------------------===//
245 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
246 /// TID NULL and no operands.
247 MachineInstr::MachineInstr()
248 : TID(0), NumImplicitOps(0), Parent(0) {
249 // Make sure that we get added to a machine basicblock
250 LeakDetector::addGarbageObject(this);
253 void MachineInstr::addImplicitDefUseOperands() {
254 if (TID->ImplicitDefs)
255 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
256 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
257 if (TID->ImplicitUses)
258 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
259 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
262 /// MachineInstr ctor - This constructor create a MachineInstr and add the
263 /// implicit operands. It reserves space for number of operands specified by
264 /// TargetInstrDesc or the numOperands if it is not zero. (for
265 /// instructions with variable number of operands).
266 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
267 : TID(&tid), NumImplicitOps(0), Parent(0) {
268 if (!NoImp && TID->getImplicitDefs())
269 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
271 if (!NoImp && TID->getImplicitUses())
272 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
274 Operands.reserve(NumImplicitOps + TID->getNumOperands());
276 addImplicitDefUseOperands();
277 // Make sure that we get added to a machine basicblock
278 LeakDetector::addGarbageObject(this);
281 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
282 /// MachineInstr is created and added to the end of the specified basic block.
284 MachineInstr::MachineInstr(MachineBasicBlock *MBB,
285 const TargetInstrDesc &tid)
286 : TID(&tid), NumImplicitOps(0), Parent(0) {
287 assert(MBB && "Cannot use inserting ctor with null basic block!");
288 if (TID->ImplicitDefs)
289 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
291 if (TID->ImplicitUses)
292 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
294 Operands.reserve(NumImplicitOps + TID->getNumOperands());
295 addImplicitDefUseOperands();
296 // Make sure that we get added to a machine basicblock
297 LeakDetector::addGarbageObject(this);
298 MBB->push_back(this); // Add instruction to end of basic block!
301 /// MachineInstr ctor - Copies MachineInstr arg exactly
303 MachineInstr::MachineInstr(const MachineInstr &MI) {
305 NumImplicitOps = MI.NumImplicitOps;
306 Operands.reserve(MI.getNumOperands());
307 MemOperands = MI.MemOperands;
310 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
311 Operands.push_back(MI.getOperand(i));
312 Operands.back().ParentMI = this;
315 // Set parent, next, and prev to null
322 MachineInstr::~MachineInstr() {
323 LeakDetector::removeGarbageObject(this);
325 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
326 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
327 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
328 "Reg operand def/use list corrupted");
333 /// getOpcode - Returns the opcode of this MachineInstr.
335 int MachineInstr::getOpcode() const {
339 /// getRegInfo - If this instruction is embedded into a MachineFunction,
340 /// return the MachineRegisterInfo object for the current function, otherwise
342 MachineRegisterInfo *MachineInstr::getRegInfo() {
343 if (MachineBasicBlock *MBB = getParent())
344 if (MachineFunction *MF = MBB->getParent())
345 return &MF->getRegInfo();
349 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
350 /// this instruction from their respective use lists. This requires that the
351 /// operands already be on their use lists.
352 void MachineInstr::RemoveRegOperandsFromUseLists() {
353 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
354 if (Operands[i].isReg())
355 Operands[i].RemoveRegOperandFromRegInfo();
359 /// AddRegOperandsToUseLists - Add all of the register operands in
360 /// this instruction from their respective use lists. This requires that the
361 /// operands not be on their use lists yet.
362 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
363 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
364 if (Operands[i].isReg())
365 Operands[i].AddRegOperandToRegInfo(&RegInfo);
370 /// addOperand - Add the specified operand to the instruction. If it is an
371 /// implicit operand, it is added to the end of the operand list. If it is
372 /// an explicit operand it is added at the end of the explicit operand list
373 /// (before the first implicit operand).
374 void MachineInstr::addOperand(const MachineOperand &Op) {
375 bool isImpReg = Op.isReg() && Op.isImplicit();
376 assert((isImpReg || !OperandsComplete()) &&
377 "Trying to add an operand to a machine instr that is already done!");
379 // If we are adding the operand to the end of the list, our job is simpler.
380 // This is true most of the time, so this is a reasonable optimization.
381 if (isImpReg || NumImplicitOps == 0) {
382 // We can only do this optimization if we know that the operand list won't
384 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
385 Operands.push_back(Op);
387 // Set the parent of the operand.
388 Operands.back().ParentMI = this;
390 // If the operand is a register, update the operand's use list.
392 Operands.back().AddRegOperandToRegInfo(getRegInfo());
397 // Otherwise, we have to insert a real operand before any implicit ones.
398 unsigned OpNo = Operands.size()-NumImplicitOps;
400 MachineRegisterInfo *RegInfo = getRegInfo();
402 // If this instruction isn't embedded into a function, then we don't need to
403 // update any operand lists.
405 // Simple insertion, no reginfo update needed for other register operands.
406 Operands.insert(Operands.begin()+OpNo, Op);
407 Operands[OpNo].ParentMI = this;
409 // Do explicitly set the reginfo for this operand though, to ensure the
410 // next/prev fields are properly nulled out.
411 if (Operands[OpNo].isReg())
412 Operands[OpNo].AddRegOperandToRegInfo(0);
414 } else if (Operands.size()+1 <= Operands.capacity()) {
415 // Otherwise, we have to remove register operands from their register use
416 // list, add the operand, then add the register operands back to their use
417 // list. This also must handle the case when the operand list reallocates
418 // to somewhere else.
420 // If insertion of this operand won't cause reallocation of the operand
421 // list, just remove the implicit operands, add the operand, then re-add all
422 // the rest of the operands.
423 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
424 assert(Operands[i].isReg() && "Should only be an implicit reg!");
425 Operands[i].RemoveRegOperandFromRegInfo();
428 // Add the operand. If it is a register, add it to the reg list.
429 Operands.insert(Operands.begin()+OpNo, Op);
430 Operands[OpNo].ParentMI = this;
432 if (Operands[OpNo].isReg())
433 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
435 // Re-add all the implicit ops.
436 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
437 assert(Operands[i].isReg() && "Should only be an implicit reg!");
438 Operands[i].AddRegOperandToRegInfo(RegInfo);
441 // Otherwise, we will be reallocating the operand list. Remove all reg
442 // operands from their list, then readd them after the operand list is
444 RemoveRegOperandsFromUseLists();
446 Operands.insert(Operands.begin()+OpNo, Op);
447 Operands[OpNo].ParentMI = this;
449 // Re-add all the operands.
450 AddRegOperandsToUseLists(*RegInfo);
454 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
455 /// fewer operand than it started with.
457 void MachineInstr::RemoveOperand(unsigned OpNo) {
458 assert(OpNo < Operands.size() && "Invalid operand number");
460 // Special case removing the last one.
461 if (OpNo == Operands.size()-1) {
462 // If needed, remove from the reg def/use list.
463 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
464 Operands.back().RemoveRegOperandFromRegInfo();
470 // Otherwise, we are removing an interior operand. If we have reginfo to
471 // update, remove all operands that will be shifted down from their reg lists,
472 // move everything down, then re-add them.
473 MachineRegisterInfo *RegInfo = getRegInfo();
475 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
476 if (Operands[i].isReg())
477 Operands[i].RemoveRegOperandFromRegInfo();
481 Operands.erase(Operands.begin()+OpNo);
484 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
485 if (Operands[i].isReg())
486 Operands[i].AddRegOperandToRegInfo(RegInfo);
492 /// removeFromParent - This method unlinks 'this' from the containing basic
493 /// block, and returns it, but does not delete it.
494 MachineInstr *MachineInstr::removeFromParent() {
495 assert(getParent() && "Not embedded in a basic block!");
496 getParent()->remove(this);
501 /// OperandComplete - Return true if it's illegal to add a new operand
503 bool MachineInstr::OperandsComplete() const {
504 unsigned short NumOperands = TID->getNumOperands();
505 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
506 return true; // Broken: we have all the operands of this instruction!
510 /// getNumExplicitOperands - Returns the number of non-implicit operands.
512 unsigned MachineInstr::getNumExplicitOperands() const {
513 unsigned NumOperands = TID->getNumOperands();
514 if (!TID->isVariadic())
517 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
518 const MachineOperand &MO = getOperand(NumOperands);
519 if (!MO.isRegister() || !MO.isImplicit())
526 /// isLabel - Returns true if the MachineInstr represents a label.
528 bool MachineInstr::isLabel() const {
529 return getOpcode() == TargetInstrInfo::DBG_LABEL ||
530 getOpcode() == TargetInstrInfo::EH_LABEL ||
531 getOpcode() == TargetInstrInfo::GC_LABEL;
534 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
536 bool MachineInstr::isDebugLabel() const {
537 return getOpcode() == TargetInstrInfo::DBG_LABEL;
540 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
541 /// the specific register or -1 if it is not found. It further tightening
542 /// the search criteria to a use that kills the register if isKill is true.
543 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
544 const TargetRegisterInfo *TRI) const {
545 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
546 const MachineOperand &MO = getOperand(i);
547 if (!MO.isRegister() || !MO.isUse())
549 unsigned MOReg = MO.getReg();
554 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
555 TargetRegisterInfo::isPhysicalRegister(Reg) &&
556 TRI->isSubRegister(MOReg, Reg)))
557 if (!isKill || MO.isKill())
563 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
564 /// the specified register or -1 if it is not found. If isDead is true, defs
565 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
566 /// also checks if there is a def of a super-register.
567 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
568 const TargetRegisterInfo *TRI) const {
569 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
570 const MachineOperand &MO = getOperand(i);
571 if (!MO.isRegister() || !MO.isDef())
573 unsigned MOReg = MO.getReg();
576 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
577 TargetRegisterInfo::isPhysicalRegister(Reg) &&
578 TRI->isSubRegister(MOReg, Reg)))
579 if (!isDead || MO.isDead())
585 /// findFirstPredOperandIdx() - Find the index of the first operand in the
586 /// operand list that is used to represent the predicate. It returns -1 if
588 int MachineInstr::findFirstPredOperandIdx() const {
589 const TargetInstrDesc &TID = getDesc();
590 if (TID.isPredicable()) {
591 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
592 if (TID.OpInfo[i].isPredicate())
599 /// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
600 /// to two addr elimination.
601 bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
602 const TargetInstrDesc &TID = getDesc();
603 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
604 const MachineOperand &MO1 = getOperand(i);
605 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
606 for (unsigned j = i+1; j < e; ++j) {
607 const MachineOperand &MO2 = getOperand(j);
608 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
609 TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i)
617 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
619 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
620 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
621 const MachineOperand &MO = MI->getOperand(i);
622 if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
624 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
625 MachineOperand &MOp = getOperand(j);
626 if (!MOp.isIdenticalTo(MO))
637 /// copyPredicates - Copies predicate operand(s) from MI.
638 void MachineInstr::copyPredicates(const MachineInstr *MI) {
639 const TargetInstrDesc &TID = MI->getDesc();
640 if (!TID.isPredicable())
642 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
643 if (TID.OpInfo[i].isPredicate()) {
644 // Predicated operands must be last operands.
645 addOperand(MI->getOperand(i));
650 /// isSafeToMove - Return true if it is safe to this instruction. If SawStore is
651 /// set to true, it means that there is a store (or call) between the
652 /// instruction's location and its intended destination.
653 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) {
654 // Ignore stuff that we obviously can't move.
655 if (TID->mayStore() || TID->isCall()) {
659 if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects())
662 // See if this instruction does a load. If so, we have to guarantee that the
663 // loaded value doesn't change between the load and the its intended
664 // destination. The check for isInvariantLoad gives the targe the chance to
665 // classify the load as always returning a constant, e.g. a constant pool
667 if (TID->mayLoad() && !TII->isInvariantLoad(this)) {
668 // Otherwise, this is a real load. If there is a store between the load and
669 // end of block, we can't sink the load.
671 // FIXME: we can't do this transformation until we know that the load is
672 // not volatile, and machineinstrs don't keep this info. :(
680 void MachineInstr::dump() const {
681 cerr << " " << *this;
684 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
685 // Specialize printing if op#0 is definition
686 unsigned StartOp = 0;
687 if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
688 getOperand(0).print(OS, TM);
690 ++StartOp; // Don't print this operand again!
693 OS << getDesc().getName();
695 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
699 getOperand(i).print(OS, TM);
702 if (getNumMemOperands() > 0) {
704 for (unsigned i = 0; i < getNumMemOperands(); i++) {
705 const MachineMemOperand &MRO = getMemOperand(i);
706 const Value *V = MRO.getValue();
708 assert((MRO.isLoad() || MRO.isStore()) &&
709 "SV has to be a load, store or both.");
711 if (MRO.isVolatile())
719 OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
723 else if (!V->getName().empty())
725 else if (isa<PseudoSourceValue>(V))
730 OS << " + " << MRO.getOffset() << "]";
737 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
738 const TargetRegisterInfo *RegInfo,
739 bool AddIfNotFound) {
740 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
742 SmallVector<unsigned,4> DeadOps;
743 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
744 MachineOperand &MO = getOperand(i);
745 if (!MO.isRegister() || !MO.isUse())
747 unsigned Reg = MO.getReg();
751 if (Reg == IncomingReg) {
752 if (!Found) // One kill of reg per instruction.
755 } else if (isPhysReg && MO.isKill() &&
756 TargetRegisterInfo::isPhysicalRegister(Reg)) {
757 // A super-register kill already exists.
758 if (RegInfo->isSuperRegister(IncomingReg, Reg))
760 else if (RegInfo->isSubRegister(IncomingReg, Reg))
761 DeadOps.push_back(i);
765 // Trim unneeded kill operands.
766 while (!DeadOps.empty()) {
767 unsigned OpIdx = DeadOps.back();
768 if (getOperand(OpIdx).isImplicit())
769 RemoveOperand(OpIdx);
771 getOperand(OpIdx).setIsKill(false);
775 // If not found, this means an alias of one of the operands is killed. Add a
776 // new implicit operand if required.
777 if (!Found && AddIfNotFound) {
778 addOperand(MachineOperand::CreateReg(IncomingReg,
787 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
788 const TargetRegisterInfo *RegInfo,
789 bool AddIfNotFound) {
790 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
791 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
793 SmallVector<unsigned,4> DeadOps;
794 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
795 MachineOperand &MO = getOperand(i);
796 if (!MO.isRegister() || !MO.isDef())
798 unsigned Reg = MO.getReg();
799 if (Reg == IncomingReg) {
802 } else if (hasAliases && MO.isDead() &&
803 TargetRegisterInfo::isPhysicalRegister(Reg)) {
804 // There exists a super-register that's marked dead.
805 if (RegInfo->isSuperRegister(IncomingReg, Reg))
807 else if (RegInfo->isSubRegister(IncomingReg, Reg))
808 DeadOps.push_back(i);
812 // Trim unneeded dead operands.
813 while (!DeadOps.empty()) {
814 unsigned OpIdx = DeadOps.back();
815 if (getOperand(OpIdx).isImplicit())
816 RemoveOperand(OpIdx);
818 getOperand(OpIdx).setIsDead(false);
822 // If not found, this means an alias of one of the operand is dead. Add a
823 // new implicit operand.
824 if (!Found && AddIfNotFound) {
825 addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/,
826 true/*IsImp*/,false/*IsKill*/,
833 /// copyKillDeadInfo - copies killed/dead information from one instr to another
834 void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI,
835 const TargetRegisterInfo *RegInfo) {
836 // If the instruction defines any virtual registers, update the VarInfo,
837 // kill and dead information for the instruction.
838 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
839 MachineOperand &MO = OldMI->getOperand(i);
840 if (MO.isRegister() && MO.getReg() &&
841 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
842 unsigned Reg = MO.getReg();
846 addRegisterDead(Reg, RegInfo);
851 addRegisterKilled(Reg, RegInfo);