1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Function.h"
17 #include "llvm/InlineAsm.h"
18 #include "llvm/Metadata.h"
19 #include "llvm/Type.h"
20 #include "llvm/Value.h"
21 #include "llvm/Assembly/Writer.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/MC/MCSymbol.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/Analysis/AliasAnalysis.h"
33 #include "llvm/Analysis/DebugInfo.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/LeakDetector.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/ADT/FoldingSet.h"
42 //===----------------------------------------------------------------------===//
43 // MachineOperand Implementation
44 //===----------------------------------------------------------------------===//
46 /// AddRegOperandToRegInfo - Add this register operand to the specified
47 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
48 /// explicitly nulled out.
49 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
50 assert(isReg() && "Can only add reg operand to use lists");
52 // If the reginfo pointer is null, just explicitly null out or next/prev
53 // pointers, to ensure they are not garbage.
55 Contents.Reg.Prev = 0;
56 Contents.Reg.Next = 0;
60 // Otherwise, add this operand to the head of the registers use/def list.
61 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
63 // For SSA values, we prefer to keep the definition at the start of the list.
64 // we do this by skipping over the definition if it is at the head of the
66 if (*Head && (*Head)->isDef())
67 Head = &(*Head)->Contents.Reg.Next;
69 Contents.Reg.Next = *Head;
70 if (Contents.Reg.Next) {
71 assert(getReg() == Contents.Reg.Next->getReg() &&
72 "Different regs on the same list!");
73 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
76 Contents.Reg.Prev = Head;
80 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
81 /// MachineRegisterInfo it is linked with.
82 void MachineOperand::RemoveRegOperandFromRegInfo() {
83 assert(isOnRegUseList() && "Reg operand is not on a use list");
84 // Unlink this from the doubly linked list of operands.
85 MachineOperand *NextOp = Contents.Reg.Next;
86 *Contents.Reg.Prev = NextOp;
88 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
89 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
91 Contents.Reg.Prev = 0;
92 Contents.Reg.Next = 0;
95 void MachineOperand::setReg(unsigned Reg) {
96 if (getReg() == Reg) return; // No change.
98 // Otherwise, we have to change the register. If this operand is embedded
99 // into a machine function, we need to update the old and new register's
101 if (MachineInstr *MI = getParent())
102 if (MachineBasicBlock *MBB = MI->getParent())
103 if (MachineFunction *MF = MBB->getParent()) {
104 RemoveRegOperandFromRegInfo();
105 SmallContents.RegNo = Reg;
106 AddRegOperandToRegInfo(&MF->getRegInfo());
110 // Otherwise, just change the register, no problem. :)
111 SmallContents.RegNo = Reg;
114 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
115 const TargetRegisterInfo &TRI) {
116 assert(TargetRegisterInfo::isVirtualRegister(Reg));
117 if (SubIdx && getSubReg())
118 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
124 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
125 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
127 Reg = TRI.getSubReg(Reg, getSubReg());
128 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
129 // That won't happen in legal code.
135 /// ChangeToImmediate - Replace this operand with a new immediate operand of
136 /// the specified value. If an operand is known to be an immediate already,
137 /// the setImm method should be used.
138 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
139 // If this operand is currently a register operand, and if this is in a
140 // function, deregister the operand from the register's use/def list.
141 if (isReg() && getParent() && getParent()->getParent() &&
142 getParent()->getParent()->getParent())
143 RemoveRegOperandFromRegInfo();
145 OpKind = MO_Immediate;
146 Contents.ImmVal = ImmVal;
149 /// ChangeToRegister - Replace this operand with a new register operand of
150 /// the specified value. If an operand is known to be an register already,
151 /// the setReg method should be used.
152 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
153 bool isKill, bool isDead, bool isUndef,
155 // If this operand is already a register operand, use setReg to update the
156 // register's use/def lists.
158 assert(!isEarlyClobber());
161 // Otherwise, change this to a register and set the reg#.
162 OpKind = MO_Register;
163 SmallContents.RegNo = Reg;
165 // If this operand is embedded in a function, add the operand to the
166 // register's use/def list.
167 if (MachineInstr *MI = getParent())
168 if (MachineBasicBlock *MBB = MI->getParent())
169 if (MachineFunction *MF = MBB->getParent())
170 AddRegOperandToRegInfo(&MF->getRegInfo());
178 IsEarlyClobber = false;
183 /// isIdenticalTo - Return true if this operand is identical to the specified
185 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
186 if (getType() != Other.getType() ||
187 getTargetFlags() != Other.getTargetFlags())
191 default: llvm_unreachable("Unrecognized operand type");
192 case MachineOperand::MO_Register:
193 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
194 getSubReg() == Other.getSubReg();
195 case MachineOperand::MO_Immediate:
196 return getImm() == Other.getImm();
197 case MachineOperand::MO_CImmediate:
198 return getCImm() == Other.getCImm();
199 case MachineOperand::MO_FPImmediate:
200 return getFPImm() == Other.getFPImm();
201 case MachineOperand::MO_MachineBasicBlock:
202 return getMBB() == Other.getMBB();
203 case MachineOperand::MO_FrameIndex:
204 return getIndex() == Other.getIndex();
205 case MachineOperand::MO_ConstantPoolIndex:
206 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
207 case MachineOperand::MO_JumpTableIndex:
208 return getIndex() == Other.getIndex();
209 case MachineOperand::MO_GlobalAddress:
210 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
211 case MachineOperand::MO_ExternalSymbol:
212 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
213 getOffset() == Other.getOffset();
214 case MachineOperand::MO_BlockAddress:
215 return getBlockAddress() == Other.getBlockAddress();
216 case MachineOperand::MO_MCSymbol:
217 return getMCSymbol() == Other.getMCSymbol();
218 case MachineOperand::MO_Metadata:
219 return getMetadata() == Other.getMetadata();
223 /// print - Print the specified machine operand.
225 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
226 // If the instruction is embedded into a basic block, we can find the
227 // target info for the instruction.
229 if (const MachineInstr *MI = getParent())
230 if (const MachineBasicBlock *MBB = MI->getParent())
231 if (const MachineFunction *MF = MBB->getParent())
232 TM = &MF->getTarget();
233 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
236 case MachineOperand::MO_Register:
237 OS << PrintReg(getReg(), TRI, getSubReg());
239 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
242 bool NeedComma = false;
244 if (NeedComma) OS << ',';
245 if (isEarlyClobber())
246 OS << "earlyclobber,";
251 } else if (isImplicit()) {
256 if (isKill() || isDead() || isUndef()) {
257 if (NeedComma) OS << ',';
258 if (isKill()) OS << "kill";
259 if (isDead()) OS << "dead";
261 if (isKill() || isDead())
269 case MachineOperand::MO_Immediate:
272 case MachineOperand::MO_CImmediate:
273 getCImm()->getValue().print(OS, false);
275 case MachineOperand::MO_FPImmediate:
276 if (getFPImm()->getType()->isFloatTy())
277 OS << getFPImm()->getValueAPF().convertToFloat();
279 OS << getFPImm()->getValueAPF().convertToDouble();
281 case MachineOperand::MO_MachineBasicBlock:
282 OS << "<BB#" << getMBB()->getNumber() << ">";
284 case MachineOperand::MO_FrameIndex:
285 OS << "<fi#" << getIndex() << '>';
287 case MachineOperand::MO_ConstantPoolIndex:
288 OS << "<cp#" << getIndex();
289 if (getOffset()) OS << "+" << getOffset();
292 case MachineOperand::MO_JumpTableIndex:
293 OS << "<jt#" << getIndex() << '>';
295 case MachineOperand::MO_GlobalAddress:
297 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
298 if (getOffset()) OS << "+" << getOffset();
301 case MachineOperand::MO_ExternalSymbol:
302 OS << "<es:" << getSymbolName();
303 if (getOffset()) OS << "+" << getOffset();
306 case MachineOperand::MO_BlockAddress:
308 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
311 case MachineOperand::MO_Metadata:
313 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
316 case MachineOperand::MO_MCSymbol:
317 OS << "<MCSym=" << *getMCSymbol() << '>';
320 llvm_unreachable("Unrecognized operand type");
323 if (unsigned TF = getTargetFlags())
324 OS << "[TF=" << TF << ']';
327 //===----------------------------------------------------------------------===//
328 // MachineMemOperand Implementation
329 //===----------------------------------------------------------------------===//
331 /// getAddrSpace - Return the LLVM IR address space number that this pointer
333 unsigned MachinePointerInfo::getAddrSpace() const {
334 if (V == 0) return 0;
335 return cast<PointerType>(V->getType())->getAddressSpace();
338 /// getConstantPool - Return a MachinePointerInfo record that refers to the
340 MachinePointerInfo MachinePointerInfo::getConstantPool() {
341 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
344 /// getFixedStack - Return a MachinePointerInfo record that refers to the
345 /// the specified FrameIndex.
346 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
347 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
350 MachinePointerInfo MachinePointerInfo::getJumpTable() {
351 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
354 MachinePointerInfo MachinePointerInfo::getGOT() {
355 return MachinePointerInfo(PseudoSourceValue::getGOT());
358 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
359 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
362 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
363 uint64_t s, unsigned int a,
364 const MDNode *TBAAInfo)
365 : PtrInfo(ptrinfo), Size(s),
366 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
368 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
369 "invalid pointer value");
370 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
371 assert((isLoad() || isStore()) && "Not a load/store!");
374 /// Profile - Gather unique data for the object.
376 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
377 ID.AddInteger(getOffset());
379 ID.AddPointer(getValue());
380 ID.AddInteger(Flags);
383 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
384 // The Value and Offset may differ due to CSE. But the flags and size
385 // should be the same.
386 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
387 assert(MMO->getSize() == getSize() && "Size mismatch!");
389 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
390 // Update the alignment value.
391 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
392 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
393 // Also update the base and offset, because the new alignment may
394 // not be applicable with the old ones.
395 PtrInfo = MMO->PtrInfo;
399 /// getAlignment - Return the minimum known alignment in bytes of the
400 /// actual memory reference.
401 uint64_t MachineMemOperand::getAlignment() const {
402 return MinAlign(getBaseAlignment(), getOffset());
405 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
406 assert((MMO.isLoad() || MMO.isStore()) &&
407 "SV has to be a load, store or both.");
409 if (MMO.isVolatile())
418 // Print the address information.
423 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
425 // If the alignment of the memory reference itself differs from the alignment
426 // of the base pointer, print the base alignment explicitly, next to the base
428 if (MMO.getBaseAlignment() != MMO.getAlignment())
429 OS << "(align=" << MMO.getBaseAlignment() << ")";
431 if (MMO.getOffset() != 0)
432 OS << "+" << MMO.getOffset();
435 // Print the alignment of the reference.
436 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
437 MMO.getBaseAlignment() != MMO.getSize())
438 OS << "(align=" << MMO.getAlignment() << ")";
441 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
443 if (TBAAInfo->getNumOperands() > 0)
444 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
450 // Print nontemporal info.
451 if (MMO.isNonTemporal())
452 OS << "(nontemporal)";
457 //===----------------------------------------------------------------------===//
458 // MachineInstr Implementation
459 //===----------------------------------------------------------------------===//
461 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
462 /// MCID NULL and no operands.
463 MachineInstr::MachineInstr()
464 : MCID(0), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
465 MemRefs(0), MemRefsEnd(0),
467 // Make sure that we get added to a machine basicblock
468 LeakDetector::addGarbageObject(this);
471 void MachineInstr::addImplicitDefUseOperands() {
472 if (MCID->ImplicitDefs)
473 for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs)
474 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
475 if (MCID->ImplicitUses)
476 for (const unsigned *ImpUses = MCID->ImplicitUses; *ImpUses; ++ImpUses)
477 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
480 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
481 /// implicit operands. It reserves space for the number of operands specified by
483 MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
484 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
485 MemRefs(0), MemRefsEnd(0), Parent(0) {
487 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
488 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
490 addImplicitDefUseOperands();
491 // Make sure that we get added to a machine basicblock
492 LeakDetector::addGarbageObject(this);
495 /// MachineInstr ctor - As above, but with a DebugLoc.
496 MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
498 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
499 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
501 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
502 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
504 addImplicitDefUseOperands();
505 // Make sure that we get added to a machine basicblock
506 LeakDetector::addGarbageObject(this);
509 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
510 /// that the MachineInstr is created and added to the end of the specified
512 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
513 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
514 MemRefs(0), MemRefsEnd(0), Parent(0) {
515 assert(MBB && "Cannot use inserting ctor with null basic block!");
516 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
517 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
518 addImplicitDefUseOperands();
519 // Make sure that we get added to a machine basicblock
520 LeakDetector::addGarbageObject(this);
521 MBB->push_back(this); // Add instruction to end of basic block!
524 /// MachineInstr ctor - As above, but with a DebugLoc.
526 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
527 const MCInstrDesc &tid)
528 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
529 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
530 assert(MBB && "Cannot use inserting ctor with null basic block!");
531 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
532 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
533 addImplicitDefUseOperands();
534 // Make sure that we get added to a machine basicblock
535 LeakDetector::addGarbageObject(this);
536 MBB->push_back(this); // Add instruction to end of basic block!
539 /// MachineInstr ctor - Copies MachineInstr arg exactly
541 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
542 : MCID(&MI.getDesc()), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
543 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
544 Parent(0), debugLoc(MI.getDebugLoc()) {
545 Operands.reserve(MI.getNumOperands());
548 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
549 addOperand(MI.getOperand(i));
550 NumImplicitOps = MI.NumImplicitOps;
552 // Copy all the flags.
555 // Set parent to null.
558 LeakDetector::addGarbageObject(this);
561 MachineInstr::~MachineInstr() {
562 LeakDetector::removeGarbageObject(this);
564 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
565 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
566 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
567 "Reg operand def/use list corrupted");
572 /// getRegInfo - If this instruction is embedded into a MachineFunction,
573 /// return the MachineRegisterInfo object for the current function, otherwise
575 MachineRegisterInfo *MachineInstr::getRegInfo() {
576 if (MachineBasicBlock *MBB = getParent())
577 return &MBB->getParent()->getRegInfo();
581 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
582 /// this instruction from their respective use lists. This requires that the
583 /// operands already be on their use lists.
584 void MachineInstr::RemoveRegOperandsFromUseLists() {
585 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
586 if (Operands[i].isReg())
587 Operands[i].RemoveRegOperandFromRegInfo();
591 /// AddRegOperandsToUseLists - Add all of the register operands in
592 /// this instruction from their respective use lists. This requires that the
593 /// operands not be on their use lists yet.
594 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
595 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
596 if (Operands[i].isReg())
597 Operands[i].AddRegOperandToRegInfo(&RegInfo);
602 /// addOperand - Add the specified operand to the instruction. If it is an
603 /// implicit operand, it is added to the end of the operand list. If it is
604 /// an explicit operand it is added at the end of the explicit operand list
605 /// (before the first implicit operand).
606 void MachineInstr::addOperand(const MachineOperand &Op) {
607 bool isImpReg = Op.isReg() && Op.isImplicit();
608 assert((isImpReg || !OperandsComplete()) &&
609 "Trying to add an operand to a machine instr that is already done!");
611 MachineRegisterInfo *RegInfo = getRegInfo();
613 // If we are adding the operand to the end of the list, our job is simpler.
614 // This is true most of the time, so this is a reasonable optimization.
615 if (isImpReg || NumImplicitOps == 0) {
616 // We can only do this optimization if we know that the operand list won't
618 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
619 Operands.push_back(Op);
621 // Set the parent of the operand.
622 Operands.back().ParentMI = this;
624 // If the operand is a register, update the operand's use list.
626 Operands.back().AddRegOperandToRegInfo(RegInfo);
627 // If the register operand is flagged as early, mark the operand as such
628 unsigned OpNo = Operands.size() - 1;
629 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
630 Operands[OpNo].setIsEarlyClobber(true);
636 // Otherwise, we have to insert a real operand before any implicit ones.
637 unsigned OpNo = Operands.size()-NumImplicitOps;
639 // If this instruction isn't embedded into a function, then we don't need to
640 // update any operand lists.
642 // Simple insertion, no reginfo update needed for other register operands.
643 Operands.insert(Operands.begin()+OpNo, Op);
644 Operands[OpNo].ParentMI = this;
646 // Do explicitly set the reginfo for this operand though, to ensure the
647 // next/prev fields are properly nulled out.
648 if (Operands[OpNo].isReg()) {
649 Operands[OpNo].AddRegOperandToRegInfo(0);
650 // If the register operand is flagged as early, mark the operand as such
651 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
652 Operands[OpNo].setIsEarlyClobber(true);
655 } else if (Operands.size()+1 <= Operands.capacity()) {
656 // Otherwise, we have to remove register operands from their register use
657 // list, add the operand, then add the register operands back to their use
658 // list. This also must handle the case when the operand list reallocates
659 // to somewhere else.
661 // If insertion of this operand won't cause reallocation of the operand
662 // list, just remove the implicit operands, add the operand, then re-add all
663 // the rest of the operands.
664 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
665 assert(Operands[i].isReg() && "Should only be an implicit reg!");
666 Operands[i].RemoveRegOperandFromRegInfo();
669 // Add the operand. If it is a register, add it to the reg list.
670 Operands.insert(Operands.begin()+OpNo, Op);
671 Operands[OpNo].ParentMI = this;
673 if (Operands[OpNo].isReg()) {
674 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
675 // If the register operand is flagged as early, mark the operand as such
676 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
677 Operands[OpNo].setIsEarlyClobber(true);
680 // Re-add all the implicit ops.
681 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
682 assert(Operands[i].isReg() && "Should only be an implicit reg!");
683 Operands[i].AddRegOperandToRegInfo(RegInfo);
686 // Otherwise, we will be reallocating the operand list. Remove all reg
687 // operands from their list, then readd them after the operand list is
689 RemoveRegOperandsFromUseLists();
691 Operands.insert(Operands.begin()+OpNo, Op);
692 Operands[OpNo].ParentMI = this;
694 // Re-add all the operands.
695 AddRegOperandsToUseLists(*RegInfo);
697 // If the register operand is flagged as early, mark the operand as such
698 if (Operands[OpNo].isReg()
699 && MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
700 Operands[OpNo].setIsEarlyClobber(true);
704 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
705 /// fewer operand than it started with.
707 void MachineInstr::RemoveOperand(unsigned OpNo) {
708 assert(OpNo < Operands.size() && "Invalid operand number");
710 // Special case removing the last one.
711 if (OpNo == Operands.size()-1) {
712 // If needed, remove from the reg def/use list.
713 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
714 Operands.back().RemoveRegOperandFromRegInfo();
720 // Otherwise, we are removing an interior operand. If we have reginfo to
721 // update, remove all operands that will be shifted down from their reg lists,
722 // move everything down, then re-add them.
723 MachineRegisterInfo *RegInfo = getRegInfo();
725 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
726 if (Operands[i].isReg())
727 Operands[i].RemoveRegOperandFromRegInfo();
731 Operands.erase(Operands.begin()+OpNo);
734 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
735 if (Operands[i].isReg())
736 Operands[i].AddRegOperandToRegInfo(RegInfo);
741 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
742 /// This function should be used only occasionally. The setMemRefs function
743 /// is the primary method for setting up a MachineInstr's MemRefs list.
744 void MachineInstr::addMemOperand(MachineFunction &MF,
745 MachineMemOperand *MO) {
746 mmo_iterator OldMemRefs = MemRefs;
747 mmo_iterator OldMemRefsEnd = MemRefsEnd;
749 size_t NewNum = (MemRefsEnd - MemRefs) + 1;
750 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
751 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
753 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
754 NewMemRefs[NewNum - 1] = MO;
756 MemRefs = NewMemRefs;
757 MemRefsEnd = NewMemRefsEnd;
760 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
761 MICheckType Check) const {
762 // If opcodes or number of operands are not the same then the two
763 // instructions are obviously not identical.
764 if (Other->getOpcode() != getOpcode() ||
765 Other->getNumOperands() != getNumOperands())
768 // Check operands to make sure they match.
769 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
770 const MachineOperand &MO = getOperand(i);
771 const MachineOperand &OMO = Other->getOperand(i);
773 if (!MO.isIdenticalTo(OMO))
778 // Clients may or may not want to ignore defs when testing for equality.
779 // For example, machine CSE pass only cares about finding common
780 // subexpressions, so it's safe to ignore virtual register defs.
782 if (Check == IgnoreDefs)
784 else if (Check == IgnoreVRegDefs) {
785 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
786 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
787 if (MO.getReg() != OMO.getReg())
790 if (!MO.isIdenticalTo(OMO))
792 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
796 if (!MO.isIdenticalTo(OMO))
798 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
805 /// removeFromParent - This method unlinks 'this' from the containing basic
806 /// block, and returns it, but does not delete it.
807 MachineInstr *MachineInstr::removeFromParent() {
808 assert(getParent() && "Not embedded in a basic block!");
809 getParent()->remove(this);
814 /// eraseFromParent - This method unlinks 'this' from the containing basic
815 /// block, and deletes it.
816 void MachineInstr::eraseFromParent() {
817 assert(getParent() && "Not embedded in a basic block!");
818 getParent()->erase(this);
822 /// OperandComplete - Return true if it's illegal to add a new operand
824 bool MachineInstr::OperandsComplete() const {
825 unsigned short NumOperands = MCID->getNumOperands();
826 if (!MCID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
827 return true; // Broken: we have all the operands of this instruction!
831 /// getNumExplicitOperands - Returns the number of non-implicit operands.
833 unsigned MachineInstr::getNumExplicitOperands() const {
834 unsigned NumOperands = MCID->getNumOperands();
835 if (!MCID->isVariadic())
838 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
839 const MachineOperand &MO = getOperand(i);
840 if (!MO.isReg() || !MO.isImplicit())
846 bool MachineInstr::isStackAligningInlineAsm() const {
848 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
849 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
855 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
856 /// the specific register or -1 if it is not found. It further tightens
857 /// the search criteria to a use that kills the register if isKill is true.
858 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
859 const TargetRegisterInfo *TRI) const {
860 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
861 const MachineOperand &MO = getOperand(i);
862 if (!MO.isReg() || !MO.isUse())
864 unsigned MOReg = MO.getReg();
869 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
870 TargetRegisterInfo::isPhysicalRegister(Reg) &&
871 TRI->isSubRegister(MOReg, Reg)))
872 if (!isKill || MO.isKill())
878 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
879 /// indicating if this instruction reads or writes Reg. This also considers
882 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
883 SmallVectorImpl<unsigned> *Ops) const {
884 bool PartDef = false; // Partial redefine.
885 bool FullDef = false; // Full define.
888 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
889 const MachineOperand &MO = getOperand(i);
890 if (!MO.isReg() || MO.getReg() != Reg)
895 Use |= !MO.isUndef();
896 else if (MO.getSubReg())
901 // A partial redefine uses Reg unless there is also a full define.
902 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
905 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
906 /// the specified register or -1 if it is not found. If isDead is true, defs
907 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
908 /// also checks if there is a def of a super-register.
910 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
911 const TargetRegisterInfo *TRI) const {
912 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
913 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
914 const MachineOperand &MO = getOperand(i);
915 if (!MO.isReg() || !MO.isDef())
917 unsigned MOReg = MO.getReg();
918 bool Found = (MOReg == Reg);
919 if (!Found && TRI && isPhys &&
920 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
922 Found = TRI->regsOverlap(MOReg, Reg);
924 Found = TRI->isSubRegister(MOReg, Reg);
926 if (Found && (!isDead || MO.isDead()))
932 /// findFirstPredOperandIdx() - Find the index of the first operand in the
933 /// operand list that is used to represent the predicate. It returns -1 if
935 int MachineInstr::findFirstPredOperandIdx() const {
936 const MCInstrDesc &MCID = getDesc();
937 if (MCID.isPredicable()) {
938 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
939 if (MCID.OpInfo[i].isPredicate())
946 /// isRegTiedToUseOperand - Given the index of a register def operand,
947 /// check if the register def is tied to a source operand, due to either
948 /// two-address elimination or inline assembly constraints. Returns the
949 /// first tied use operand index by reference is UseOpIdx is not null.
951 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
953 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
954 const MachineOperand &MO = getOperand(DefOpIdx);
955 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
957 // Determine the actual operand index that corresponds to this index.
959 unsigned DefPart = 0;
960 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
962 const MachineOperand &FMO = getOperand(i);
963 // After the normal asm operands there may be additional imp-def regs.
966 // Skip over this def.
967 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
968 unsigned PrevDef = i + 1;
969 i = PrevDef + NumOps;
971 DefPart = DefOpIdx - PrevDef;
976 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
978 const MachineOperand &FMO = getOperand(i);
981 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
984 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
987 *UseOpIdx = (unsigned)i + 1 + DefPart;
994 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
995 const MCInstrDesc &MCID = getDesc();
996 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
997 const MachineOperand &MO = getOperand(i);
998 if (MO.isReg() && MO.isUse() &&
999 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
1001 *UseOpIdx = (unsigned)i;
1008 /// isRegTiedToDefOperand - Return true if the operand of the specified index
1009 /// is a register use and it is tied to an def operand. It also returns the def
1010 /// operand index by reference.
1012 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
1013 if (isInlineAsm()) {
1014 const MachineOperand &MO = getOperand(UseOpIdx);
1015 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
1018 // Find the flag operand corresponding to UseOpIdx
1019 unsigned FlagIdx, NumOps=0;
1020 for (FlagIdx = InlineAsm::MIOp_FirstOperand;
1021 FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
1022 const MachineOperand &UFMO = getOperand(FlagIdx);
1023 // After the normal asm operands there may be additional imp-def regs.
1026 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
1027 assert(NumOps < getNumOperands() && "Invalid inline asm flag");
1028 if (UseOpIdx < FlagIdx+NumOps+1)
1031 if (FlagIdx >= UseOpIdx)
1033 const MachineOperand &UFMO = getOperand(FlagIdx);
1035 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1039 unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1040 // Remember to adjust the index. First operand is asm string, second is
1041 // the HasSideEffects and AlignStack bits, then there is a flag for each.
1043 const MachineOperand &FMO = getOperand(DefIdx);
1044 assert(FMO.isImm());
1045 // Skip over this def.
1046 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1049 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1055 const MCInstrDesc &MCID = getDesc();
1056 if (UseOpIdx >= MCID.getNumOperands())
1058 const MachineOperand &MO = getOperand(UseOpIdx);
1059 if (!MO.isReg() || !MO.isUse())
1061 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
1065 *DefOpIdx = (unsigned)DefIdx;
1069 /// clearKillInfo - Clears kill flags on all operands.
1071 void MachineInstr::clearKillInfo() {
1072 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1073 MachineOperand &MO = getOperand(i);
1074 if (MO.isReg() && MO.isUse())
1075 MO.setIsKill(false);
1079 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1081 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1082 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1083 const MachineOperand &MO = MI->getOperand(i);
1084 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1086 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1087 MachineOperand &MOp = getOperand(j);
1088 if (!MOp.isIdenticalTo(MO))
1099 /// copyPredicates - Copies predicate operand(s) from MI.
1100 void MachineInstr::copyPredicates(const MachineInstr *MI) {
1101 const MCInstrDesc &MCID = MI->getDesc();
1102 if (!MCID.isPredicable())
1104 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1105 if (MCID.OpInfo[i].isPredicate()) {
1106 // Predicated operands must be last operands.
1107 addOperand(MI->getOperand(i));
1112 void MachineInstr::substituteRegister(unsigned FromReg,
1115 const TargetRegisterInfo &RegInfo) {
1116 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1118 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1119 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1120 MachineOperand &MO = getOperand(i);
1121 if (!MO.isReg() || MO.getReg() != FromReg)
1123 MO.substPhysReg(ToReg, RegInfo);
1126 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1127 MachineOperand &MO = getOperand(i);
1128 if (!MO.isReg() || MO.getReg() != FromReg)
1130 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1135 /// isSafeToMove - Return true if it is safe to move this instruction. If
1136 /// SawStore is set to true, it means that there is a store (or call) between
1137 /// the instruction's location and its intended destination.
1138 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1140 bool &SawStore) const {
1141 // Ignore stuff that we obviously can't move.
1142 if (MCID->mayStore() || MCID->isCall()) {
1147 if (isLabel() || isDebugValue() ||
1148 MCID->isTerminator() || hasUnmodeledSideEffects())
1151 // See if this instruction does a load. If so, we have to guarantee that the
1152 // loaded value doesn't change between the load and the its intended
1153 // destination. The check for isInvariantLoad gives the targe the chance to
1154 // classify the load as always returning a constant, e.g. a constant pool
1156 if (MCID->mayLoad() && !isInvariantLoad(AA))
1157 // Otherwise, this is a real load. If there is a store between the load and
1158 // end of block, or if the load is volatile, we can't move it.
1159 return !SawStore && !hasVolatileMemoryRef();
1164 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1165 /// instruction which defined the specified register instead of copying it.
1166 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1168 unsigned DstReg) const {
1169 bool SawStore = false;
1170 if (!TII->isTriviallyReMaterializable(this, AA) ||
1171 !isSafeToMove(TII, AA, SawStore))
1173 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1174 const MachineOperand &MO = getOperand(i);
1177 // FIXME: For now, do not remat any instruction with register operands.
1178 // Later on, we can loosen the restriction is the register operands have
1179 // not been modified between the def and use. Note, this is different from
1180 // MachineSink because the code is no longer in two-address form (at least
1184 else if (!MO.isDead() && MO.getReg() != DstReg)
1190 /// hasVolatileMemoryRef - Return true if this instruction may have a
1191 /// volatile memory reference, or if the information describing the
1192 /// memory reference is not available. Return false if it is known to
1193 /// have no volatile memory references.
1194 bool MachineInstr::hasVolatileMemoryRef() const {
1195 // An instruction known never to access memory won't have a volatile access.
1196 if (!MCID->mayStore() &&
1199 !hasUnmodeledSideEffects())
1202 // Otherwise, if the instruction has no memory reference information,
1203 // conservatively assume it wasn't preserved.
1204 if (memoperands_empty())
1207 // Check the memory reference information for volatile references.
1208 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1209 if ((*I)->isVolatile())
1215 /// isInvariantLoad - Return true if this instruction is loading from a
1216 /// location whose value is invariant across the function. For example,
1217 /// loading a value from the constant pool or from the argument area
1218 /// of a function if it does not change. This should only return true of
1219 /// *all* loads the instruction does are invariant (if it does multiple loads).
1220 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1221 // If the instruction doesn't load at all, it isn't an invariant load.
1222 if (!MCID->mayLoad())
1225 // If the instruction has lost its memoperands, conservatively assume that
1226 // it may not be an invariant load.
1227 if (memoperands_empty())
1230 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1232 for (mmo_iterator I = memoperands_begin(),
1233 E = memoperands_end(); I != E; ++I) {
1234 if ((*I)->isVolatile()) return false;
1235 if ((*I)->isStore()) return false;
1237 if (const Value *V = (*I)->getValue()) {
1238 // A load from a constant PseudoSourceValue is invariant.
1239 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1240 if (PSV->isConstant(MFI))
1242 // If we have an AliasAnalysis, ask it whether the memory is constant.
1243 if (AA && AA->pointsToConstantMemory(
1244 AliasAnalysis::Location(V, (*I)->getSize(),
1245 (*I)->getTBAAInfo())))
1249 // Otherwise assume conservatively.
1253 // Everything checks out.
1257 /// isConstantValuePHI - If the specified instruction is a PHI that always
1258 /// merges together the same virtual register, return the register, otherwise
1260 unsigned MachineInstr::isConstantValuePHI() const {
1263 assert(getNumOperands() >= 3 &&
1264 "It's illegal to have a PHI without source operands");
1266 unsigned Reg = getOperand(1).getReg();
1267 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1268 if (getOperand(i).getReg() != Reg)
1273 bool MachineInstr::hasUnmodeledSideEffects() const {
1274 if (getDesc().hasUnmodeledSideEffects())
1276 if (isInlineAsm()) {
1277 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1278 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1285 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1287 bool MachineInstr::allDefsAreDead() const {
1288 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1289 const MachineOperand &MO = getOperand(i);
1290 if (!MO.isReg() || MO.isUse())
1298 /// copyImplicitOps - Copy implicit register operands from specified
1299 /// instruction to this instruction.
1300 void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1301 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1303 const MachineOperand &MO = MI->getOperand(i);
1304 if (MO.isReg() && MO.isImplicit())
1309 void MachineInstr::dump() const {
1310 dbgs() << " " << *this;
1313 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1314 raw_ostream &CommentOS) {
1315 const LLVMContext &Ctx = MF->getFunction()->getContext();
1316 if (!DL.isUnknown()) { // Print source line info.
1317 DIScope Scope(DL.getScope(Ctx));
1318 // Omit the directory, because it's likely to be long and uninteresting.
1320 CommentOS << Scope.getFilename();
1322 CommentOS << "<unknown>";
1323 CommentOS << ':' << DL.getLine();
1324 if (DL.getCol() != 0)
1325 CommentOS << ':' << DL.getCol();
1326 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1327 if (!InlinedAtDL.isUnknown()) {
1328 CommentOS << " @[ ";
1329 printDebugLoc(InlinedAtDL, MF, CommentOS);
1335 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1336 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1337 const MachineFunction *MF = 0;
1338 const MachineRegisterInfo *MRI = 0;
1339 if (const MachineBasicBlock *MBB = getParent()) {
1340 MF = MBB->getParent();
1342 TM = &MF->getTarget();
1344 MRI = &MF->getRegInfo();
1347 // Save a list of virtual registers.
1348 SmallVector<unsigned, 8> VirtRegs;
1350 // Print explicitly defined operands on the left of an assignment syntax.
1351 unsigned StartOp = 0, e = getNumOperands();
1352 for (; StartOp < e && getOperand(StartOp).isReg() &&
1353 getOperand(StartOp).isDef() &&
1354 !getOperand(StartOp).isImplicit();
1356 if (StartOp != 0) OS << ", ";
1357 getOperand(StartOp).print(OS, TM);
1358 unsigned Reg = getOperand(StartOp).getReg();
1359 if (TargetRegisterInfo::isVirtualRegister(Reg))
1360 VirtRegs.push_back(Reg);
1366 // Print the opcode name.
1367 OS << getDesc().getName();
1369 // Print the rest of the operands.
1370 bool OmittedAnyCallClobbers = false;
1371 bool FirstOp = true;
1372 unsigned AsmDescOp = ~0u;
1373 unsigned AsmOpCount = 0;
1375 if (isInlineAsm()) {
1376 // Print asm string.
1378 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1380 // Print HasSideEffects, IsAlignStack
1381 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1382 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1383 OS << " [sideeffect]";
1384 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1385 OS << " [alignstack]";
1387 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1392 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1393 const MachineOperand &MO = getOperand(i);
1395 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1396 VirtRegs.push_back(MO.getReg());
1398 // Omit call-clobbered registers which aren't used anywhere. This makes
1399 // call instructions much less noisy on targets where calls clobber lots
1400 // of registers. Don't rely on MO.isDead() because we may be called before
1401 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1402 if (MF && getDesc().isCall() &&
1403 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1404 unsigned Reg = MO.getReg();
1405 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1406 const MachineRegisterInfo &MRI = MF->getRegInfo();
1407 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1408 bool HasAliasLive = false;
1409 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1410 unsigned AliasReg = *Alias; ++Alias)
1411 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1412 HasAliasLive = true;
1415 if (!HasAliasLive) {
1416 OmittedAnyCallClobbers = true;
1423 if (FirstOp) FirstOp = false; else OS << ",";
1425 if (i < getDesc().NumOperands) {
1426 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1427 if (MCOI.isPredicate())
1429 if (MCOI.isOptionalDef())
1432 if (isDebugValue() && MO.isMetadata()) {
1433 // Pretty print DBG_VALUE instructions.
1434 const MDNode *MD = MO.getMetadata();
1435 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1436 OS << "!\"" << MDS->getString() << '\"';
1439 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1440 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1441 } else if (i == AsmDescOp && MO.isImm()) {
1442 // Pretty print the inline asm operand descriptor.
1443 OS << '$' << AsmOpCount++;
1444 unsigned Flag = MO.getImm();
1445 switch (InlineAsm::getKind(Flag)) {
1446 case InlineAsm::Kind_RegUse: OS << ":[reguse]"; break;
1447 case InlineAsm::Kind_RegDef: OS << ":[regdef]"; break;
1448 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec]"; break;
1449 case InlineAsm::Kind_Clobber: OS << ":[clobber]"; break;
1450 case InlineAsm::Kind_Imm: OS << ":[imm]"; break;
1451 case InlineAsm::Kind_Mem: OS << ":[mem]"; break;
1452 default: OS << ":[??" << InlineAsm::getKind(Flag) << ']'; break;
1455 unsigned TiedTo = 0;
1456 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1457 OS << " [tiedto:$" << TiedTo << ']';
1459 // Compute the index of the next operand descriptor.
1460 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1465 // Briefly indicate whether any call clobbers were omitted.
1466 if (OmittedAnyCallClobbers) {
1467 if (!FirstOp) OS << ",";
1471 bool HaveSemi = false;
1473 if (!HaveSemi) OS << ";"; HaveSemi = true;
1476 if (Flags & FrameSetup)
1480 if (!memoperands_empty()) {
1481 if (!HaveSemi) OS << ";"; HaveSemi = true;
1484 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1487 if (llvm::next(i) != e)
1492 // Print the regclass of any virtual registers encountered.
1493 if (MRI && !VirtRegs.empty()) {
1494 if (!HaveSemi) OS << ";"; HaveSemi = true;
1495 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1496 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1497 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1498 for (unsigned j = i+1; j != VirtRegs.size();) {
1499 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1503 if (VirtRegs[i] != VirtRegs[j])
1504 OS << "," << PrintReg(VirtRegs[j]);
1505 VirtRegs.erase(VirtRegs.begin()+j);
1510 // Print debug location information.
1511 if (!debugLoc.isUnknown() && MF) {
1512 if (!HaveSemi) OS << ";"; HaveSemi = true;
1514 printDebugLoc(debugLoc, MF, OS);
1520 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1521 const TargetRegisterInfo *RegInfo,
1522 bool AddIfNotFound) {
1523 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1524 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1526 SmallVector<unsigned,4> DeadOps;
1527 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1528 MachineOperand &MO = getOperand(i);
1529 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1531 unsigned Reg = MO.getReg();
1535 if (Reg == IncomingReg) {
1538 // The register is already marked kill.
1540 if (isPhysReg && isRegTiedToDefOperand(i))
1541 // Two-address uses of physregs must not be marked kill.
1546 } else if (hasAliases && MO.isKill() &&
1547 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1548 // A super-register kill already exists.
1549 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1551 if (RegInfo->isSubRegister(IncomingReg, Reg))
1552 DeadOps.push_back(i);
1556 // Trim unneeded kill operands.
1557 while (!DeadOps.empty()) {
1558 unsigned OpIdx = DeadOps.back();
1559 if (getOperand(OpIdx).isImplicit())
1560 RemoveOperand(OpIdx);
1562 getOperand(OpIdx).setIsKill(false);
1566 // If not found, this means an alias of one of the operands is killed. Add a
1567 // new implicit operand if required.
1568 if (!Found && AddIfNotFound) {
1569 addOperand(MachineOperand::CreateReg(IncomingReg,
1578 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1579 const TargetRegisterInfo *RegInfo,
1580 bool AddIfNotFound) {
1581 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1582 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1584 SmallVector<unsigned,4> DeadOps;
1585 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1586 MachineOperand &MO = getOperand(i);
1587 if (!MO.isReg() || !MO.isDef())
1589 unsigned Reg = MO.getReg();
1593 if (Reg == IncomingReg) {
1596 } else if (hasAliases && MO.isDead() &&
1597 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1598 // There exists a super-register that's marked dead.
1599 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1601 if (RegInfo->getSubRegisters(IncomingReg) &&
1602 RegInfo->getSuperRegisters(Reg) &&
1603 RegInfo->isSubRegister(IncomingReg, Reg))
1604 DeadOps.push_back(i);
1608 // Trim unneeded dead operands.
1609 while (!DeadOps.empty()) {
1610 unsigned OpIdx = DeadOps.back();
1611 if (getOperand(OpIdx).isImplicit())
1612 RemoveOperand(OpIdx);
1614 getOperand(OpIdx).setIsDead(false);
1618 // If not found, this means an alias of one of the operands is dead. Add a
1619 // new implicit operand if required.
1620 if (Found || !AddIfNotFound)
1623 addOperand(MachineOperand::CreateReg(IncomingReg,
1631 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1632 const TargetRegisterInfo *RegInfo) {
1633 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1634 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1638 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1639 const MachineOperand &MO = getOperand(i);
1640 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1641 MO.getSubReg() == 0)
1645 addOperand(MachineOperand::CreateReg(IncomingReg,
1650 void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
1651 const TargetRegisterInfo &TRI) {
1652 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1653 MachineOperand &MO = getOperand(i);
1654 if (!MO.isReg() || !MO.isDef()) continue;
1655 unsigned Reg = MO.getReg();
1656 if (Reg == 0) continue;
1658 for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
1659 E = UsedRegs.end(); I != E; ++I)
1660 if (TRI.regsOverlap(*I, Reg)) {
1664 // If there are no uses, including partial uses, the def is dead.
1665 if (Dead) MO.setIsDead();
1670 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1671 unsigned Hash = MI->getOpcode() * 37;
1672 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1673 const MachineOperand &MO = MI->getOperand(i);
1674 uint64_t Key = (uint64_t)MO.getType() << 32;
1675 switch (MO.getType()) {
1677 case MachineOperand::MO_Register:
1678 if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1679 continue; // Skip virtual register defs.
1682 case MachineOperand::MO_Immediate:
1685 case MachineOperand::MO_FrameIndex:
1686 case MachineOperand::MO_ConstantPoolIndex:
1687 case MachineOperand::MO_JumpTableIndex:
1688 Key |= MO.getIndex();
1690 case MachineOperand::MO_MachineBasicBlock:
1691 Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1693 case MachineOperand::MO_GlobalAddress:
1694 Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1696 case MachineOperand::MO_BlockAddress:
1697 Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1699 case MachineOperand::MO_MCSymbol:
1700 Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1703 Key += ~(Key << 32);
1705 Key += ~(Key << 13);
1709 Key += ~(Key << 27);
1711 Hash = (unsigned)Key + Hash * 37;