1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Constants.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/Value.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetInstrDesc.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Support/LeakDetector.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/Streams.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/ADT/FoldingSet.h"
32 //===----------------------------------------------------------------------===//
33 // MachineOperand Implementation
34 //===----------------------------------------------------------------------===//
36 /// AddRegOperandToRegInfo - Add this register operand to the specified
37 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
38 /// explicitly nulled out.
39 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
40 assert(isReg() && "Can only add reg operand to use lists");
42 // If the reginfo pointer is null, just explicitly null out or next/prev
43 // pointers, to ensure they are not garbage.
45 Contents.Reg.Prev = 0;
46 Contents.Reg.Next = 0;
50 // Otherwise, add this operand to the head of the registers use/def list.
51 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
53 // For SSA values, we prefer to keep the definition at the start of the list.
54 // we do this by skipping over the definition if it is at the head of the
56 if (*Head && (*Head)->isDef())
57 Head = &(*Head)->Contents.Reg.Next;
59 Contents.Reg.Next = *Head;
60 if (Contents.Reg.Next) {
61 assert(getReg() == Contents.Reg.Next->getReg() &&
62 "Different regs on the same list!");
63 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
66 Contents.Reg.Prev = Head;
70 void MachineOperand::setReg(unsigned Reg) {
71 if (getReg() == Reg) return; // No change.
73 // Otherwise, we have to change the register. If this operand is embedded
74 // into a machine function, we need to update the old and new register's
76 if (MachineInstr *MI = getParent())
77 if (MachineBasicBlock *MBB = MI->getParent())
78 if (MachineFunction *MF = MBB->getParent()) {
79 RemoveRegOperandFromRegInfo();
80 Contents.Reg.RegNo = Reg;
81 AddRegOperandToRegInfo(&MF->getRegInfo());
85 // Otherwise, just change the register, no problem. :)
86 Contents.Reg.RegNo = Reg;
89 /// ChangeToImmediate - Replace this operand with a new immediate operand of
90 /// the specified value. If an operand is known to be an immediate already,
91 /// the setImm method should be used.
92 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
93 // If this operand is currently a register operand, and if this is in a
94 // function, deregister the operand from the register's use/def list.
95 if (isReg() && getParent() && getParent()->getParent() &&
96 getParent()->getParent()->getParent())
97 RemoveRegOperandFromRegInfo();
99 OpKind = MO_Immediate;
100 Contents.ImmVal = ImmVal;
103 /// ChangeToRegister - Replace this operand with a new register operand of
104 /// the specified value. If an operand is known to be an register already,
105 /// the setReg method should be used.
106 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
107 bool isKill, bool isDead) {
108 // If this operand is already a register operand, use setReg to update the
109 // register's use/def lists.
111 assert(!isEarlyClobber());
114 // Otherwise, change this to a register and set the reg#.
115 OpKind = MO_Register;
116 Contents.Reg.RegNo = Reg;
118 // If this operand is embedded in a function, add the operand to the
119 // register's use/def list.
120 if (MachineInstr *MI = getParent())
121 if (MachineBasicBlock *MBB = MI->getParent())
122 if (MachineFunction *MF = MBB->getParent())
123 AddRegOperandToRegInfo(&MF->getRegInfo());
130 IsEarlyClobber = false;
134 /// isIdenticalTo - Return true if this operand is identical to the specified
136 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
137 if (getType() != Other.getType()) return false;
140 default: assert(0 && "Unrecognized operand type");
141 case MachineOperand::MO_Register:
142 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
143 getSubReg() == Other.getSubReg();
144 case MachineOperand::MO_Immediate:
145 return getImm() == Other.getImm();
146 case MachineOperand::MO_FPImmediate:
147 return getFPImm() == Other.getFPImm();
148 case MachineOperand::MO_MachineBasicBlock:
149 return getMBB() == Other.getMBB();
150 case MachineOperand::MO_FrameIndex:
151 return getIndex() == Other.getIndex();
152 case MachineOperand::MO_ConstantPoolIndex:
153 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
154 case MachineOperand::MO_JumpTableIndex:
155 return getIndex() == Other.getIndex();
156 case MachineOperand::MO_GlobalAddress:
157 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
158 case MachineOperand::MO_ExternalSymbol:
159 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
160 getOffset() == Other.getOffset();
164 /// print - Print the specified machine operand.
166 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
167 raw_os_ostream RawOS(OS);
171 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
173 case MachineOperand::MO_Register:
174 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
175 OS << "%reg" << getReg();
177 // If the instruction is embedded into a basic block, we can find the
178 // target info for the instruction.
180 if (const MachineInstr *MI = getParent())
181 if (const MachineBasicBlock *MBB = MI->getParent())
182 if (const MachineFunction *MF = MBB->getParent())
183 TM = &MF->getTarget();
186 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
188 OS << "%mreg" << getReg();
191 if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) {
193 bool NeedComma = false;
195 if (NeedComma) OS << ",";
196 OS << (isDef() ? "imp-def" : "imp-use");
198 } else if (isDef()) {
199 if (NeedComma) OS << ",";
200 if (isEarlyClobber())
201 OS << "earlyclobber,";
205 if (isKill() || isDead()) {
206 if (NeedComma) OS << ",";
207 if (isKill()) OS << "kill";
208 if (isDead()) OS << "dead";
213 case MachineOperand::MO_Immediate:
216 case MachineOperand::MO_FPImmediate:
217 if (getFPImm()->getType() == Type::FloatTy) {
218 OS << getFPImm()->getValueAPF().convertToFloat();
220 OS << getFPImm()->getValueAPF().convertToDouble();
223 case MachineOperand::MO_MachineBasicBlock:
225 << ((Value*)getMBB()->getBasicBlock())->getName()
226 << "," << (void*)getMBB() << ">";
228 case MachineOperand::MO_FrameIndex:
229 OS << "<fi#" << getIndex() << ">";
231 case MachineOperand::MO_ConstantPoolIndex:
232 OS << "<cp#" << getIndex();
233 if (getOffset()) OS << "+" << getOffset();
236 case MachineOperand::MO_JumpTableIndex:
237 OS << "<jt#" << getIndex() << ">";
239 case MachineOperand::MO_GlobalAddress:
240 OS << "<ga:" << ((Value*)getGlobal())->getName();
241 if (getOffset()) OS << "+" << getOffset();
244 case MachineOperand::MO_ExternalSymbol:
245 OS << "<es:" << getSymbolName();
246 if (getOffset()) OS << "+" << getOffset();
250 assert(0 && "Unrecognized operand type");
254 //===----------------------------------------------------------------------===//
255 // MachineMemOperand Implementation
256 //===----------------------------------------------------------------------===//
258 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
259 int64_t o, uint64_t s, unsigned int a)
260 : Offset(o), Size(s), V(v),
261 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
262 assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
263 assert((isLoad() || isStore()) && "Not a load/store!");
266 /// Profile - Gather unique data for the object.
268 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
269 ID.AddInteger(Offset);
272 ID.AddInteger(Flags);
275 //===----------------------------------------------------------------------===//
276 // MachineInstr Implementation
277 //===----------------------------------------------------------------------===//
279 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
280 /// TID NULL and no operands.
281 MachineInstr::MachineInstr()
282 : TID(0), NumImplicitOps(0), Parent(0) {
283 // Make sure that we get added to a machine basicblock
284 LeakDetector::addGarbageObject(this);
287 void MachineInstr::addImplicitDefUseOperands() {
288 if (TID->ImplicitDefs)
289 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
290 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
291 if (TID->ImplicitUses)
292 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
293 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
296 /// MachineInstr ctor - This constructor create a MachineInstr and add the
297 /// implicit operands. It reserves space for number of operands specified by
298 /// TargetInstrDesc or the numOperands if it is not zero. (for
299 /// instructions with variable number of operands).
300 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
301 : TID(&tid), NumImplicitOps(0), Parent(0) {
302 if (!NoImp && TID->getImplicitDefs())
303 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
305 if (!NoImp && TID->getImplicitUses())
306 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
308 Operands.reserve(NumImplicitOps + TID->getNumOperands());
310 addImplicitDefUseOperands();
311 // Make sure that we get added to a machine basicblock
312 LeakDetector::addGarbageObject(this);
315 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
316 /// MachineInstr is created and added to the end of the specified basic block.
318 MachineInstr::MachineInstr(MachineBasicBlock *MBB,
319 const TargetInstrDesc &tid)
320 : TID(&tid), NumImplicitOps(0), Parent(0) {
321 assert(MBB && "Cannot use inserting ctor with null basic block!");
322 if (TID->ImplicitDefs)
323 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
325 if (TID->ImplicitUses)
326 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
328 Operands.reserve(NumImplicitOps + TID->getNumOperands());
329 addImplicitDefUseOperands();
330 // Make sure that we get added to a machine basicblock
331 LeakDetector::addGarbageObject(this);
332 MBB->push_back(this); // Add instruction to end of basic block!
335 /// MachineInstr ctor - Copies MachineInstr arg exactly
337 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
338 : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0) {
339 Operands.reserve(MI.getNumOperands());
342 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
343 addOperand(MI.getOperand(i));
344 NumImplicitOps = MI.NumImplicitOps;
346 // Add memory operands.
347 for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
348 j = MI.memoperands_end(); i != j; ++i)
349 addMemOperand(MF, *i);
351 // Set parent to null.
354 LeakDetector::addGarbageObject(this);
357 MachineInstr::~MachineInstr() {
358 LeakDetector::removeGarbageObject(this);
359 assert(MemOperands.empty() &&
360 "MachineInstr being deleted with live memoperands!");
362 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
363 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
364 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
365 "Reg operand def/use list corrupted");
370 /// getRegInfo - If this instruction is embedded into a MachineFunction,
371 /// return the MachineRegisterInfo object for the current function, otherwise
373 MachineRegisterInfo *MachineInstr::getRegInfo() {
374 if (MachineBasicBlock *MBB = getParent())
375 return &MBB->getParent()->getRegInfo();
379 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
380 /// this instruction from their respective use lists. This requires that the
381 /// operands already be on their use lists.
382 void MachineInstr::RemoveRegOperandsFromUseLists() {
383 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
384 if (Operands[i].isReg())
385 Operands[i].RemoveRegOperandFromRegInfo();
389 /// AddRegOperandsToUseLists - Add all of the register operands in
390 /// this instruction from their respective use lists. This requires that the
391 /// operands not be on their use lists yet.
392 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
393 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
394 if (Operands[i].isReg())
395 Operands[i].AddRegOperandToRegInfo(&RegInfo);
400 /// addOperand - Add the specified operand to the instruction. If it is an
401 /// implicit operand, it is added to the end of the operand list. If it is
402 /// an explicit operand it is added at the end of the explicit operand list
403 /// (before the first implicit operand).
404 void MachineInstr::addOperand(const MachineOperand &Op) {
405 bool isImpReg = Op.isReg() && Op.isImplicit();
406 assert((isImpReg || !OperandsComplete()) &&
407 "Trying to add an operand to a machine instr that is already done!");
409 // If we are adding the operand to the end of the list, our job is simpler.
410 // This is true most of the time, so this is a reasonable optimization.
411 if (isImpReg || NumImplicitOps == 0) {
412 // We can only do this optimization if we know that the operand list won't
414 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
415 Operands.push_back(Op);
417 // Set the parent of the operand.
418 Operands.back().ParentMI = this;
420 // If the operand is a register, update the operand's use list.
422 Operands.back().AddRegOperandToRegInfo(getRegInfo());
427 // Otherwise, we have to insert a real operand before any implicit ones.
428 unsigned OpNo = Operands.size()-NumImplicitOps;
430 MachineRegisterInfo *RegInfo = getRegInfo();
432 // If this instruction isn't embedded into a function, then we don't need to
433 // update any operand lists.
435 // Simple insertion, no reginfo update needed for other register operands.
436 Operands.insert(Operands.begin()+OpNo, Op);
437 Operands[OpNo].ParentMI = this;
439 // Do explicitly set the reginfo for this operand though, to ensure the
440 // next/prev fields are properly nulled out.
441 if (Operands[OpNo].isReg())
442 Operands[OpNo].AddRegOperandToRegInfo(0);
444 } else if (Operands.size()+1 <= Operands.capacity()) {
445 // Otherwise, we have to remove register operands from their register use
446 // list, add the operand, then add the register operands back to their use
447 // list. This also must handle the case when the operand list reallocates
448 // to somewhere else.
450 // If insertion of this operand won't cause reallocation of the operand
451 // list, just remove the implicit operands, add the operand, then re-add all
452 // the rest of the operands.
453 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
454 assert(Operands[i].isReg() && "Should only be an implicit reg!");
455 Operands[i].RemoveRegOperandFromRegInfo();
458 // Add the operand. If it is a register, add it to the reg list.
459 Operands.insert(Operands.begin()+OpNo, Op);
460 Operands[OpNo].ParentMI = this;
462 if (Operands[OpNo].isReg())
463 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
465 // Re-add all the implicit ops.
466 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
467 assert(Operands[i].isReg() && "Should only be an implicit reg!");
468 Operands[i].AddRegOperandToRegInfo(RegInfo);
471 // Otherwise, we will be reallocating the operand list. Remove all reg
472 // operands from their list, then readd them after the operand list is
474 RemoveRegOperandsFromUseLists();
476 Operands.insert(Operands.begin()+OpNo, Op);
477 Operands[OpNo].ParentMI = this;
479 // Re-add all the operands.
480 AddRegOperandsToUseLists(*RegInfo);
484 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
485 /// fewer operand than it started with.
487 void MachineInstr::RemoveOperand(unsigned OpNo) {
488 assert(OpNo < Operands.size() && "Invalid operand number");
490 // Special case removing the last one.
491 if (OpNo == Operands.size()-1) {
492 // If needed, remove from the reg def/use list.
493 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
494 Operands.back().RemoveRegOperandFromRegInfo();
500 // Otherwise, we are removing an interior operand. If we have reginfo to
501 // update, remove all operands that will be shifted down from their reg lists,
502 // move everything down, then re-add them.
503 MachineRegisterInfo *RegInfo = getRegInfo();
505 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
506 if (Operands[i].isReg())
507 Operands[i].RemoveRegOperandFromRegInfo();
511 Operands.erase(Operands.begin()+OpNo);
514 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
515 if (Operands[i].isReg())
516 Operands[i].AddRegOperandToRegInfo(RegInfo);
521 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
522 /// referencing arbitrary storage.
523 void MachineInstr::addMemOperand(MachineFunction &MF,
524 const MachineMemOperand &MO) {
525 MemOperands.push_back(MO);
528 /// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
529 void MachineInstr::clearMemOperands(MachineFunction &MF) {
534 /// removeFromParent - This method unlinks 'this' from the containing basic
535 /// block, and returns it, but does not delete it.
536 MachineInstr *MachineInstr::removeFromParent() {
537 assert(getParent() && "Not embedded in a basic block!");
538 getParent()->remove(this);
543 /// eraseFromParent - This method unlinks 'this' from the containing basic
544 /// block, and deletes it.
545 void MachineInstr::eraseFromParent() {
546 assert(getParent() && "Not embedded in a basic block!");
547 getParent()->erase(this);
551 /// OperandComplete - Return true if it's illegal to add a new operand
553 bool MachineInstr::OperandsComplete() const {
554 unsigned short NumOperands = TID->getNumOperands();
555 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
556 return true; // Broken: we have all the operands of this instruction!
560 /// getNumExplicitOperands - Returns the number of non-implicit operands.
562 unsigned MachineInstr::getNumExplicitOperands() const {
563 unsigned NumOperands = TID->getNumOperands();
564 if (!TID->isVariadic())
567 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
568 const MachineOperand &MO = getOperand(NumOperands);
569 if (!MO.isReg() || !MO.isImplicit())
576 /// isLabel - Returns true if the MachineInstr represents a label.
578 bool MachineInstr::isLabel() const {
579 return getOpcode() == TargetInstrInfo::DBG_LABEL ||
580 getOpcode() == TargetInstrInfo::EH_LABEL ||
581 getOpcode() == TargetInstrInfo::GC_LABEL;
584 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
586 bool MachineInstr::isDebugLabel() const {
587 return getOpcode() == TargetInstrInfo::DBG_LABEL;
590 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
591 /// the specific register or -1 if it is not found. It further tightening
592 /// the search criteria to a use that kills the register if isKill is true.
593 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
594 const TargetRegisterInfo *TRI) const {
595 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
596 const MachineOperand &MO = getOperand(i);
597 if (!MO.isReg() || !MO.isUse())
599 unsigned MOReg = MO.getReg();
604 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
605 TargetRegisterInfo::isPhysicalRegister(Reg) &&
606 TRI->isSubRegister(MOReg, Reg)))
607 if (!isKill || MO.isKill())
613 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
614 /// the specified register or -1 if it is not found. If isDead is true, defs
615 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
616 /// also checks if there is a def of a super-register.
617 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
618 const TargetRegisterInfo *TRI) const {
619 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
620 const MachineOperand &MO = getOperand(i);
621 if (!MO.isReg() || !MO.isDef())
623 unsigned MOReg = MO.getReg();
626 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
627 TargetRegisterInfo::isPhysicalRegister(Reg) &&
628 TRI->isSubRegister(MOReg, Reg)))
629 if (!isDead || MO.isDead())
635 /// findFirstPredOperandIdx() - Find the index of the first operand in the
636 /// operand list that is used to represent the predicate. It returns -1 if
638 int MachineInstr::findFirstPredOperandIdx() const {
639 const TargetInstrDesc &TID = getDesc();
640 if (TID.isPredicable()) {
641 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
642 if (TID.OpInfo[i].isPredicate())
649 /// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
650 /// check if the register def is a re-definition due to two addr elimination.
651 bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const{
652 const TargetInstrDesc &TID = getDesc();
653 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
654 const MachineOperand &MO = getOperand(i);
655 if (MO.isReg() && MO.isUse() && MO.getReg() == Reg &&
656 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
662 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
664 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
665 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
666 const MachineOperand &MO = MI->getOperand(i);
667 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
669 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
670 MachineOperand &MOp = getOperand(j);
671 if (!MOp.isIdenticalTo(MO))
682 /// copyPredicates - Copies predicate operand(s) from MI.
683 void MachineInstr::copyPredicates(const MachineInstr *MI) {
684 const TargetInstrDesc &TID = MI->getDesc();
685 if (!TID.isPredicable())
687 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
688 if (TID.OpInfo[i].isPredicate()) {
689 // Predicated operands must be last operands.
690 addOperand(MI->getOperand(i));
695 /// isSafeToMove - Return true if it is safe to move this instruction. If
696 /// SawStore is set to true, it means that there is a store (or call) between
697 /// the instruction's location and its intended destination.
698 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) {
699 // Ignore stuff that we obviously can't move.
700 if (TID->mayStore() || TID->isCall()) {
704 if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects())
707 // See if this instruction does a load. If so, we have to guarantee that the
708 // loaded value doesn't change between the load and the its intended
709 // destination. The check for isInvariantLoad gives the targe the chance to
710 // classify the load as always returning a constant, e.g. a constant pool
712 if (TID->mayLoad() && !TII->isInvariantLoad(this))
713 // Otherwise, this is a real load. If there is a store between the load and
714 // end of block, or if the laod is volatile, we can't move it.
715 return !SawStore && !hasVolatileMemoryRef();
720 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
721 /// instruction which defined the specified register instead of copying it.
722 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, unsigned DstReg) {
723 bool SawStore = false;
724 if (!getDesc().isRematerializable() ||
725 !TII->isTriviallyReMaterializable(this) ||
726 !isSafeToMove(TII, SawStore))
728 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
729 MachineOperand &MO = getOperand(i);
732 // FIXME: For now, do not remat any instruction with register operands.
733 // Later on, we can loosen the restriction is the register operands have
734 // not been modified between the def and use. Note, this is different from
735 // MachineSink because the code is no longer in two-address form (at least
739 else if (!MO.isDead() && MO.getReg() != DstReg)
745 /// hasVolatileMemoryRef - Return true if this instruction may have a
746 /// volatile memory reference, or if the information describing the
747 /// memory reference is not available. Return false if it is known to
748 /// have no volatile memory references.
749 bool MachineInstr::hasVolatileMemoryRef() const {
750 // An instruction known never to access memory won't have a volatile access.
751 if (!TID->mayStore() &&
754 !TID->hasUnmodeledSideEffects())
757 // Otherwise, if the instruction has no memory reference information,
758 // conservatively assume it wasn't preserved.
759 if (memoperands_empty())
762 // Check the memory reference information for volatile references.
763 for (std::list<MachineMemOperand>::const_iterator I = memoperands_begin(),
764 E = memoperands_end(); I != E; ++I)
771 void MachineInstr::dump() const {
772 cerr << " " << *this;
775 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
776 raw_os_ostream RawOS(OS);
780 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
781 // Specialize printing if op#0 is definition
782 unsigned StartOp = 0;
783 if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
784 getOperand(0).print(OS, TM);
786 ++StartOp; // Don't print this operand again!
789 OS << getDesc().getName();
791 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
795 getOperand(i).print(OS, TM);
798 if (!memoperands_empty()) {
800 for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(),
801 e = memoperands_end(); i != e; ++i) {
802 const MachineMemOperand &MRO = *i;
803 const Value *V = MRO.getValue();
805 assert((MRO.isLoad() || MRO.isStore()) &&
806 "SV has to be a load, store or both.");
808 if (MRO.isVolatile())
816 OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
820 else if (!V->getName().empty())
822 else if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
827 OS << " + " << MRO.getOffset() << "]";
834 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
835 const TargetRegisterInfo *RegInfo,
836 bool AddIfNotFound) {
837 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
838 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
840 SmallVector<unsigned,4> DeadOps;
841 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
842 MachineOperand &MO = getOperand(i);
843 if (!MO.isReg() || !MO.isUse())
845 unsigned Reg = MO.getReg();
849 if (Reg == IncomingReg) {
852 // The register is already marked kill.
857 } else if (hasAliases && MO.isKill() &&
858 TargetRegisterInfo::isPhysicalRegister(Reg)) {
859 // A super-register kill already exists.
860 if (RegInfo->isSuperRegister(IncomingReg, Reg))
862 if (RegInfo->isSubRegister(IncomingReg, Reg))
863 DeadOps.push_back(i);
867 // Trim unneeded kill operands.
868 while (!DeadOps.empty()) {
869 unsigned OpIdx = DeadOps.back();
870 if (getOperand(OpIdx).isImplicit())
871 RemoveOperand(OpIdx);
873 getOperand(OpIdx).setIsKill(false);
877 // If not found, this means an alias of one of the operands is killed. Add a
878 // new implicit operand if required.
879 if (!Found && AddIfNotFound) {
880 addOperand(MachineOperand::CreateReg(IncomingReg,
889 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
890 const TargetRegisterInfo *RegInfo,
891 bool AddIfNotFound) {
892 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
893 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
895 SmallVector<unsigned,4> DeadOps;
896 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
897 MachineOperand &MO = getOperand(i);
898 if (!MO.isReg() || !MO.isDef())
900 unsigned Reg = MO.getReg();
904 if (Reg == IncomingReg) {
907 // The register is already marked dead.
912 } else if (hasAliases && MO.isDead() &&
913 TargetRegisterInfo::isPhysicalRegister(Reg)) {
914 // There exists a super-register that's marked dead.
915 if (RegInfo->isSuperRegister(IncomingReg, Reg))
917 if (RegInfo->getSubRegisters(IncomingReg) &&
918 RegInfo->getSuperRegisters(Reg) &&
919 RegInfo->isSubRegister(IncomingReg, Reg))
920 DeadOps.push_back(i);
924 // Trim unneeded dead operands.
925 while (!DeadOps.empty()) {
926 unsigned OpIdx = DeadOps.back();
927 if (getOperand(OpIdx).isImplicit())
928 RemoveOperand(OpIdx);
930 getOperand(OpIdx).setIsDead(false);
934 // If not found, this means an alias of one of the operands is dead. Add a
935 // new implicit operand if required.
936 if (!Found && AddIfNotFound) {
937 addOperand(MachineOperand::CreateReg(IncomingReg,