1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Function.h"
17 #include "llvm/InlineAsm.h"
18 #include "llvm/LLVMContext.h"
19 #include "llvm/Metadata.h"
20 #include "llvm/Module.h"
21 #include "llvm/Type.h"
22 #include "llvm/Value.h"
23 #include "llvm/Assembly/Writer.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCSymbol.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Analysis/AliasAnalysis.h"
36 #include "llvm/Analysis/DebugInfo.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/LeakDetector.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/FoldingSet.h"
45 //===----------------------------------------------------------------------===//
46 // MachineOperand Implementation
47 //===----------------------------------------------------------------------===//
49 /// AddRegOperandToRegInfo - Add this register operand to the specified
50 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
51 /// explicitly nulled out.
52 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
53 assert(isReg() && "Can only add reg operand to use lists");
55 // If the reginfo pointer is null, just explicitly null out or next/prev
56 // pointers, to ensure they are not garbage.
58 Contents.Reg.Prev = 0;
59 Contents.Reg.Next = 0;
63 // Otherwise, add this operand to the head of the registers use/def list.
64 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
66 // For SSA values, we prefer to keep the definition at the start of the list.
67 // we do this by skipping over the definition if it is at the head of the
69 if (*Head && (*Head)->isDef())
70 Head = &(*Head)->Contents.Reg.Next;
72 Contents.Reg.Next = *Head;
73 if (Contents.Reg.Next) {
74 assert(getReg() == Contents.Reg.Next->getReg() &&
75 "Different regs on the same list!");
76 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
79 Contents.Reg.Prev = Head;
83 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
84 /// MachineRegisterInfo it is linked with.
85 void MachineOperand::RemoveRegOperandFromRegInfo() {
86 assert(isOnRegUseList() && "Reg operand is not on a use list");
87 // Unlink this from the doubly linked list of operands.
88 MachineOperand *NextOp = Contents.Reg.Next;
89 *Contents.Reg.Prev = NextOp;
91 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
92 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
94 Contents.Reg.Prev = 0;
95 Contents.Reg.Next = 0;
98 void MachineOperand::setReg(unsigned Reg) {
99 if (getReg() == Reg) return; // No change.
101 // Otherwise, we have to change the register. If this operand is embedded
102 // into a machine function, we need to update the old and new register's
104 if (MachineInstr *MI = getParent())
105 if (MachineBasicBlock *MBB = MI->getParent())
106 if (MachineFunction *MF = MBB->getParent()) {
107 RemoveRegOperandFromRegInfo();
108 SmallContents.RegNo = Reg;
109 AddRegOperandToRegInfo(&MF->getRegInfo());
113 // Otherwise, just change the register, no problem. :)
114 SmallContents.RegNo = Reg;
117 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
118 const TargetRegisterInfo &TRI) {
119 assert(TargetRegisterInfo::isVirtualRegister(Reg));
120 if (SubIdx && getSubReg())
121 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
127 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
128 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
130 Reg = TRI.getSubReg(Reg, getSubReg());
131 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
132 // That won't happen in legal code.
138 /// ChangeToImmediate - Replace this operand with a new immediate operand of
139 /// the specified value. If an operand is known to be an immediate already,
140 /// the setImm method should be used.
141 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
142 // If this operand is currently a register operand, and if this is in a
143 // function, deregister the operand from the register's use/def list.
144 if (isReg() && getParent() && getParent()->getParent() &&
145 getParent()->getParent()->getParent())
146 RemoveRegOperandFromRegInfo();
148 OpKind = MO_Immediate;
149 Contents.ImmVal = ImmVal;
152 /// ChangeToRegister - Replace this operand with a new register operand of
153 /// the specified value. If an operand is known to be an register already,
154 /// the setReg method should be used.
155 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
156 bool isKill, bool isDead, bool isUndef,
158 // If this operand is already a register operand, use setReg to update the
159 // register's use/def lists.
161 assert(!isEarlyClobber());
164 // Otherwise, change this to a register and set the reg#.
165 OpKind = MO_Register;
166 SmallContents.RegNo = Reg;
168 // If this operand is embedded in a function, add the operand to the
169 // register's use/def list.
170 if (MachineInstr *MI = getParent())
171 if (MachineBasicBlock *MBB = MI->getParent())
172 if (MachineFunction *MF = MBB->getParent())
173 AddRegOperandToRegInfo(&MF->getRegInfo());
181 IsInternalRead = false;
182 IsEarlyClobber = false;
187 /// isIdenticalTo - Return true if this operand is identical to the specified
189 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
190 if (getType() != Other.getType() ||
191 getTargetFlags() != Other.getTargetFlags())
195 case MachineOperand::MO_Register:
196 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
197 getSubReg() == Other.getSubReg();
198 case MachineOperand::MO_Immediate:
199 return getImm() == Other.getImm();
200 case MachineOperand::MO_CImmediate:
201 return getCImm() == Other.getCImm();
202 case MachineOperand::MO_FPImmediate:
203 return getFPImm() == Other.getFPImm();
204 case MachineOperand::MO_MachineBasicBlock:
205 return getMBB() == Other.getMBB();
206 case MachineOperand::MO_FrameIndex:
207 return getIndex() == Other.getIndex();
208 case MachineOperand::MO_ConstantPoolIndex:
209 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
210 case MachineOperand::MO_JumpTableIndex:
211 return getIndex() == Other.getIndex();
212 case MachineOperand::MO_GlobalAddress:
213 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
214 case MachineOperand::MO_ExternalSymbol:
215 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
216 getOffset() == Other.getOffset();
217 case MachineOperand::MO_BlockAddress:
218 return getBlockAddress() == Other.getBlockAddress();
219 case MachineOperand::MO_MCSymbol:
220 return getMCSymbol() == Other.getMCSymbol();
221 case MachineOperand::MO_Metadata:
222 return getMetadata() == Other.getMetadata();
224 llvm_unreachable("Invalid machine operand type");
227 /// print - Print the specified machine operand.
229 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
230 // If the instruction is embedded into a basic block, we can find the
231 // target info for the instruction.
233 if (const MachineInstr *MI = getParent())
234 if (const MachineBasicBlock *MBB = MI->getParent())
235 if (const MachineFunction *MF = MBB->getParent())
236 TM = &MF->getTarget();
237 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
240 case MachineOperand::MO_Register:
241 OS << PrintReg(getReg(), TRI, getSubReg());
243 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
244 isInternalRead() || isEarlyClobber()) {
246 bool NeedComma = false;
248 if (NeedComma) OS << ',';
249 if (isEarlyClobber())
250 OS << "earlyclobber,";
255 } else if (isImplicit()) {
260 if (isKill() || isDead() || isUndef() || isInternalRead()) {
261 if (NeedComma) OS << ',';
272 if (NeedComma) OS << ',';
276 if (isInternalRead()) {
277 if (NeedComma) OS << ',';
285 case MachineOperand::MO_Immediate:
288 case MachineOperand::MO_CImmediate:
289 getCImm()->getValue().print(OS, false);
291 case MachineOperand::MO_FPImmediate:
292 if (getFPImm()->getType()->isFloatTy())
293 OS << getFPImm()->getValueAPF().convertToFloat();
295 OS << getFPImm()->getValueAPF().convertToDouble();
297 case MachineOperand::MO_MachineBasicBlock:
298 OS << "<BB#" << getMBB()->getNumber() << ">";
300 case MachineOperand::MO_FrameIndex:
301 OS << "<fi#" << getIndex() << '>';
303 case MachineOperand::MO_ConstantPoolIndex:
304 OS << "<cp#" << getIndex();
305 if (getOffset()) OS << "+" << getOffset();
308 case MachineOperand::MO_JumpTableIndex:
309 OS << "<jt#" << getIndex() << '>';
311 case MachineOperand::MO_GlobalAddress:
313 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
314 if (getOffset()) OS << "+" << getOffset();
317 case MachineOperand::MO_ExternalSymbol:
318 OS << "<es:" << getSymbolName();
319 if (getOffset()) OS << "+" << getOffset();
322 case MachineOperand::MO_BlockAddress:
324 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
327 case MachineOperand::MO_Metadata:
329 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
332 case MachineOperand::MO_MCSymbol:
333 OS << "<MCSym=" << *getMCSymbol() << '>';
337 if (unsigned TF = getTargetFlags())
338 OS << "[TF=" << TF << ']';
341 //===----------------------------------------------------------------------===//
342 // MachineMemOperand Implementation
343 //===----------------------------------------------------------------------===//
345 /// getAddrSpace - Return the LLVM IR address space number that this pointer
347 unsigned MachinePointerInfo::getAddrSpace() const {
348 if (V == 0) return 0;
349 return cast<PointerType>(V->getType())->getAddressSpace();
352 /// getConstantPool - Return a MachinePointerInfo record that refers to the
354 MachinePointerInfo MachinePointerInfo::getConstantPool() {
355 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
358 /// getFixedStack - Return a MachinePointerInfo record that refers to the
359 /// the specified FrameIndex.
360 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
361 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
364 MachinePointerInfo MachinePointerInfo::getJumpTable() {
365 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
368 MachinePointerInfo MachinePointerInfo::getGOT() {
369 return MachinePointerInfo(PseudoSourceValue::getGOT());
372 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
373 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
376 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
377 uint64_t s, unsigned int a,
378 const MDNode *TBAAInfo)
379 : PtrInfo(ptrinfo), Size(s),
380 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
382 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
383 "invalid pointer value");
384 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
385 assert((isLoad() || isStore()) && "Not a load/store!");
388 /// Profile - Gather unique data for the object.
390 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
391 ID.AddInteger(getOffset());
393 ID.AddPointer(getValue());
394 ID.AddInteger(Flags);
397 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
398 // The Value and Offset may differ due to CSE. But the flags and size
399 // should be the same.
400 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
401 assert(MMO->getSize() == getSize() && "Size mismatch!");
403 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
404 // Update the alignment value.
405 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
406 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
407 // Also update the base and offset, because the new alignment may
408 // not be applicable with the old ones.
409 PtrInfo = MMO->PtrInfo;
413 /// getAlignment - Return the minimum known alignment in bytes of the
414 /// actual memory reference.
415 uint64_t MachineMemOperand::getAlignment() const {
416 return MinAlign(getBaseAlignment(), getOffset());
419 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
420 assert((MMO.isLoad() || MMO.isStore()) &&
421 "SV has to be a load, store or both.");
423 if (MMO.isVolatile())
432 // Print the address information.
437 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
439 // If the alignment of the memory reference itself differs from the alignment
440 // of the base pointer, print the base alignment explicitly, next to the base
442 if (MMO.getBaseAlignment() != MMO.getAlignment())
443 OS << "(align=" << MMO.getBaseAlignment() << ")";
445 if (MMO.getOffset() != 0)
446 OS << "+" << MMO.getOffset();
449 // Print the alignment of the reference.
450 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
451 MMO.getBaseAlignment() != MMO.getSize())
452 OS << "(align=" << MMO.getAlignment() << ")";
455 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
457 if (TBAAInfo->getNumOperands() > 0)
458 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
464 // Print nontemporal info.
465 if (MMO.isNonTemporal())
466 OS << "(nontemporal)";
471 //===----------------------------------------------------------------------===//
472 // MachineInstr Implementation
473 //===----------------------------------------------------------------------===//
475 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
476 /// MCID NULL and no operands.
477 MachineInstr::MachineInstr()
478 : MCID(0), Flags(0), AsmPrinterFlags(0),
479 MemRefs(0), MemRefsEnd(0),
481 // Make sure that we get added to a machine basicblock
482 LeakDetector::addGarbageObject(this);
485 void MachineInstr::addImplicitDefUseOperands() {
486 if (MCID->ImplicitDefs)
487 for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs)
488 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
489 if (MCID->ImplicitUses)
490 for (const unsigned *ImpUses = MCID->ImplicitUses; *ImpUses; ++ImpUses)
491 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
494 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
495 /// implicit operands. It reserves space for the number of operands specified by
497 MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
498 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
499 MemRefs(0), MemRefsEnd(0), Parent(0) {
500 unsigned NumImplicitOps = 0;
502 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
503 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
505 addImplicitDefUseOperands();
506 // Make sure that we get added to a machine basicblock
507 LeakDetector::addGarbageObject(this);
510 /// MachineInstr ctor - As above, but with a DebugLoc.
511 MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
513 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
514 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
515 unsigned NumImplicitOps = 0;
517 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
518 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
520 addImplicitDefUseOperands();
521 // Make sure that we get added to a machine basicblock
522 LeakDetector::addGarbageObject(this);
525 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
526 /// that the MachineInstr is created and added to the end of the specified
528 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
529 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
530 MemRefs(0), MemRefsEnd(0), Parent(0) {
531 assert(MBB && "Cannot use inserting ctor with null basic block!");
532 unsigned NumImplicitOps =
533 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
534 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
535 addImplicitDefUseOperands();
536 // Make sure that we get added to a machine basicblock
537 LeakDetector::addGarbageObject(this);
538 MBB->push_back(this); // Add instruction to end of basic block!
541 /// MachineInstr ctor - As above, but with a DebugLoc.
543 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
544 const MCInstrDesc &tid)
545 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
546 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
547 assert(MBB && "Cannot use inserting ctor with null basic block!");
548 unsigned NumImplicitOps =
549 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
550 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
551 addImplicitDefUseOperands();
552 // Make sure that we get added to a machine basicblock
553 LeakDetector::addGarbageObject(this);
554 MBB->push_back(this); // Add instruction to end of basic block!
557 /// MachineInstr ctor - Copies MachineInstr arg exactly
559 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
560 : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
561 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
562 Parent(0), debugLoc(MI.getDebugLoc()) {
563 Operands.reserve(MI.getNumOperands());
566 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
567 addOperand(MI.getOperand(i));
569 // Copy all the flags.
572 // Set parent to null.
575 LeakDetector::addGarbageObject(this);
578 MachineInstr::~MachineInstr() {
579 LeakDetector::removeGarbageObject(this);
581 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
582 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
583 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
584 "Reg operand def/use list corrupted");
589 /// getRegInfo - If this instruction is embedded into a MachineFunction,
590 /// return the MachineRegisterInfo object for the current function, otherwise
592 MachineRegisterInfo *MachineInstr::getRegInfo() {
593 if (MachineBasicBlock *MBB = getParent())
594 return &MBB->getParent()->getRegInfo();
598 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
599 /// this instruction from their respective use lists. This requires that the
600 /// operands already be on their use lists.
601 void MachineInstr::RemoveRegOperandsFromUseLists() {
602 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
603 if (Operands[i].isReg())
604 Operands[i].RemoveRegOperandFromRegInfo();
608 /// AddRegOperandsToUseLists - Add all of the register operands in
609 /// this instruction from their respective use lists. This requires that the
610 /// operands not be on their use lists yet.
611 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
612 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
613 if (Operands[i].isReg())
614 Operands[i].AddRegOperandToRegInfo(&RegInfo);
619 /// addOperand - Add the specified operand to the instruction. If it is an
620 /// implicit operand, it is added to the end of the operand list. If it is
621 /// an explicit operand it is added at the end of the explicit operand list
622 /// (before the first implicit operand).
623 void MachineInstr::addOperand(const MachineOperand &Op) {
624 assert(MCID && "Cannot add operands before providing an instr descriptor");
625 bool isImpReg = Op.isReg() && Op.isImplicit();
626 MachineRegisterInfo *RegInfo = getRegInfo();
628 // If the Operands backing store is reallocated, all register operands must
629 // be removed and re-added to RegInfo. It is storing pointers to operands.
630 bool Reallocate = RegInfo &&
631 !Operands.empty() && Operands.size() == Operands.capacity();
633 // Find the insert location for the new operand. Implicit registers go at
634 // the end, everything goes before the implicit regs.
635 unsigned OpNo = Operands.size();
637 // Remove all the implicit operands from RegInfo if they need to be shifted.
638 // FIXME: Allow mixed explicit and implicit operands on inline asm.
639 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
640 // implicit-defs, but they must not be moved around. See the FIXME in
642 if (!isImpReg && !isInlineAsm()) {
643 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
646 Operands[OpNo].RemoveRegOperandFromRegInfo();
650 // OpNo now points as the desired insertion point. Unless this is a variadic
651 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
652 assert((isImpReg || MCID->isVariadic() || OpNo < MCID->getNumOperands()) &&
653 "Trying to add an operand to a machine instr that is already done!");
655 // All operands from OpNo have been removed from RegInfo. If the Operands
656 // backing store needs to be reallocated, we also need to remove any other
657 // register operands.
659 for (unsigned i = 0; i != OpNo; ++i)
660 if (Operands[i].isReg())
661 Operands[i].RemoveRegOperandFromRegInfo();
663 // Insert the new operand at OpNo.
664 Operands.insert(Operands.begin() + OpNo, Op);
665 Operands[OpNo].ParentMI = this;
667 // The Operands backing store has now been reallocated, so we can re-add the
668 // operands before OpNo.
670 for (unsigned i = 0; i != OpNo; ++i)
671 if (Operands[i].isReg())
672 Operands[i].AddRegOperandToRegInfo(RegInfo);
674 // When adding a register operand, tell RegInfo about it.
675 if (Operands[OpNo].isReg()) {
676 // Add the new operand to RegInfo, even when RegInfo is NULL.
677 // This will initialize the linked list pointers.
678 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
679 // If the register operand is flagged as early, mark the operand as such.
680 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
681 Operands[OpNo].setIsEarlyClobber(true);
684 // Re-add all the implicit ops.
686 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
687 assert(Operands[i].isReg() && "Should only be an implicit reg!");
688 Operands[i].AddRegOperandToRegInfo(RegInfo);
693 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
694 /// fewer operand than it started with.
696 void MachineInstr::RemoveOperand(unsigned OpNo) {
697 assert(OpNo < Operands.size() && "Invalid operand number");
699 // Special case removing the last one.
700 if (OpNo == Operands.size()-1) {
701 // If needed, remove from the reg def/use list.
702 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
703 Operands.back().RemoveRegOperandFromRegInfo();
709 // Otherwise, we are removing an interior operand. If we have reginfo to
710 // update, remove all operands that will be shifted down from their reg lists,
711 // move everything down, then re-add them.
712 MachineRegisterInfo *RegInfo = getRegInfo();
714 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
715 if (Operands[i].isReg())
716 Operands[i].RemoveRegOperandFromRegInfo();
720 Operands.erase(Operands.begin()+OpNo);
723 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
724 if (Operands[i].isReg())
725 Operands[i].AddRegOperandToRegInfo(RegInfo);
730 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
731 /// This function should be used only occasionally. The setMemRefs function
732 /// is the primary method for setting up a MachineInstr's MemRefs list.
733 void MachineInstr::addMemOperand(MachineFunction &MF,
734 MachineMemOperand *MO) {
735 mmo_iterator OldMemRefs = MemRefs;
736 mmo_iterator OldMemRefsEnd = MemRefsEnd;
738 size_t NewNum = (MemRefsEnd - MemRefs) + 1;
739 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
740 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
742 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
743 NewMemRefs[NewNum - 1] = MO;
745 MemRefs = NewMemRefs;
746 MemRefsEnd = NewMemRefsEnd;
750 MachineInstr::hasProperty(unsigned MCFlag, QueryType Type) const {
751 if (Type == IgnoreBundle || !isBundle())
752 return getDesc().getFlags() & (1 << MCFlag);
754 const MachineBasicBlock *MBB = getParent();
755 MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
756 while (MII != MBB->end() && MII->isInsideBundle()) {
757 if (MII->getDesc().getFlags() & (1 << MCFlag)) {
758 if (Type == AnyInBundle)
761 if (Type == AllInBundle)
767 return Type == AllInBundle;
770 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
771 MICheckType Check) const {
772 // If opcodes or number of operands are not the same then the two
773 // instructions are obviously not identical.
774 if (Other->getOpcode() != getOpcode() ||
775 Other->getNumOperands() != getNumOperands())
779 // Both instructions are bundles, compare MIs inside the bundle.
780 MachineBasicBlock::const_instr_iterator I1 = *this;
781 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
782 MachineBasicBlock::const_instr_iterator I2 = *Other;
783 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
784 while (++I1 != E1 && I1->isInsideBundle()) {
786 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
791 // Check operands to make sure they match.
792 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
793 const MachineOperand &MO = getOperand(i);
794 const MachineOperand &OMO = Other->getOperand(i);
796 if (!MO.isIdenticalTo(OMO))
801 // Clients may or may not want to ignore defs when testing for equality.
802 // For example, machine CSE pass only cares about finding common
803 // subexpressions, so it's safe to ignore virtual register defs.
805 if (Check == IgnoreDefs)
807 else if (Check == IgnoreVRegDefs) {
808 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
809 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
810 if (MO.getReg() != OMO.getReg())
813 if (!MO.isIdenticalTo(OMO))
815 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
819 if (!MO.isIdenticalTo(OMO))
821 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
825 // If DebugLoc does not match then two dbg.values are not identical.
827 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
828 && getDebugLoc() != Other->getDebugLoc())
833 /// removeFromParent - This method unlinks 'this' from the containing basic
834 /// block, and returns it, but does not delete it.
835 MachineInstr *MachineInstr::removeFromParent() {
836 assert(getParent() && "Not embedded in a basic block!");
838 // If it's a bundle then remove the MIs inside the bundle as well.
840 MachineBasicBlock *MBB = getParent();
841 MachineBasicBlock::instr_iterator MII = *this; ++MII;
842 MachineBasicBlock::instr_iterator E = MBB->instr_end();
843 while (MII != E && MII->isInsideBundle()) {
844 MachineInstr *MI = &*MII;
849 getParent()->remove(this);
854 /// eraseFromParent - This method unlinks 'this' from the containing basic
855 /// block, and deletes it.
856 void MachineInstr::eraseFromParent() {
857 assert(getParent() && "Not embedded in a basic block!");
858 // If it's a bundle then remove the MIs inside the bundle as well.
860 MachineBasicBlock *MBB = getParent();
861 MachineBasicBlock::instr_iterator MII = *this; ++MII;
862 MachineBasicBlock::instr_iterator E = MBB->instr_end();
863 while (MII != E && MII->isInsideBundle()) {
864 MachineInstr *MI = &*MII;
869 getParent()->erase(this);
873 /// getNumExplicitOperands - Returns the number of non-implicit operands.
875 unsigned MachineInstr::getNumExplicitOperands() const {
876 unsigned NumOperands = MCID->getNumOperands();
877 if (!MCID->isVariadic())
880 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
881 const MachineOperand &MO = getOperand(i);
882 if (!MO.isReg() || !MO.isImplicit())
888 bool MachineInstr::isStackAligningInlineAsm() const {
890 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
891 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
897 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
898 unsigned *GroupNo) const {
899 assert(isInlineAsm() && "Expected an inline asm instruction");
900 assert(OpIdx < getNumOperands() && "OpIdx out of range");
902 // Ignore queries about the initial operands.
903 if (OpIdx < InlineAsm::MIOp_FirstOperand)
908 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
910 const MachineOperand &FlagMO = getOperand(i);
911 // If we reach the implicit register operands, stop looking.
914 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
915 if (i + NumOps > OpIdx) {
925 const TargetRegisterClass*
926 MachineInstr::getRegClassConstraint(unsigned OpIdx,
927 const TargetInstrInfo *TII,
928 const TargetRegisterInfo *TRI) const {
929 // Most opcodes have fixed constraints in their MCInstrDesc.
931 return TII->getRegClass(getDesc(), OpIdx, TRI);
933 if (!getOperand(OpIdx).isReg())
936 // For tied uses on inline asm, get the constraint from the def.
938 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
941 // Inline asm stores register class constraints in the flag word.
942 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
946 unsigned Flag = getOperand(FlagIdx).getImm();
948 if (InlineAsm::hasRegClassConstraint(Flag, RCID))
949 return TRI->getRegClass(RCID);
951 // Assume that all registers in a memory operand are pointers.
952 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
953 return TRI->getPointerRegClass();
958 /// getBundleSize - Return the number of instructions inside the MI bundle.
959 unsigned MachineInstr::getBundleSize() const {
960 assert(isBundle() && "Expecting a bundle");
962 MachineBasicBlock::const_instr_iterator I = *this;
964 while ((++I)->isInsideBundle()) {
967 assert(Size > 1 && "Malformed bundle");
972 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
973 /// the specific register or -1 if it is not found. It further tightens
974 /// the search criteria to a use that kills the register if isKill is true.
975 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
976 const TargetRegisterInfo *TRI) const {
977 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
978 const MachineOperand &MO = getOperand(i);
979 if (!MO.isReg() || !MO.isUse())
981 unsigned MOReg = MO.getReg();
986 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
987 TargetRegisterInfo::isPhysicalRegister(Reg) &&
988 TRI->isSubRegister(MOReg, Reg)))
989 if (!isKill || MO.isKill())
995 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
996 /// indicating if this instruction reads or writes Reg. This also considers
999 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1000 SmallVectorImpl<unsigned> *Ops) const {
1001 bool PartDef = false; // Partial redefine.
1002 bool FullDef = false; // Full define.
1005 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1006 const MachineOperand &MO = getOperand(i);
1007 if (!MO.isReg() || MO.getReg() != Reg)
1012 Use |= !MO.isUndef();
1013 else if (MO.getSubReg() && !MO.isUndef())
1014 // A partial <def,undef> doesn't count as reading the register.
1019 // A partial redefine uses Reg unless there is also a full define.
1020 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1023 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1024 /// the specified register or -1 if it is not found. If isDead is true, defs
1025 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1026 /// also checks if there is a def of a super-register.
1028 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1029 const TargetRegisterInfo *TRI) const {
1030 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1031 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1032 const MachineOperand &MO = getOperand(i);
1033 if (!MO.isReg() || !MO.isDef())
1035 unsigned MOReg = MO.getReg();
1036 bool Found = (MOReg == Reg);
1037 if (!Found && TRI && isPhys &&
1038 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1040 Found = TRI->regsOverlap(MOReg, Reg);
1042 Found = TRI->isSubRegister(MOReg, Reg);
1044 if (Found && (!isDead || MO.isDead()))
1050 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1051 /// operand list that is used to represent the predicate. It returns -1 if
1053 int MachineInstr::findFirstPredOperandIdx() const {
1054 // Don't call MCID.findFirstPredOperandIdx() because this variant
1055 // is sometimes called on an instruction that's not yet complete, and
1056 // so the number of operands is less than the MCID indicates. In
1057 // particular, the PTX target does this.
1058 const MCInstrDesc &MCID = getDesc();
1059 if (MCID.isPredicable()) {
1060 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1061 if (MCID.OpInfo[i].isPredicate())
1068 /// isRegTiedToUseOperand - Given the index of a register def operand,
1069 /// check if the register def is tied to a source operand, due to either
1070 /// two-address elimination or inline assembly constraints. Returns the
1071 /// first tied use operand index by reference is UseOpIdx is not null.
1073 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
1074 if (isInlineAsm()) {
1075 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
1076 const MachineOperand &MO = getOperand(DefOpIdx);
1077 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
1079 // Determine the actual operand index that corresponds to this index.
1081 int FlagIdx = findInlineAsmFlagIdx(DefOpIdx, &DefNo);
1085 // Which part of the group is DefOpIdx?
1086 unsigned DefPart = DefOpIdx - (FlagIdx + 1);
1088 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
1090 const MachineOperand &FMO = getOperand(i);
1093 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
1096 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
1099 *UseOpIdx = (unsigned)i + 1 + DefPart;
1106 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
1107 const MCInstrDesc &MCID = getDesc();
1108 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
1109 const MachineOperand &MO = getOperand(i);
1110 if (MO.isReg() && MO.isUse() &&
1111 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
1113 *UseOpIdx = (unsigned)i;
1120 /// isRegTiedToDefOperand - Return true if the operand of the specified index
1121 /// is a register use and it is tied to an def operand. It also returns the def
1122 /// operand index by reference.
1124 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
1125 if (isInlineAsm()) {
1126 const MachineOperand &MO = getOperand(UseOpIdx);
1127 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
1130 // Find the flag operand corresponding to UseOpIdx
1131 int FlagIdx = findInlineAsmFlagIdx(UseOpIdx);
1135 const MachineOperand &UFMO = getOperand(FlagIdx);
1137 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1141 unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1142 // Remember to adjust the index. First operand is asm string, second is
1143 // the HasSideEffects and AlignStack bits, then there is a flag for each.
1145 const MachineOperand &FMO = getOperand(DefIdx);
1146 assert(FMO.isImm());
1147 // Skip over this def.
1148 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1151 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1157 const MCInstrDesc &MCID = getDesc();
1158 if (UseOpIdx >= MCID.getNumOperands())
1160 const MachineOperand &MO = getOperand(UseOpIdx);
1161 if (!MO.isReg() || !MO.isUse())
1163 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
1167 *DefOpIdx = (unsigned)DefIdx;
1171 /// clearKillInfo - Clears kill flags on all operands.
1173 void MachineInstr::clearKillInfo() {
1174 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1175 MachineOperand &MO = getOperand(i);
1176 if (MO.isReg() && MO.isUse())
1177 MO.setIsKill(false);
1181 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1183 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1184 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1185 const MachineOperand &MO = MI->getOperand(i);
1186 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1188 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1189 MachineOperand &MOp = getOperand(j);
1190 if (!MOp.isIdenticalTo(MO))
1201 /// copyPredicates - Copies predicate operand(s) from MI.
1202 void MachineInstr::copyPredicates(const MachineInstr *MI) {
1203 assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles");
1205 const MCInstrDesc &MCID = MI->getDesc();
1206 if (!MCID.isPredicable())
1208 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1209 if (MCID.OpInfo[i].isPredicate()) {
1210 // Predicated operands must be last operands.
1211 addOperand(MI->getOperand(i));
1216 void MachineInstr::substituteRegister(unsigned FromReg,
1219 const TargetRegisterInfo &RegInfo) {
1220 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1222 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1223 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1224 MachineOperand &MO = getOperand(i);
1225 if (!MO.isReg() || MO.getReg() != FromReg)
1227 MO.substPhysReg(ToReg, RegInfo);
1230 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1231 MachineOperand &MO = getOperand(i);
1232 if (!MO.isReg() || MO.getReg() != FromReg)
1234 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1239 /// isSafeToMove - Return true if it is safe to move this instruction. If
1240 /// SawStore is set to true, it means that there is a store (or call) between
1241 /// the instruction's location and its intended destination.
1242 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1244 bool &SawStore) const {
1245 // Ignore stuff that we obviously can't move.
1246 if (mayStore() || isCall()) {
1251 if (isLabel() || isDebugValue() ||
1252 isTerminator() || hasUnmodeledSideEffects())
1255 // See if this instruction does a load. If so, we have to guarantee that the
1256 // loaded value doesn't change between the load and the its intended
1257 // destination. The check for isInvariantLoad gives the targe the chance to
1258 // classify the load as always returning a constant, e.g. a constant pool
1260 if (mayLoad() && !isInvariantLoad(AA))
1261 // Otherwise, this is a real load. If there is a store between the load and
1262 // end of block, or if the load is volatile, we can't move it.
1263 return !SawStore && !hasVolatileMemoryRef();
1268 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1269 /// instruction which defined the specified register instead of copying it.
1270 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1272 unsigned DstReg) const {
1273 bool SawStore = false;
1274 if (!TII->isTriviallyReMaterializable(this, AA) ||
1275 !isSafeToMove(TII, AA, SawStore))
1277 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1278 const MachineOperand &MO = getOperand(i);
1281 // FIXME: For now, do not remat any instruction with register operands.
1282 // Later on, we can loosen the restriction is the register operands have
1283 // not been modified between the def and use. Note, this is different from
1284 // MachineSink because the code is no longer in two-address form (at least
1288 else if (!MO.isDead() && MO.getReg() != DstReg)
1294 /// hasVolatileMemoryRef - Return true if this instruction may have a
1295 /// volatile memory reference, or if the information describing the
1296 /// memory reference is not available. Return false if it is known to
1297 /// have no volatile memory references.
1298 bool MachineInstr::hasVolatileMemoryRef() const {
1299 // An instruction known never to access memory won't have a volatile access.
1303 !hasUnmodeledSideEffects())
1306 // Otherwise, if the instruction has no memory reference information,
1307 // conservatively assume it wasn't preserved.
1308 if (memoperands_empty())
1311 // Check the memory reference information for volatile references.
1312 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1313 if ((*I)->isVolatile())
1319 /// isInvariantLoad - Return true if this instruction is loading from a
1320 /// location whose value is invariant across the function. For example,
1321 /// loading a value from the constant pool or from the argument area
1322 /// of a function if it does not change. This should only return true of
1323 /// *all* loads the instruction does are invariant (if it does multiple loads).
1324 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1325 // If the instruction doesn't load at all, it isn't an invariant load.
1329 // If the instruction has lost its memoperands, conservatively assume that
1330 // it may not be an invariant load.
1331 if (memoperands_empty())
1334 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1336 for (mmo_iterator I = memoperands_begin(),
1337 E = memoperands_end(); I != E; ++I) {
1338 if ((*I)->isVolatile()) return false;
1339 if ((*I)->isStore()) return false;
1340 if ((*I)->isInvariant()) return true;
1342 if (const Value *V = (*I)->getValue()) {
1343 // A load from a constant PseudoSourceValue is invariant.
1344 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1345 if (PSV->isConstant(MFI))
1347 // If we have an AliasAnalysis, ask it whether the memory is constant.
1348 if (AA && AA->pointsToConstantMemory(
1349 AliasAnalysis::Location(V, (*I)->getSize(),
1350 (*I)->getTBAAInfo())))
1354 // Otherwise assume conservatively.
1358 // Everything checks out.
1362 /// isConstantValuePHI - If the specified instruction is a PHI that always
1363 /// merges together the same virtual register, return the register, otherwise
1365 unsigned MachineInstr::isConstantValuePHI() const {
1368 assert(getNumOperands() >= 3 &&
1369 "It's illegal to have a PHI without source operands");
1371 unsigned Reg = getOperand(1).getReg();
1372 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1373 if (getOperand(i).getReg() != Reg)
1378 bool MachineInstr::hasUnmodeledSideEffects() const {
1379 if (hasProperty(MCID::UnmodeledSideEffects))
1381 if (isInlineAsm()) {
1382 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1383 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1390 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1392 bool MachineInstr::allDefsAreDead() const {
1393 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1394 const MachineOperand &MO = getOperand(i);
1395 if (!MO.isReg() || MO.isUse())
1403 /// copyImplicitOps - Copy implicit register operands from specified
1404 /// instruction to this instruction.
1405 void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1406 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1408 const MachineOperand &MO = MI->getOperand(i);
1409 if (MO.isReg() && MO.isImplicit())
1414 void MachineInstr::dump() const {
1415 dbgs() << " " << *this;
1418 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1419 raw_ostream &CommentOS) {
1420 const LLVMContext &Ctx = MF->getFunction()->getContext();
1421 if (!DL.isUnknown()) { // Print source line info.
1422 DIScope Scope(DL.getScope(Ctx));
1423 // Omit the directory, because it's likely to be long and uninteresting.
1425 CommentOS << Scope.getFilename();
1427 CommentOS << "<unknown>";
1428 CommentOS << ':' << DL.getLine();
1429 if (DL.getCol() != 0)
1430 CommentOS << ':' << DL.getCol();
1431 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1432 if (!InlinedAtDL.isUnknown()) {
1433 CommentOS << " @[ ";
1434 printDebugLoc(InlinedAtDL, MF, CommentOS);
1440 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1441 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1442 const MachineFunction *MF = 0;
1443 const MachineRegisterInfo *MRI = 0;
1444 if (const MachineBasicBlock *MBB = getParent()) {
1445 MF = MBB->getParent();
1447 TM = &MF->getTarget();
1449 MRI = &MF->getRegInfo();
1452 // Save a list of virtual registers.
1453 SmallVector<unsigned, 8> VirtRegs;
1455 // Print explicitly defined operands on the left of an assignment syntax.
1456 unsigned StartOp = 0, e = getNumOperands();
1457 for (; StartOp < e && getOperand(StartOp).isReg() &&
1458 getOperand(StartOp).isDef() &&
1459 !getOperand(StartOp).isImplicit();
1461 if (StartOp != 0) OS << ", ";
1462 getOperand(StartOp).print(OS, TM);
1463 unsigned Reg = getOperand(StartOp).getReg();
1464 if (TargetRegisterInfo::isVirtualRegister(Reg))
1465 VirtRegs.push_back(Reg);
1471 // Print the opcode name.
1472 OS << getDesc().getName();
1474 // Print the rest of the operands.
1475 bool OmittedAnyCallClobbers = false;
1476 bool FirstOp = true;
1477 unsigned AsmDescOp = ~0u;
1478 unsigned AsmOpCount = 0;
1480 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1481 // Print asm string.
1483 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1485 // Print HasSideEffects, IsAlignStack
1486 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1487 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1488 OS << " [sideeffect]";
1489 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1490 OS << " [alignstack]";
1492 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1497 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1498 const MachineOperand &MO = getOperand(i);
1500 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1501 VirtRegs.push_back(MO.getReg());
1503 // Omit call-clobbered registers which aren't used anywhere. This makes
1504 // call instructions much less noisy on targets where calls clobber lots
1505 // of registers. Don't rely on MO.isDead() because we may be called before
1506 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1507 if (MF && isCall() &&
1508 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1509 unsigned Reg = MO.getReg();
1510 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1511 const MachineRegisterInfo &MRI = MF->getRegInfo();
1512 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1513 bool HasAliasLive = false;
1514 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1515 unsigned AliasReg = *Alias; ++Alias)
1516 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1517 HasAliasLive = true;
1520 if (!HasAliasLive) {
1521 OmittedAnyCallClobbers = true;
1528 if (FirstOp) FirstOp = false; else OS << ",";
1530 if (i < getDesc().NumOperands) {
1531 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1532 if (MCOI.isPredicate())
1534 if (MCOI.isOptionalDef())
1537 if (isDebugValue() && MO.isMetadata()) {
1538 // Pretty print DBG_VALUE instructions.
1539 const MDNode *MD = MO.getMetadata();
1540 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1541 OS << "!\"" << MDS->getString() << '\"';
1544 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1545 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1546 } else if (i == AsmDescOp && MO.isImm()) {
1547 // Pretty print the inline asm operand descriptor.
1548 OS << '$' << AsmOpCount++;
1549 unsigned Flag = MO.getImm();
1550 switch (InlineAsm::getKind(Flag)) {
1551 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1552 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1553 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1554 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1555 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1556 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1557 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1561 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1563 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1565 OS << ":RC" << RCID;
1568 unsigned TiedTo = 0;
1569 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1570 OS << " tiedto:$" << TiedTo;
1574 // Compute the index of the next operand descriptor.
1575 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1580 // Briefly indicate whether any call clobbers were omitted.
1581 if (OmittedAnyCallClobbers) {
1582 if (!FirstOp) OS << ",";
1586 bool HaveSemi = false;
1588 if (!HaveSemi) OS << ";"; HaveSemi = true;
1591 if (Flags & FrameSetup)
1595 if (!memoperands_empty()) {
1596 if (!HaveSemi) OS << ";"; HaveSemi = true;
1599 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1602 if (llvm::next(i) != e)
1607 // Print the regclass of any virtual registers encountered.
1608 if (MRI && !VirtRegs.empty()) {
1609 if (!HaveSemi) OS << ";"; HaveSemi = true;
1610 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1611 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1612 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1613 for (unsigned j = i+1; j != VirtRegs.size();) {
1614 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1618 if (VirtRegs[i] != VirtRegs[j])
1619 OS << "," << PrintReg(VirtRegs[j]);
1620 VirtRegs.erase(VirtRegs.begin()+j);
1625 // Print debug location information.
1626 if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1627 if (!HaveSemi) OS << ";"; HaveSemi = true;
1628 DIVariable DV(getOperand(e - 1).getMetadata());
1629 OS << " line no:" << DV.getLineNumber();
1630 if (MDNode *InlinedAt = DV.getInlinedAt()) {
1631 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1632 if (!InlinedAtDL.isUnknown()) {
1633 OS << " inlined @[ ";
1634 printDebugLoc(InlinedAtDL, MF, OS);
1638 } else if (!debugLoc.isUnknown() && MF) {
1639 if (!HaveSemi) OS << ";"; HaveSemi = true;
1641 printDebugLoc(debugLoc, MF, OS);
1647 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1648 const TargetRegisterInfo *RegInfo,
1649 bool AddIfNotFound) {
1650 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1651 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1653 SmallVector<unsigned,4> DeadOps;
1654 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1655 MachineOperand &MO = getOperand(i);
1656 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1658 unsigned Reg = MO.getReg();
1662 if (Reg == IncomingReg) {
1665 // The register is already marked kill.
1667 if (isPhysReg && isRegTiedToDefOperand(i))
1668 // Two-address uses of physregs must not be marked kill.
1673 } else if (hasAliases && MO.isKill() &&
1674 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1675 // A super-register kill already exists.
1676 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1678 if (RegInfo->isSubRegister(IncomingReg, Reg))
1679 DeadOps.push_back(i);
1683 // Trim unneeded kill operands.
1684 while (!DeadOps.empty()) {
1685 unsigned OpIdx = DeadOps.back();
1686 if (getOperand(OpIdx).isImplicit())
1687 RemoveOperand(OpIdx);
1689 getOperand(OpIdx).setIsKill(false);
1693 // If not found, this means an alias of one of the operands is killed. Add a
1694 // new implicit operand if required.
1695 if (!Found && AddIfNotFound) {
1696 addOperand(MachineOperand::CreateReg(IncomingReg,
1705 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1706 const TargetRegisterInfo *RegInfo,
1707 bool AddIfNotFound) {
1708 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1709 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1711 SmallVector<unsigned,4> DeadOps;
1712 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1713 MachineOperand &MO = getOperand(i);
1714 if (!MO.isReg() || !MO.isDef())
1716 unsigned Reg = MO.getReg();
1720 if (Reg == IncomingReg) {
1723 } else if (hasAliases && MO.isDead() &&
1724 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1725 // There exists a super-register that's marked dead.
1726 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1728 if (RegInfo->getSubRegisters(IncomingReg) &&
1729 RegInfo->getSuperRegisters(Reg) &&
1730 RegInfo->isSubRegister(IncomingReg, Reg))
1731 DeadOps.push_back(i);
1735 // Trim unneeded dead operands.
1736 while (!DeadOps.empty()) {
1737 unsigned OpIdx = DeadOps.back();
1738 if (getOperand(OpIdx).isImplicit())
1739 RemoveOperand(OpIdx);
1741 getOperand(OpIdx).setIsDead(false);
1745 // If not found, this means an alias of one of the operands is dead. Add a
1746 // new implicit operand if required.
1747 if (Found || !AddIfNotFound)
1750 addOperand(MachineOperand::CreateReg(IncomingReg,
1758 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1759 const TargetRegisterInfo *RegInfo) {
1760 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1761 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1765 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1766 const MachineOperand &MO = getOperand(i);
1767 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1768 MO.getSubReg() == 0)
1772 addOperand(MachineOperand::CreateReg(IncomingReg,
1777 void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
1778 const TargetRegisterInfo &TRI) {
1779 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1780 MachineOperand &MO = getOperand(i);
1781 if (!MO.isReg() || !MO.isDef()) continue;
1782 unsigned Reg = MO.getReg();
1783 if (Reg == 0) continue;
1785 for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
1786 E = UsedRegs.end(); I != E; ++I)
1787 if (TRI.regsOverlap(*I, Reg)) {
1791 // If there are no uses, including partial uses, the def is dead.
1792 if (Dead) MO.setIsDead();
1797 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1798 unsigned Hash = MI->getOpcode() * 37;
1799 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1800 const MachineOperand &MO = MI->getOperand(i);
1801 uint64_t Key = (uint64_t)MO.getType() << 32;
1802 switch (MO.getType()) {
1804 case MachineOperand::MO_Register:
1805 if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1806 continue; // Skip virtual register defs.
1809 case MachineOperand::MO_Immediate:
1812 case MachineOperand::MO_FrameIndex:
1813 case MachineOperand::MO_ConstantPoolIndex:
1814 case MachineOperand::MO_JumpTableIndex:
1815 Key |= MO.getIndex();
1817 case MachineOperand::MO_MachineBasicBlock:
1818 Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1820 case MachineOperand::MO_GlobalAddress:
1821 Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1823 case MachineOperand::MO_BlockAddress:
1824 Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1826 case MachineOperand::MO_MCSymbol:
1827 Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1830 Key += ~(Key << 32);
1832 Key += ~(Key << 13);
1836 Key += ~(Key << 27);
1838 Hash = (unsigned)Key + Hash * 37;
1843 void MachineInstr::emitError(StringRef Msg) const {
1844 // Find the source location cookie.
1845 unsigned LocCookie = 0;
1846 const MDNode *LocMD = 0;
1847 for (unsigned i = getNumOperands(); i != 0; --i) {
1848 if (getOperand(i-1).isMetadata() &&
1849 (LocMD = getOperand(i-1).getMetadata()) &&
1850 LocMD->getNumOperands() != 0) {
1851 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1852 LocCookie = CI->getZExtValue();
1858 if (const MachineBasicBlock *MBB = getParent())
1859 if (const MachineFunction *MF = MBB->getParent())
1860 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1861 report_fatal_error(Msg);