1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 #include "llvm/CodeGen/MachineInstr.h"
13 #include "llvm/CodeGen/MachineBasicBlock.h"
14 #include "llvm/Value.h"
15 #include "llvm/Target/TargetMachine.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Target/MRegisterInfo.h"
21 // Global variable holding an array of descriptors for machine instructions.
22 // The actual object needs to be created separately for each target machine.
23 // This variable is initialized and reset by class TargetInstrInfo.
25 // FIXME: This should be a property of the target so that more than one target
26 // at a time can be active...
28 extern const TargetInstrDescriptor *TargetInstrDescriptors;
30 // Constructor for instructions with variable #operands
31 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
34 operands(numOperands, MachineOperand()),
39 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
40 /// not a resize for them. It is expected that if you use this that you call
41 /// add* methods below to fill up the operands, instead of the Set methods.
42 /// Eventually, the "resizing" ctors will be phased out.
44 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
50 operands.reserve(numOperands);
53 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
54 /// MachineInstr is created and added to the end of the specified basic block.
56 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
62 assert(MBB && "Cannot use inserting ctor with null basic block!");
63 operands.reserve(numOperands);
64 MBB->push_back(this); // Add instruction to end of basic block!
68 // OperandComplete - Return true if it's illegal to add a new operand
69 bool MachineInstr::OperandsComplete() const
71 int NumOperands = TargetInstrDescriptors[opCode].numOperands;
72 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
73 return true; // Broken: we have all the operands of this instruction!
79 // Support for replacing opcode and operands of a MachineInstr in place.
80 // This only resets the size of the operand vector and initializes it.
81 // The new operands must be set explicitly later.
83 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
85 assert(getNumImplicitRefs() == 0 &&
86 "This is probably broken because implicit refs are going to be lost.");
89 operands.resize(numOperands, MachineOperand());
92 void MachineInstr::SetMachineOperandVal(unsigned i,
93 MachineOperand::MachineOperandType opTy,
95 assert(i < operands.size()); // may be explicit or implicit op
96 operands[i].opType = opTy;
97 operands[i].value = V;
98 operands[i].regNum = -1;
102 MachineInstr::SetMachineOperandConst(unsigned i,
103 MachineOperand::MachineOperandType operandType,
106 assert(i < getNumOperands()); // must be explicit op
107 assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
108 "immed. constant cannot be defined");
110 operands[i].opType = operandType;
111 operands[i].value = NULL;
112 operands[i].immedVal = intValue;
113 operands[i].regNum = -1;
114 operands[i].flags = 0;
117 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
118 assert(i < getNumOperands()); // must be explicit op
120 operands[i].opType = MachineOperand::MO_MachineRegister;
121 operands[i].value = NULL;
122 operands[i].regNum = regNum;
126 MachineInstr::SetRegForOperand(unsigned i, int regNum)
128 assert(i < getNumOperands()); // must be explicit op
129 operands[i].setRegForValue(regNum);
133 MachineInstr::SetRegForImplicitRef(unsigned i, int regNum)
135 getImplicitOp(i).setRegForValue(regNum);
139 // Substitute all occurrences of Value* oldVal with newVal in all operands
140 // and all implicit refs.
141 // If defsOnly == true, substitute defs only.
143 MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
144 bool defsOnly, bool notDefsAndUses,
145 bool& someArgsWereIgnored)
147 assert((!defsOnly || !notDefsAndUses) &&
148 "notDefsAndUses is irrelevant if defsOnly == true.");
150 unsigned numSubst = 0;
152 // Substitute operands
153 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
156 notDefsAndUses && (O.isDef() && !O.isUse()) ||
157 !notDefsAndUses && O.isDef())
159 O.getMachineOperand().value = newVal;
163 someArgsWereIgnored = true;
165 // Substitute implicit refs
166 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
167 if (getImplicitRef(i) == oldVal)
169 notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
170 !notDefsAndUses && getImplicitOp(i).isDef())
172 getImplicitOp(i).value = newVal;
176 someArgsWereIgnored = true;
183 MachineInstr::dump() const
185 std::cerr << " " << *this;
188 static inline std::ostream&
189 OutputValue(std::ostream &os, const Value* val)
192 os << (void*) val; // print address always
193 if (val && val->hasName())
194 os << " " << val->getName() << ")"; // print name also, if available
198 static inline void OutputReg(std::ostream &os, unsigned RegNo,
199 const MRegisterInfo *MRI = 0) {
201 if (RegNo < MRegisterInfo::FirstVirtualRegister)
202 os << "%" << MRI->get(RegNo).Name;
204 os << "%reg" << RegNo;
206 os << "%mreg(" << RegNo << ")";
209 static void print(const MachineOperand &MO, std::ostream &OS,
210 const TargetMachine &TM) {
211 const MRegisterInfo *MRI = TM.getRegisterInfo();
212 bool CloseParen = true;
215 else if (MO.isLoBits32())
217 else if (MO.isHiBits64())
219 else if (MO.isLoBits64())
224 switch (MO.getType()) {
225 case MachineOperand::MO_VirtualRegister:
226 if (MO.getVRegValue()) {
228 OutputValue(OS, MO.getVRegValue());
229 if (MO.hasAllocatedReg())
232 if (MO.hasAllocatedReg())
233 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
235 case MachineOperand::MO_CCRegister:
237 OutputValue(OS, MO.getVRegValue());
238 if (MO.hasAllocatedReg()) {
240 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
243 case MachineOperand::MO_MachineRegister:
244 OutputReg(OS, MO.getMachineRegNum(), MRI);
246 case MachineOperand::MO_SignExtendedImmed:
247 OS << (long)MO.getImmedValue();
249 case MachineOperand::MO_UnextendedImmed:
250 OS << (long)MO.getImmedValue();
252 case MachineOperand::MO_PCRelativeDisp: {
253 const Value* opVal = MO.getVRegValue();
254 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
255 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
256 if (opVal->hasName())
257 OS << opVal->getName();
259 OS << (const void*) opVal;
263 case MachineOperand::MO_MachineBasicBlock:
265 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
266 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
268 case MachineOperand::MO_FrameIndex:
269 OS << "<fi#" << MO.getFrameIndex() << ">";
271 case MachineOperand::MO_ConstantPoolIndex:
272 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
274 case MachineOperand::MO_GlobalAddress:
275 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
277 case MachineOperand::MO_ExternalSymbol:
278 OS << "<es:" << MO.getSymbolName() << ">";
281 assert(0 && "Unrecognized operand type");
288 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
289 unsigned StartOp = 0;
291 // Specialize printing if op#0 is definition
292 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
293 llvm::print(getOperand(0), OS, TM);
295 ++StartOp; // Don't print this operand again!
297 OS << TM.getInstrInfo().getName(getOpcode());
299 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
300 const MachineOperand& mop = getOperand(i);
304 llvm::print(mop, OS, TM);
313 // code for printing implicit references
314 if (getNumImplicitRefs()) {
315 OS << "\tImplicitRefs: ";
316 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
318 OutputValue(OS, getImplicitRef(i));
319 if (getImplicitOp(i).isDef())
320 if (getImplicitOp(i).isUse())
331 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
333 os << TargetInstrDescriptors[MI.opCode].Name;
335 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
336 os << "\t" << MI.getOperand(i);
337 if (MI.getOperand(i).isDef())
338 if (MI.getOperand(i).isUse())
344 // code for printing implicit references
345 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
346 if (NumOfImpRefs > 0) {
347 os << "\tImplicit: ";
348 for (unsigned z=0; z < NumOfImpRefs; z++) {
349 OutputValue(os, MI.getImplicitRef(z));
350 if (MI.getImplicitOp(z).isDef())
351 if (MI.getImplicitOp(z).isUse())
362 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
366 else if (MO.isLoBits32())
368 else if (MO.isHiBits64())
370 else if (MO.isLoBits64())
373 switch (MO.getType())
375 case MachineOperand::MO_VirtualRegister:
376 if (MO.hasAllocatedReg())
377 OutputReg(OS, MO.getAllocatedRegNum());
379 if (MO.getVRegValue()) {
380 if (MO.hasAllocatedReg()) OS << "==";
382 OutputValue(OS, MO.getVRegValue());
385 case MachineOperand::MO_CCRegister:
387 OutputValue(OS, MO.getVRegValue());
388 if (MO.hasAllocatedReg()) {
390 OutputReg(OS, MO.getAllocatedRegNum());
393 case MachineOperand::MO_MachineRegister:
394 OutputReg(OS, MO.getMachineRegNum());
396 case MachineOperand::MO_SignExtendedImmed:
397 OS << (long)MO.getImmedValue();
399 case MachineOperand::MO_UnextendedImmed:
400 OS << (long)MO.getImmedValue();
402 case MachineOperand::MO_PCRelativeDisp:
404 const Value* opVal = MO.getVRegValue();
405 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
406 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
407 if (opVal->hasName())
408 OS << opVal->getName();
410 OS << (const void*) opVal;
414 case MachineOperand::MO_MachineBasicBlock:
416 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
417 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
419 case MachineOperand::MO_FrameIndex:
420 OS << "<fi#" << MO.getFrameIndex() << ">";
422 case MachineOperand::MO_ConstantPoolIndex:
423 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
425 case MachineOperand::MO_GlobalAddress:
426 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
428 case MachineOperand::MO_ExternalSymbol:
429 OS << "<es:" << MO.getSymbolName() << ">";
432 assert(0 && "Unrecognized operand type");
437 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
438 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))
444 } // End llvm namespace