1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/DebugInfo.h"
17 #include "llvm/Function.h"
18 #include "llvm/InlineAsm.h"
19 #include "llvm/LLVMContext.h"
20 #include "llvm/Metadata.h"
21 #include "llvm/Module.h"
22 #include "llvm/Type.h"
23 #include "llvm/Value.h"
24 #include "llvm/Assembly/Writer.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/PseudoSourceValue.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/MC/MCSymbol.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetRegisterInfo.h"
36 #include "llvm/Analysis/AliasAnalysis.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/LeakDetector.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/FoldingSet.h"
43 #include "llvm/ADT/Hashing.h"
46 //===----------------------------------------------------------------------===//
47 // MachineOperand Implementation
48 //===----------------------------------------------------------------------===//
50 void MachineOperand::setReg(unsigned Reg) {
51 if (getReg() == Reg) return; // No change.
53 // Otherwise, we have to change the register. If this operand is embedded
54 // into a machine function, we need to update the old and new register's
56 if (MachineInstr *MI = getParent())
57 if (MachineBasicBlock *MBB = MI->getParent())
58 if (MachineFunction *MF = MBB->getParent()) {
59 MachineRegisterInfo &MRI = MF->getRegInfo();
60 MRI.removeRegOperandFromUseList(this);
61 SmallContents.RegNo = Reg;
62 MRI.addRegOperandToUseList(this);
66 // Otherwise, just change the register, no problem. :)
67 SmallContents.RegNo = Reg;
70 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
71 const TargetRegisterInfo &TRI) {
72 assert(TargetRegisterInfo::isVirtualRegister(Reg));
73 if (SubIdx && getSubReg())
74 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
80 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
81 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
83 Reg = TRI.getSubReg(Reg, getSubReg());
84 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
85 // That won't happen in legal code.
91 /// ChangeToImmediate - Replace this operand with a new immediate operand of
92 /// the specified value. If an operand is known to be an immediate already,
93 /// the setImm method should be used.
94 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
95 // If this operand is currently a register operand, and if this is in a
96 // function, deregister the operand from the register's use/def list.
97 if (isReg() && isOnRegUseList())
98 if (MachineInstr *MI = getParent())
99 if (MachineBasicBlock *MBB = MI->getParent())
100 if (MachineFunction *MF = MBB->getParent())
101 MF->getRegInfo().removeRegOperandFromUseList(this);
103 OpKind = MO_Immediate;
104 Contents.ImmVal = ImmVal;
107 /// ChangeToRegister - Replace this operand with a new register operand of
108 /// the specified value. If an operand is known to be an register already,
109 /// the setReg method should be used.
110 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
111 bool isKill, bool isDead, bool isUndef,
113 // If this operand is already a register operand, use setReg to update the
114 // register's use/def lists.
116 assert(!isEarlyClobber());
119 // Otherwise, change this to a register and set the reg#.
120 OpKind = MO_Register;
121 SmallContents.RegNo = Reg;
122 // Ensure isOnRegUseList() returns false.
123 Contents.Reg.Prev = 0;
125 // If this operand is embedded in a function, add the operand to the
126 // register's use/def list.
127 if (MachineInstr *MI = getParent())
128 if (MachineBasicBlock *MBB = MI->getParent())
129 if (MachineFunction *MF = MBB->getParent())
130 MF->getRegInfo().addRegOperandToUseList(this);
138 IsInternalRead = false;
139 IsEarlyClobber = false;
144 /// isIdenticalTo - Return true if this operand is identical to the specified
145 /// operand. Note that this should stay in sync with the hash_value overload
147 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
148 if (getType() != Other.getType() ||
149 getTargetFlags() != Other.getTargetFlags())
153 case MachineOperand::MO_Register:
154 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
155 getSubReg() == Other.getSubReg();
156 case MachineOperand::MO_Immediate:
157 return getImm() == Other.getImm();
158 case MachineOperand::MO_CImmediate:
159 return getCImm() == Other.getCImm();
160 case MachineOperand::MO_FPImmediate:
161 return getFPImm() == Other.getFPImm();
162 case MachineOperand::MO_MachineBasicBlock:
163 return getMBB() == Other.getMBB();
164 case MachineOperand::MO_FrameIndex:
165 return getIndex() == Other.getIndex();
166 case MachineOperand::MO_ConstantPoolIndex:
167 case MachineOperand::MO_TargetIndex:
168 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
169 case MachineOperand::MO_JumpTableIndex:
170 return getIndex() == Other.getIndex();
171 case MachineOperand::MO_GlobalAddress:
172 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
173 case MachineOperand::MO_ExternalSymbol:
174 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
175 getOffset() == Other.getOffset();
176 case MachineOperand::MO_BlockAddress:
177 return getBlockAddress() == Other.getBlockAddress();
178 case MO_RegisterMask:
179 return getRegMask() == Other.getRegMask();
180 case MachineOperand::MO_MCSymbol:
181 return getMCSymbol() == Other.getMCSymbol();
182 case MachineOperand::MO_Metadata:
183 return getMetadata() == Other.getMetadata();
185 llvm_unreachable("Invalid machine operand type");
188 // Note: this must stay exactly in sync with isIdenticalTo above.
189 hash_code llvm::hash_value(const MachineOperand &MO) {
190 switch (MO.getType()) {
191 case MachineOperand::MO_Register:
192 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getReg(),
193 MO.getSubReg(), MO.isDef());
194 case MachineOperand::MO_Immediate:
195 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
196 case MachineOperand::MO_CImmediate:
197 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
198 case MachineOperand::MO_FPImmediate:
199 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
200 case MachineOperand::MO_MachineBasicBlock:
201 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
202 case MachineOperand::MO_FrameIndex:
203 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
204 case MachineOperand::MO_ConstantPoolIndex:
205 case MachineOperand::MO_TargetIndex:
206 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
208 case MachineOperand::MO_JumpTableIndex:
209 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
210 case MachineOperand::MO_ExternalSymbol:
211 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
213 case MachineOperand::MO_GlobalAddress:
214 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
216 case MachineOperand::MO_BlockAddress:
217 return hash_combine(MO.getType(), MO.getTargetFlags(),
218 MO.getBlockAddress());
219 case MachineOperand::MO_RegisterMask:
220 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
221 case MachineOperand::MO_Metadata:
222 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
223 case MachineOperand::MO_MCSymbol:
224 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
226 llvm_unreachable("Invalid machine operand type");
229 /// print - Print the specified machine operand.
231 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
232 // If the instruction is embedded into a basic block, we can find the
233 // target info for the instruction.
235 if (const MachineInstr *MI = getParent())
236 if (const MachineBasicBlock *MBB = MI->getParent())
237 if (const MachineFunction *MF = MBB->getParent())
238 TM = &MF->getTarget();
239 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
242 case MachineOperand::MO_Register:
243 OS << PrintReg(getReg(), TRI, getSubReg());
245 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
246 isInternalRead() || isEarlyClobber()) {
248 bool NeedComma = false;
250 if (NeedComma) OS << ',';
251 if (isEarlyClobber())
252 OS << "earlyclobber,";
257 // <def,read-undef> only makes sense when getSubReg() is set.
258 // Don't clutter the output otherwise.
259 if (isUndef() && getSubReg())
261 } else if (isImplicit()) {
266 if (isKill() || isDead() || (isUndef() && isUse()) || isInternalRead()) {
267 if (NeedComma) OS << ',';
277 if (isUndef() && isUse()) {
278 if (NeedComma) OS << ',';
282 if (isInternalRead()) {
283 if (NeedComma) OS << ',';
291 case MachineOperand::MO_Immediate:
294 case MachineOperand::MO_CImmediate:
295 getCImm()->getValue().print(OS, false);
297 case MachineOperand::MO_FPImmediate:
298 if (getFPImm()->getType()->isFloatTy())
299 OS << getFPImm()->getValueAPF().convertToFloat();
301 OS << getFPImm()->getValueAPF().convertToDouble();
303 case MachineOperand::MO_MachineBasicBlock:
304 OS << "<BB#" << getMBB()->getNumber() << ">";
306 case MachineOperand::MO_FrameIndex:
307 OS << "<fi#" << getIndex() << '>';
309 case MachineOperand::MO_ConstantPoolIndex:
310 OS << "<cp#" << getIndex();
311 if (getOffset()) OS << "+" << getOffset();
314 case MachineOperand::MO_TargetIndex:
315 OS << "<ti#" << getIndex();
316 if (getOffset()) OS << "+" << getOffset();
319 case MachineOperand::MO_JumpTableIndex:
320 OS << "<jt#" << getIndex() << '>';
322 case MachineOperand::MO_GlobalAddress:
324 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
325 if (getOffset()) OS << "+" << getOffset();
328 case MachineOperand::MO_ExternalSymbol:
329 OS << "<es:" << getSymbolName();
330 if (getOffset()) OS << "+" << getOffset();
333 case MachineOperand::MO_BlockAddress:
335 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
338 case MachineOperand::MO_RegisterMask:
341 case MachineOperand::MO_Metadata:
343 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
346 case MachineOperand::MO_MCSymbol:
347 OS << "<MCSym=" << *getMCSymbol() << '>';
351 if (unsigned TF = getTargetFlags())
352 OS << "[TF=" << TF << ']';
355 //===----------------------------------------------------------------------===//
356 // MachineMemOperand Implementation
357 //===----------------------------------------------------------------------===//
359 /// getAddrSpace - Return the LLVM IR address space number that this pointer
361 unsigned MachinePointerInfo::getAddrSpace() const {
362 if (V == 0) return 0;
363 return cast<PointerType>(V->getType())->getAddressSpace();
366 /// getConstantPool - Return a MachinePointerInfo record that refers to the
368 MachinePointerInfo MachinePointerInfo::getConstantPool() {
369 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
372 /// getFixedStack - Return a MachinePointerInfo record that refers to the
373 /// the specified FrameIndex.
374 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
375 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
378 MachinePointerInfo MachinePointerInfo::getJumpTable() {
379 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
382 MachinePointerInfo MachinePointerInfo::getGOT() {
383 return MachinePointerInfo(PseudoSourceValue::getGOT());
386 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
387 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
390 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
391 uint64_t s, unsigned int a,
392 const MDNode *TBAAInfo,
393 const MDNode *Ranges)
394 : PtrInfo(ptrinfo), Size(s),
395 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
396 TBAAInfo(TBAAInfo), Ranges(Ranges) {
397 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
398 "invalid pointer value");
399 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
400 assert((isLoad() || isStore()) && "Not a load/store!");
403 /// Profile - Gather unique data for the object.
405 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
406 ID.AddInteger(getOffset());
408 ID.AddPointer(getValue());
409 ID.AddInteger(Flags);
412 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
413 // The Value and Offset may differ due to CSE. But the flags and size
414 // should be the same.
415 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
416 assert(MMO->getSize() == getSize() && "Size mismatch!");
418 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
419 // Update the alignment value.
420 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
421 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
422 // Also update the base and offset, because the new alignment may
423 // not be applicable with the old ones.
424 PtrInfo = MMO->PtrInfo;
428 /// getAlignment - Return the minimum known alignment in bytes of the
429 /// actual memory reference.
430 uint64_t MachineMemOperand::getAlignment() const {
431 return MinAlign(getBaseAlignment(), getOffset());
434 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
435 assert((MMO.isLoad() || MMO.isStore()) &&
436 "SV has to be a load, store or both.");
438 if (MMO.isVolatile())
447 // Print the address information.
452 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
454 // If the alignment of the memory reference itself differs from the alignment
455 // of the base pointer, print the base alignment explicitly, next to the base
457 if (MMO.getBaseAlignment() != MMO.getAlignment())
458 OS << "(align=" << MMO.getBaseAlignment() << ")";
460 if (MMO.getOffset() != 0)
461 OS << "+" << MMO.getOffset();
464 // Print the alignment of the reference.
465 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
466 MMO.getBaseAlignment() != MMO.getSize())
467 OS << "(align=" << MMO.getAlignment() << ")";
470 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
472 if (TBAAInfo->getNumOperands() > 0)
473 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
479 // Print nontemporal info.
480 if (MMO.isNonTemporal())
481 OS << "(nontemporal)";
486 //===----------------------------------------------------------------------===//
487 // MachineInstr Implementation
488 //===----------------------------------------------------------------------===//
490 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
491 /// MCID NULL and no operands.
492 MachineInstr::MachineInstr()
493 : MCID(0), Flags(0), AsmPrinterFlags(0),
494 NumMemRefs(0), MemRefs(0),
496 // Make sure that we get added to a machine basicblock
497 LeakDetector::addGarbageObject(this);
500 void MachineInstr::addImplicitDefUseOperands() {
501 if (MCID->ImplicitDefs)
502 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
503 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
504 if (MCID->ImplicitUses)
505 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
506 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
509 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
510 /// implicit operands. It reserves space for the number of operands specified by
512 MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
513 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
514 NumMemRefs(0), MemRefs(0), Parent(0) {
515 unsigned NumImplicitOps = 0;
517 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
518 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
520 addImplicitDefUseOperands();
521 // Make sure that we get added to a machine basicblock
522 LeakDetector::addGarbageObject(this);
525 /// MachineInstr ctor - As above, but with a DebugLoc.
526 MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
528 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
529 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
530 unsigned NumImplicitOps = 0;
532 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
533 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
535 addImplicitDefUseOperands();
536 // Make sure that we get added to a machine basicblock
537 LeakDetector::addGarbageObject(this);
540 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
541 /// that the MachineInstr is created and added to the end of the specified
543 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
544 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
545 NumMemRefs(0), MemRefs(0), Parent(0) {
546 assert(MBB && "Cannot use inserting ctor with null basic block!");
547 unsigned NumImplicitOps =
548 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
549 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
550 addImplicitDefUseOperands();
551 // Make sure that we get added to a machine basicblock
552 LeakDetector::addGarbageObject(this);
553 MBB->push_back(this); // Add instruction to end of basic block!
556 /// MachineInstr ctor - As above, but with a DebugLoc.
558 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
559 const MCInstrDesc &tid)
560 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
561 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
562 assert(MBB && "Cannot use inserting ctor with null basic block!");
563 unsigned NumImplicitOps =
564 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
565 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
566 addImplicitDefUseOperands();
567 // Make sure that we get added to a machine basicblock
568 LeakDetector::addGarbageObject(this);
569 MBB->push_back(this); // Add instruction to end of basic block!
572 /// MachineInstr ctor - Copies MachineInstr arg exactly
574 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
575 : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
576 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
577 Parent(0), debugLoc(MI.getDebugLoc()) {
578 Operands.reserve(MI.getNumOperands());
581 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
582 addOperand(MI.getOperand(i));
584 // Copy all the flags.
587 // Set parent to null.
590 LeakDetector::addGarbageObject(this);
593 MachineInstr::~MachineInstr() {
594 LeakDetector::removeGarbageObject(this);
596 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
597 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
598 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
599 "Reg operand def/use list corrupted");
604 /// getRegInfo - If this instruction is embedded into a MachineFunction,
605 /// return the MachineRegisterInfo object for the current function, otherwise
607 MachineRegisterInfo *MachineInstr::getRegInfo() {
608 if (MachineBasicBlock *MBB = getParent())
609 return &MBB->getParent()->getRegInfo();
613 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
614 /// this instruction from their respective use lists. This requires that the
615 /// operands already be on their use lists.
616 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
617 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
618 if (Operands[i].isReg())
619 MRI.removeRegOperandFromUseList(&Operands[i]);
622 /// AddRegOperandsToUseLists - Add all of the register operands in
623 /// this instruction from their respective use lists. This requires that the
624 /// operands not be on their use lists yet.
625 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
626 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
627 if (Operands[i].isReg())
628 MRI.addRegOperandToUseList(&Operands[i]);
631 /// addOperand - Add the specified operand to the instruction. If it is an
632 /// implicit operand, it is added to the end of the operand list. If it is
633 /// an explicit operand it is added at the end of the explicit operand list
634 /// (before the first implicit operand).
635 void MachineInstr::addOperand(const MachineOperand &Op) {
636 assert(MCID && "Cannot add operands before providing an instr descriptor");
637 bool isImpReg = Op.isReg() && Op.isImplicit();
638 MachineRegisterInfo *RegInfo = getRegInfo();
640 // If the Operands backing store is reallocated, all register operands must
641 // be removed and re-added to RegInfo. It is storing pointers to operands.
642 bool Reallocate = RegInfo &&
643 !Operands.empty() && Operands.size() == Operands.capacity();
645 // Find the insert location for the new operand. Implicit registers go at
646 // the end, everything goes before the implicit regs.
647 unsigned OpNo = Operands.size();
649 // Remove all the implicit operands from RegInfo if they need to be shifted.
650 // FIXME: Allow mixed explicit and implicit operands on inline asm.
651 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
652 // implicit-defs, but they must not be moved around. See the FIXME in
654 if (!isImpReg && !isInlineAsm()) {
655 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
658 RegInfo->removeRegOperandFromUseList(&Operands[OpNo]);
662 // OpNo now points as the desired insertion point. Unless this is a variadic
663 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
664 // RegMask operands go between the explicit and implicit operands.
665 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
666 OpNo < MCID->getNumOperands()) &&
667 "Trying to add an operand to a machine instr that is already done!");
669 // All operands from OpNo have been removed from RegInfo. If the Operands
670 // backing store needs to be reallocated, we also need to remove any other
671 // register operands.
673 for (unsigned i = 0; i != OpNo; ++i)
674 if (Operands[i].isReg())
675 RegInfo->removeRegOperandFromUseList(&Operands[i]);
677 // Insert the new operand at OpNo.
678 Operands.insert(Operands.begin() + OpNo, Op);
679 Operands[OpNo].ParentMI = this;
681 // The Operands backing store has now been reallocated, so we can re-add the
682 // operands before OpNo.
684 for (unsigned i = 0; i != OpNo; ++i)
685 if (Operands[i].isReg())
686 RegInfo->addRegOperandToUseList(&Operands[i]);
688 // When adding a register operand, tell RegInfo about it.
689 if (Operands[OpNo].isReg()) {
690 // Ensure isOnRegUseList() returns false, regardless of Op's status.
691 Operands[OpNo].Contents.Reg.Prev = 0;
692 // Add the new operand to RegInfo.
694 RegInfo->addRegOperandToUseList(&Operands[OpNo]);
695 // If the register operand is flagged as early, mark the operand as such.
696 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
697 Operands[OpNo].setIsEarlyClobber(true);
700 // Re-add all the implicit ops.
702 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
703 assert(Operands[i].isReg() && "Should only be an implicit reg!");
704 RegInfo->addRegOperandToUseList(&Operands[i]);
709 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
710 /// fewer operand than it started with.
712 void MachineInstr::RemoveOperand(unsigned OpNo) {
713 assert(OpNo < Operands.size() && "Invalid operand number");
714 MachineRegisterInfo *RegInfo = getRegInfo();
716 // Special case removing the last one.
717 if (OpNo == Operands.size()-1) {
718 // If needed, remove from the reg def/use list.
719 if (RegInfo && Operands.back().isReg() && Operands.back().isOnRegUseList())
720 RegInfo->removeRegOperandFromUseList(&Operands.back());
726 // Otherwise, we are removing an interior operand. If we have reginfo to
727 // update, remove all operands that will be shifted down from their reg lists,
728 // move everything down, then re-add them.
730 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
731 if (Operands[i].isReg())
732 RegInfo->removeRegOperandFromUseList(&Operands[i]);
736 Operands.erase(Operands.begin()+OpNo);
739 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
740 if (Operands[i].isReg())
741 RegInfo->addRegOperandToUseList(&Operands[i]);
746 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
747 /// This function should be used only occasionally. The setMemRefs function
748 /// is the primary method for setting up a MachineInstr's MemRefs list.
749 void MachineInstr::addMemOperand(MachineFunction &MF,
750 MachineMemOperand *MO) {
751 mmo_iterator OldMemRefs = MemRefs;
752 uint16_t OldNumMemRefs = NumMemRefs;
754 uint16_t NewNum = NumMemRefs + 1;
755 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
757 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
758 NewMemRefs[NewNum - 1] = MO;
760 MemRefs = NewMemRefs;
764 bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
765 const MachineBasicBlock *MBB = getParent();
766 MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
767 while (MII != MBB->end() && MII->isInsideBundle()) {
768 if (MII->getDesc().getFlags() & Mask) {
769 if (Type == AnyInBundle)
772 if (Type == AllInBundle)
778 return Type == AllInBundle;
781 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
782 MICheckType Check) const {
783 // If opcodes or number of operands are not the same then the two
784 // instructions are obviously not identical.
785 if (Other->getOpcode() != getOpcode() ||
786 Other->getNumOperands() != getNumOperands())
790 // Both instructions are bundles, compare MIs inside the bundle.
791 MachineBasicBlock::const_instr_iterator I1 = *this;
792 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
793 MachineBasicBlock::const_instr_iterator I2 = *Other;
794 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
795 while (++I1 != E1 && I1->isInsideBundle()) {
797 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
802 // Check operands to make sure they match.
803 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
804 const MachineOperand &MO = getOperand(i);
805 const MachineOperand &OMO = Other->getOperand(i);
807 if (!MO.isIdenticalTo(OMO))
812 // Clients may or may not want to ignore defs when testing for equality.
813 // For example, machine CSE pass only cares about finding common
814 // subexpressions, so it's safe to ignore virtual register defs.
816 if (Check == IgnoreDefs)
818 else if (Check == IgnoreVRegDefs) {
819 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
820 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
821 if (MO.getReg() != OMO.getReg())
824 if (!MO.isIdenticalTo(OMO))
826 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
830 if (!MO.isIdenticalTo(OMO))
832 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
836 // If DebugLoc does not match then two dbg.values are not identical.
838 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
839 && getDebugLoc() != Other->getDebugLoc())
844 /// removeFromParent - This method unlinks 'this' from the containing basic
845 /// block, and returns it, but does not delete it.
846 MachineInstr *MachineInstr::removeFromParent() {
847 assert(getParent() && "Not embedded in a basic block!");
849 // If it's a bundle then remove the MIs inside the bundle as well.
851 MachineBasicBlock *MBB = getParent();
852 MachineBasicBlock::instr_iterator MII = *this; ++MII;
853 MachineBasicBlock::instr_iterator E = MBB->instr_end();
854 while (MII != E && MII->isInsideBundle()) {
855 MachineInstr *MI = &*MII;
860 getParent()->remove(this);
865 /// eraseFromParent - This method unlinks 'this' from the containing basic
866 /// block, and deletes it.
867 void MachineInstr::eraseFromParent() {
868 assert(getParent() && "Not embedded in a basic block!");
869 // If it's a bundle then remove the MIs inside the bundle as well.
871 MachineBasicBlock *MBB = getParent();
872 MachineBasicBlock::instr_iterator MII = *this; ++MII;
873 MachineBasicBlock::instr_iterator E = MBB->instr_end();
874 while (MII != E && MII->isInsideBundle()) {
875 MachineInstr *MI = &*MII;
880 // Erase the individual instruction, which may itself be inside a bundle.
881 getParent()->erase_instr(this);
885 /// getNumExplicitOperands - Returns the number of non-implicit operands.
887 unsigned MachineInstr::getNumExplicitOperands() const {
888 unsigned NumOperands = MCID->getNumOperands();
889 if (!MCID->isVariadic())
892 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
893 const MachineOperand &MO = getOperand(i);
894 if (!MO.isReg() || !MO.isImplicit())
900 /// isBundled - Return true if this instruction part of a bundle. This is true
901 /// if either itself or its following instruction is marked "InsideBundle".
902 bool MachineInstr::isBundled() const {
903 if (isInsideBundle())
905 MachineBasicBlock::const_instr_iterator nextMI = this;
907 return nextMI != Parent->instr_end() && nextMI->isInsideBundle();
910 bool MachineInstr::isStackAligningInlineAsm() const {
912 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
913 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
919 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
920 unsigned *GroupNo) const {
921 assert(isInlineAsm() && "Expected an inline asm instruction");
922 assert(OpIdx < getNumOperands() && "OpIdx out of range");
924 // Ignore queries about the initial operands.
925 if (OpIdx < InlineAsm::MIOp_FirstOperand)
930 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
932 const MachineOperand &FlagMO = getOperand(i);
933 // If we reach the implicit register operands, stop looking.
936 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
937 if (i + NumOps > OpIdx) {
947 const TargetRegisterClass*
948 MachineInstr::getRegClassConstraint(unsigned OpIdx,
949 const TargetInstrInfo *TII,
950 const TargetRegisterInfo *TRI) const {
951 assert(getParent() && "Can't have an MBB reference here!");
952 assert(getParent()->getParent() && "Can't have an MF reference here!");
953 const MachineFunction &MF = *getParent()->getParent();
955 // Most opcodes have fixed constraints in their MCInstrDesc.
957 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
959 if (!getOperand(OpIdx).isReg())
962 // For tied uses on inline asm, get the constraint from the def.
964 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
967 // Inline asm stores register class constraints in the flag word.
968 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
972 unsigned Flag = getOperand(FlagIdx).getImm();
974 if (InlineAsm::hasRegClassConstraint(Flag, RCID))
975 return TRI->getRegClass(RCID);
977 // Assume that all registers in a memory operand are pointers.
978 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
979 return TRI->getPointerRegClass(MF);
984 /// getBundleSize - Return the number of instructions inside the MI bundle.
985 unsigned MachineInstr::getBundleSize() const {
986 assert(isBundle() && "Expecting a bundle");
988 MachineBasicBlock::const_instr_iterator I = *this;
990 while ((++I)->isInsideBundle()) {
993 assert(Size > 1 && "Malformed bundle");
998 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
999 /// the specific register or -1 if it is not found. It further tightens
1000 /// the search criteria to a use that kills the register if isKill is true.
1001 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
1002 const TargetRegisterInfo *TRI) const {
1003 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1004 const MachineOperand &MO = getOperand(i);
1005 if (!MO.isReg() || !MO.isUse())
1007 unsigned MOReg = MO.getReg();
1012 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1013 TargetRegisterInfo::isPhysicalRegister(Reg) &&
1014 TRI->isSubRegister(MOReg, Reg)))
1015 if (!isKill || MO.isKill())
1021 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1022 /// indicating if this instruction reads or writes Reg. This also considers
1023 /// partial defines.
1024 std::pair<bool,bool>
1025 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1026 SmallVectorImpl<unsigned> *Ops) const {
1027 bool PartDef = false; // Partial redefine.
1028 bool FullDef = false; // Full define.
1031 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1032 const MachineOperand &MO = getOperand(i);
1033 if (!MO.isReg() || MO.getReg() != Reg)
1038 Use |= !MO.isUndef();
1039 else if (MO.getSubReg() && !MO.isUndef())
1040 // A partial <def,undef> doesn't count as reading the register.
1045 // A partial redefine uses Reg unless there is also a full define.
1046 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1049 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1050 /// the specified register or -1 if it is not found. If isDead is true, defs
1051 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1052 /// also checks if there is a def of a super-register.
1054 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1055 const TargetRegisterInfo *TRI) const {
1056 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1057 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1058 const MachineOperand &MO = getOperand(i);
1059 // Accept regmask operands when Overlap is set.
1060 // Ignore them when looking for a specific def operand (Overlap == false).
1061 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1063 if (!MO.isReg() || !MO.isDef())
1065 unsigned MOReg = MO.getReg();
1066 bool Found = (MOReg == Reg);
1067 if (!Found && TRI && isPhys &&
1068 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1070 Found = TRI->regsOverlap(MOReg, Reg);
1072 Found = TRI->isSubRegister(MOReg, Reg);
1074 if (Found && (!isDead || MO.isDead()))
1080 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1081 /// operand list that is used to represent the predicate. It returns -1 if
1083 int MachineInstr::findFirstPredOperandIdx() const {
1084 // Don't call MCID.findFirstPredOperandIdx() because this variant
1085 // is sometimes called on an instruction that's not yet complete, and
1086 // so the number of operands is less than the MCID indicates. In
1087 // particular, the PTX target does this.
1088 const MCInstrDesc &MCID = getDesc();
1089 if (MCID.isPredicable()) {
1090 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1091 if (MCID.OpInfo[i].isPredicate())
1098 /// isRegTiedToUseOperand - Given the index of a register def operand,
1099 /// check if the register def is tied to a source operand, due to either
1100 /// two-address elimination or inline assembly constraints. Returns the
1101 /// first tied use operand index by reference is UseOpIdx is not null.
1103 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
1104 if (isInlineAsm()) {
1105 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
1106 const MachineOperand &MO = getOperand(DefOpIdx);
1107 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
1109 // Determine the actual operand index that corresponds to this index.
1111 int FlagIdx = findInlineAsmFlagIdx(DefOpIdx, &DefNo);
1115 // Which part of the group is DefOpIdx?
1116 unsigned DefPart = DefOpIdx - (FlagIdx + 1);
1118 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
1120 const MachineOperand &FMO = getOperand(i);
1123 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
1126 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
1129 *UseOpIdx = (unsigned)i + 1 + DefPart;
1136 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
1137 const MCInstrDesc &MCID = getDesc();
1138 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
1139 const MachineOperand &MO = getOperand(i);
1140 if (MO.isReg() && MO.isUse() &&
1141 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
1143 *UseOpIdx = (unsigned)i;
1150 /// isRegTiedToDefOperand - Return true if the operand of the specified index
1151 /// is a register use and it is tied to an def operand. It also returns the def
1152 /// operand index by reference.
1154 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
1155 if (isInlineAsm()) {
1156 const MachineOperand &MO = getOperand(UseOpIdx);
1157 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
1160 // Find the flag operand corresponding to UseOpIdx
1161 int FlagIdx = findInlineAsmFlagIdx(UseOpIdx);
1165 const MachineOperand &UFMO = getOperand(FlagIdx);
1167 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1171 unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1172 // Remember to adjust the index. First operand is asm string, second is
1173 // the HasSideEffects and AlignStack bits, then there is a flag for each.
1175 const MachineOperand &FMO = getOperand(DefIdx);
1176 assert(FMO.isImm());
1177 // Skip over this def.
1178 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1181 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1187 const MCInstrDesc &MCID = getDesc();
1188 if (UseOpIdx >= MCID.getNumOperands())
1190 const MachineOperand &MO = getOperand(UseOpIdx);
1191 if (!MO.isReg() || !MO.isUse())
1193 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
1197 *DefOpIdx = (unsigned)DefIdx;
1201 /// clearKillInfo - Clears kill flags on all operands.
1203 void MachineInstr::clearKillInfo() {
1204 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1205 MachineOperand &MO = getOperand(i);
1206 if (MO.isReg() && MO.isUse())
1207 MO.setIsKill(false);
1211 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1213 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1214 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1215 const MachineOperand &MO = MI->getOperand(i);
1216 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1218 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1219 MachineOperand &MOp = getOperand(j);
1220 if (!MOp.isIdenticalTo(MO))
1231 /// copyPredicates - Copies predicate operand(s) from MI.
1232 void MachineInstr::copyPredicates(const MachineInstr *MI) {
1233 assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles");
1235 const MCInstrDesc &MCID = MI->getDesc();
1236 if (!MCID.isPredicable())
1238 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1239 if (MCID.OpInfo[i].isPredicate()) {
1240 // Predicated operands must be last operands.
1241 addOperand(MI->getOperand(i));
1246 void MachineInstr::substituteRegister(unsigned FromReg,
1249 const TargetRegisterInfo &RegInfo) {
1250 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1252 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1253 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1254 MachineOperand &MO = getOperand(i);
1255 if (!MO.isReg() || MO.getReg() != FromReg)
1257 MO.substPhysReg(ToReg, RegInfo);
1260 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1261 MachineOperand &MO = getOperand(i);
1262 if (!MO.isReg() || MO.getReg() != FromReg)
1264 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1269 /// isSafeToMove - Return true if it is safe to move this instruction. If
1270 /// SawStore is set to true, it means that there is a store (or call) between
1271 /// the instruction's location and its intended destination.
1272 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1274 bool &SawStore) const {
1275 // Ignore stuff that we obviously can't move.
1276 if (mayStore() || isCall()) {
1281 if (isLabel() || isDebugValue() ||
1282 isTerminator() || hasUnmodeledSideEffects())
1285 // See if this instruction does a load. If so, we have to guarantee that the
1286 // loaded value doesn't change between the load and the its intended
1287 // destination. The check for isInvariantLoad gives the targe the chance to
1288 // classify the load as always returning a constant, e.g. a constant pool
1290 if (mayLoad() && !isInvariantLoad(AA))
1291 // Otherwise, this is a real load. If there is a store between the load and
1292 // end of block, or if the load is volatile, we can't move it.
1293 return !SawStore && !hasVolatileMemoryRef();
1298 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1299 /// instruction which defined the specified register instead of copying it.
1300 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1302 unsigned DstReg) const {
1303 bool SawStore = false;
1304 if (!TII->isTriviallyReMaterializable(this, AA) ||
1305 !isSafeToMove(TII, AA, SawStore))
1307 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1308 const MachineOperand &MO = getOperand(i);
1311 // FIXME: For now, do not remat any instruction with register operands.
1312 // Later on, we can loosen the restriction is the register operands have
1313 // not been modified between the def and use. Note, this is different from
1314 // MachineSink because the code is no longer in two-address form (at least
1318 else if (!MO.isDead() && MO.getReg() != DstReg)
1324 /// hasVolatileMemoryRef - Return true if this instruction may have a
1325 /// volatile memory reference, or if the information describing the
1326 /// memory reference is not available. Return false if it is known to
1327 /// have no volatile memory references.
1328 bool MachineInstr::hasVolatileMemoryRef() const {
1329 // An instruction known never to access memory won't have a volatile access.
1333 !hasUnmodeledSideEffects())
1336 // Otherwise, if the instruction has no memory reference information,
1337 // conservatively assume it wasn't preserved.
1338 if (memoperands_empty())
1341 // Check the memory reference information for volatile references.
1342 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1343 if ((*I)->isVolatile())
1349 /// isInvariantLoad - Return true if this instruction is loading from a
1350 /// location whose value is invariant across the function. For example,
1351 /// loading a value from the constant pool or from the argument area
1352 /// of a function if it does not change. This should only return true of
1353 /// *all* loads the instruction does are invariant (if it does multiple loads).
1354 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1355 // If the instruction doesn't load at all, it isn't an invariant load.
1359 // If the instruction has lost its memoperands, conservatively assume that
1360 // it may not be an invariant load.
1361 if (memoperands_empty())
1364 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1366 for (mmo_iterator I = memoperands_begin(),
1367 E = memoperands_end(); I != E; ++I) {
1368 if ((*I)->isVolatile()) return false;
1369 if ((*I)->isStore()) return false;
1370 if ((*I)->isInvariant()) return true;
1372 if (const Value *V = (*I)->getValue()) {
1373 // A load from a constant PseudoSourceValue is invariant.
1374 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1375 if (PSV->isConstant(MFI))
1377 // If we have an AliasAnalysis, ask it whether the memory is constant.
1378 if (AA && AA->pointsToConstantMemory(
1379 AliasAnalysis::Location(V, (*I)->getSize(),
1380 (*I)->getTBAAInfo())))
1384 // Otherwise assume conservatively.
1388 // Everything checks out.
1392 /// isConstantValuePHI - If the specified instruction is a PHI that always
1393 /// merges together the same virtual register, return the register, otherwise
1395 unsigned MachineInstr::isConstantValuePHI() const {
1398 assert(getNumOperands() >= 3 &&
1399 "It's illegal to have a PHI without source operands");
1401 unsigned Reg = getOperand(1).getReg();
1402 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1403 if (getOperand(i).getReg() != Reg)
1408 bool MachineInstr::hasUnmodeledSideEffects() const {
1409 if (hasProperty(MCID::UnmodeledSideEffects))
1411 if (isInlineAsm()) {
1412 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1413 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1420 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1422 bool MachineInstr::allDefsAreDead() const {
1423 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1424 const MachineOperand &MO = getOperand(i);
1425 if (!MO.isReg() || MO.isUse())
1433 /// copyImplicitOps - Copy implicit register operands from specified
1434 /// instruction to this instruction.
1435 void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1436 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1438 const MachineOperand &MO = MI->getOperand(i);
1439 if (MO.isReg() && MO.isImplicit())
1444 void MachineInstr::dump() const {
1445 dbgs() << " " << *this;
1448 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1449 raw_ostream &CommentOS) {
1450 const LLVMContext &Ctx = MF->getFunction()->getContext();
1451 if (!DL.isUnknown()) { // Print source line info.
1452 DIScope Scope(DL.getScope(Ctx));
1453 // Omit the directory, because it's likely to be long and uninteresting.
1455 CommentOS << Scope.getFilename();
1457 CommentOS << "<unknown>";
1458 CommentOS << ':' << DL.getLine();
1459 if (DL.getCol() != 0)
1460 CommentOS << ':' << DL.getCol();
1461 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1462 if (!InlinedAtDL.isUnknown()) {
1463 CommentOS << " @[ ";
1464 printDebugLoc(InlinedAtDL, MF, CommentOS);
1470 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1471 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1472 const MachineFunction *MF = 0;
1473 const MachineRegisterInfo *MRI = 0;
1474 if (const MachineBasicBlock *MBB = getParent()) {
1475 MF = MBB->getParent();
1477 TM = &MF->getTarget();
1479 MRI = &MF->getRegInfo();
1482 // Save a list of virtual registers.
1483 SmallVector<unsigned, 8> VirtRegs;
1485 // Print explicitly defined operands on the left of an assignment syntax.
1486 unsigned StartOp = 0, e = getNumOperands();
1487 for (; StartOp < e && getOperand(StartOp).isReg() &&
1488 getOperand(StartOp).isDef() &&
1489 !getOperand(StartOp).isImplicit();
1491 if (StartOp != 0) OS << ", ";
1492 getOperand(StartOp).print(OS, TM);
1493 unsigned Reg = getOperand(StartOp).getReg();
1494 if (TargetRegisterInfo::isVirtualRegister(Reg))
1495 VirtRegs.push_back(Reg);
1501 // Print the opcode name.
1502 if (TM && TM->getInstrInfo())
1503 OS << TM->getInstrInfo()->getName(getOpcode());
1507 // Print the rest of the operands.
1508 bool OmittedAnyCallClobbers = false;
1509 bool FirstOp = true;
1510 unsigned AsmDescOp = ~0u;
1511 unsigned AsmOpCount = 0;
1513 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1514 // Print asm string.
1516 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1518 // Print HasSideEffects, IsAlignStack
1519 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1520 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1521 OS << " [sideeffect]";
1522 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1523 OS << " [alignstack]";
1525 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1530 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1531 const MachineOperand &MO = getOperand(i);
1533 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1534 VirtRegs.push_back(MO.getReg());
1536 // Omit call-clobbered registers which aren't used anywhere. This makes
1537 // call instructions much less noisy on targets where calls clobber lots
1538 // of registers. Don't rely on MO.isDead() because we may be called before
1539 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1540 if (MF && isCall() &&
1541 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1542 unsigned Reg = MO.getReg();
1543 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1544 const MachineRegisterInfo &MRI = MF->getRegInfo();
1545 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1546 bool HasAliasLive = false;
1547 for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
1548 AI.isValid(); ++AI) {
1549 unsigned AliasReg = *AI;
1550 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1551 HasAliasLive = true;
1555 if (!HasAliasLive) {
1556 OmittedAnyCallClobbers = true;
1563 if (FirstOp) FirstOp = false; else OS << ",";
1565 if (i < getDesc().NumOperands) {
1566 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1567 if (MCOI.isPredicate())
1569 if (MCOI.isOptionalDef())
1572 if (isDebugValue() && MO.isMetadata()) {
1573 // Pretty print DBG_VALUE instructions.
1574 const MDNode *MD = MO.getMetadata();
1575 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1576 OS << "!\"" << MDS->getString() << '\"';
1579 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1580 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1581 } else if (i == AsmDescOp && MO.isImm()) {
1582 // Pretty print the inline asm operand descriptor.
1583 OS << '$' << AsmOpCount++;
1584 unsigned Flag = MO.getImm();
1585 switch (InlineAsm::getKind(Flag)) {
1586 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1587 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1588 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1589 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1590 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1591 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1592 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1596 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1598 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1600 OS << ":RC" << RCID;
1603 unsigned TiedTo = 0;
1604 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1605 OS << " tiedto:$" << TiedTo;
1609 // Compute the index of the next operand descriptor.
1610 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1615 // Briefly indicate whether any call clobbers were omitted.
1616 if (OmittedAnyCallClobbers) {
1617 if (!FirstOp) OS << ",";
1621 bool HaveSemi = false;
1623 if (!HaveSemi) OS << ";"; HaveSemi = true;
1626 if (Flags & FrameSetup)
1630 if (!memoperands_empty()) {
1631 if (!HaveSemi) OS << ";"; HaveSemi = true;
1634 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1637 if (llvm::next(i) != e)
1642 // Print the regclass of any virtual registers encountered.
1643 if (MRI && !VirtRegs.empty()) {
1644 if (!HaveSemi) OS << ";"; HaveSemi = true;
1645 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1646 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1647 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1648 for (unsigned j = i+1; j != VirtRegs.size();) {
1649 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1653 if (VirtRegs[i] != VirtRegs[j])
1654 OS << "," << PrintReg(VirtRegs[j]);
1655 VirtRegs.erase(VirtRegs.begin()+j);
1660 // Print debug location information.
1661 if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1662 if (!HaveSemi) OS << ";"; HaveSemi = true;
1663 DIVariable DV(getOperand(e - 1).getMetadata());
1664 OS << " line no:" << DV.getLineNumber();
1665 if (MDNode *InlinedAt = DV.getInlinedAt()) {
1666 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1667 if (!InlinedAtDL.isUnknown()) {
1668 OS << " inlined @[ ";
1669 printDebugLoc(InlinedAtDL, MF, OS);
1673 } else if (!debugLoc.isUnknown() && MF) {
1674 if (!HaveSemi) OS << ";"; HaveSemi = true;
1676 printDebugLoc(debugLoc, MF, OS);
1682 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1683 const TargetRegisterInfo *RegInfo,
1684 bool AddIfNotFound) {
1685 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1686 bool hasAliases = isPhysReg &&
1687 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1689 SmallVector<unsigned,4> DeadOps;
1690 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1691 MachineOperand &MO = getOperand(i);
1692 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1694 unsigned Reg = MO.getReg();
1698 if (Reg == IncomingReg) {
1701 // The register is already marked kill.
1703 if (isPhysReg && isRegTiedToDefOperand(i))
1704 // Two-address uses of physregs must not be marked kill.
1709 } else if (hasAliases && MO.isKill() &&
1710 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1711 // A super-register kill already exists.
1712 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1714 if (RegInfo->isSubRegister(IncomingReg, Reg))
1715 DeadOps.push_back(i);
1719 // Trim unneeded kill operands.
1720 while (!DeadOps.empty()) {
1721 unsigned OpIdx = DeadOps.back();
1722 if (getOperand(OpIdx).isImplicit())
1723 RemoveOperand(OpIdx);
1725 getOperand(OpIdx).setIsKill(false);
1729 // If not found, this means an alias of one of the operands is killed. Add a
1730 // new implicit operand if required.
1731 if (!Found && AddIfNotFound) {
1732 addOperand(MachineOperand::CreateReg(IncomingReg,
1741 void MachineInstr::clearRegisterKills(unsigned Reg,
1742 const TargetRegisterInfo *RegInfo) {
1743 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1745 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1746 MachineOperand &MO = getOperand(i);
1747 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1749 unsigned OpReg = MO.getReg();
1750 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1751 MO.setIsKill(false);
1755 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1756 const TargetRegisterInfo *RegInfo,
1757 bool AddIfNotFound) {
1758 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1759 bool hasAliases = isPhysReg &&
1760 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1762 SmallVector<unsigned,4> DeadOps;
1763 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1764 MachineOperand &MO = getOperand(i);
1765 if (!MO.isReg() || !MO.isDef())
1767 unsigned Reg = MO.getReg();
1771 if (Reg == IncomingReg) {
1774 } else if (hasAliases && MO.isDead() &&
1775 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1776 // There exists a super-register that's marked dead.
1777 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1779 if (RegInfo->isSubRegister(IncomingReg, Reg))
1780 DeadOps.push_back(i);
1784 // Trim unneeded dead operands.
1785 while (!DeadOps.empty()) {
1786 unsigned OpIdx = DeadOps.back();
1787 if (getOperand(OpIdx).isImplicit())
1788 RemoveOperand(OpIdx);
1790 getOperand(OpIdx).setIsDead(false);
1794 // If not found, this means an alias of one of the operands is dead. Add a
1795 // new implicit operand if required.
1796 if (Found || !AddIfNotFound)
1799 addOperand(MachineOperand::CreateReg(IncomingReg,
1807 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1808 const TargetRegisterInfo *RegInfo) {
1809 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1810 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1814 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1815 const MachineOperand &MO = getOperand(i);
1816 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1817 MO.getSubReg() == 0)
1821 addOperand(MachineOperand::CreateReg(IncomingReg,
1826 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1827 const TargetRegisterInfo &TRI) {
1828 bool HasRegMask = false;
1829 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1830 MachineOperand &MO = getOperand(i);
1831 if (MO.isRegMask()) {
1835 if (!MO.isReg() || !MO.isDef()) continue;
1836 unsigned Reg = MO.getReg();
1837 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1839 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1841 if (TRI.regsOverlap(*I, Reg)) {
1845 // If there are no uses, including partial uses, the def is dead.
1846 if (Dead) MO.setIsDead();
1849 // This is a call with a register mask operand.
1850 // Mask clobbers are always dead, so add defs for the non-dead defines.
1852 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1854 addRegisterDefined(*I, &TRI);
1858 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1859 // Build up a buffer of hash code components.
1860 SmallVector<size_t, 8> HashComponents;
1861 HashComponents.reserve(MI->getNumOperands() + 1);
1862 HashComponents.push_back(MI->getOpcode());
1863 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1864 const MachineOperand &MO = MI->getOperand(i);
1865 if (MO.isReg() && MO.isDef() &&
1866 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1867 continue; // Skip virtual register defs.
1869 HashComponents.push_back(hash_value(MO));
1871 return hash_combine_range(HashComponents.begin(), HashComponents.end());
1874 void MachineInstr::emitError(StringRef Msg) const {
1875 // Find the source location cookie.
1876 unsigned LocCookie = 0;
1877 const MDNode *LocMD = 0;
1878 for (unsigned i = getNumOperands(); i != 0; --i) {
1879 if (getOperand(i-1).isMetadata() &&
1880 (LocMD = getOperand(i-1).getMetadata()) &&
1881 LocMD->getNumOperands() != 0) {
1882 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1883 LocCookie = CI->getZExtValue();
1889 if (const MachineBasicBlock *MBB = getParent())
1890 if (const MachineFunction *MF = MBB->getParent())
1891 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1892 report_fatal_error(Msg);