1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Function.h"
17 #include "llvm/InlineAsm.h"
18 #include "llvm/LLVMContext.h"
19 #include "llvm/Metadata.h"
20 #include "llvm/Module.h"
21 #include "llvm/Type.h"
22 #include "llvm/Value.h"
23 #include "llvm/Assembly/Writer.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCSymbol.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Analysis/AliasAnalysis.h"
36 #include "llvm/Analysis/DebugInfo.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/LeakDetector.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/FoldingSet.h"
43 #include "llvm/ADT/Hashing.h"
46 //===----------------------------------------------------------------------===//
47 // MachineOperand Implementation
48 //===----------------------------------------------------------------------===//
50 /// AddRegOperandToRegInfo - Add this register operand to the specified
51 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
52 /// explicitly nulled out.
53 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
54 assert(isReg() && "Can only add reg operand to use lists");
56 // If the reginfo pointer is null, just explicitly null out or next/prev
57 // pointers, to ensure they are not garbage.
59 Contents.Reg.Prev = 0;
60 Contents.Reg.Next = 0;
64 // Otherwise, add this operand to the head of the registers use/def list.
65 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
67 // For SSA values, we prefer to keep the definition at the start of the list.
68 // we do this by skipping over the definition if it is at the head of the
70 if (*Head && (*Head)->isDef())
71 Head = &(*Head)->Contents.Reg.Next;
73 Contents.Reg.Next = *Head;
74 if (Contents.Reg.Next) {
75 assert(getReg() == Contents.Reg.Next->getReg() &&
76 "Different regs on the same list!");
77 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
80 Contents.Reg.Prev = Head;
84 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
85 /// MachineRegisterInfo it is linked with.
86 void MachineOperand::RemoveRegOperandFromRegInfo() {
87 assert(isOnRegUseList() && "Reg operand is not on a use list");
88 // Unlink this from the doubly linked list of operands.
89 MachineOperand *NextOp = Contents.Reg.Next;
90 *Contents.Reg.Prev = NextOp;
92 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
93 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
95 Contents.Reg.Prev = 0;
96 Contents.Reg.Next = 0;
99 void MachineOperand::setReg(unsigned Reg) {
100 if (getReg() == Reg) return; // No change.
102 // Otherwise, we have to change the register. If this operand is embedded
103 // into a machine function, we need to update the old and new register's
105 if (MachineInstr *MI = getParent())
106 if (MachineBasicBlock *MBB = MI->getParent())
107 if (MachineFunction *MF = MBB->getParent()) {
108 RemoveRegOperandFromRegInfo();
109 SmallContents.RegNo = Reg;
110 AddRegOperandToRegInfo(&MF->getRegInfo());
114 // Otherwise, just change the register, no problem. :)
115 SmallContents.RegNo = Reg;
118 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
119 const TargetRegisterInfo &TRI) {
120 assert(TargetRegisterInfo::isVirtualRegister(Reg));
121 if (SubIdx && getSubReg())
122 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
128 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
129 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
131 Reg = TRI.getSubReg(Reg, getSubReg());
132 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
133 // That won't happen in legal code.
139 /// ChangeToImmediate - Replace this operand with a new immediate operand of
140 /// the specified value. If an operand is known to be an immediate already,
141 /// the setImm method should be used.
142 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
143 // If this operand is currently a register operand, and if this is in a
144 // function, deregister the operand from the register's use/def list.
145 if (isReg() && getParent() && getParent()->getParent() &&
146 getParent()->getParent()->getParent())
147 RemoveRegOperandFromRegInfo();
149 OpKind = MO_Immediate;
150 Contents.ImmVal = ImmVal;
153 /// ChangeToRegister - Replace this operand with a new register operand of
154 /// the specified value. If an operand is known to be an register already,
155 /// the setReg method should be used.
156 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
157 bool isKill, bool isDead, bool isUndef,
159 // If this operand is already a register operand, use setReg to update the
160 // register's use/def lists.
162 assert(!isEarlyClobber());
165 // Otherwise, change this to a register and set the reg#.
166 OpKind = MO_Register;
167 SmallContents.RegNo = Reg;
169 // If this operand is embedded in a function, add the operand to the
170 // register's use/def list.
171 if (MachineInstr *MI = getParent())
172 if (MachineBasicBlock *MBB = MI->getParent())
173 if (MachineFunction *MF = MBB->getParent())
174 AddRegOperandToRegInfo(&MF->getRegInfo());
182 IsInternalRead = false;
183 IsEarlyClobber = false;
188 /// isIdenticalTo - Return true if this operand is identical to the specified
190 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
191 if (getType() != Other.getType() ||
192 getTargetFlags() != Other.getTargetFlags())
196 case MachineOperand::MO_Register:
197 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
198 getSubReg() == Other.getSubReg();
199 case MachineOperand::MO_Immediate:
200 return getImm() == Other.getImm();
201 case MachineOperand::MO_CImmediate:
202 return getCImm() == Other.getCImm();
203 case MachineOperand::MO_FPImmediate:
204 return getFPImm() == Other.getFPImm();
205 case MachineOperand::MO_MachineBasicBlock:
206 return getMBB() == Other.getMBB();
207 case MachineOperand::MO_FrameIndex:
208 return getIndex() == Other.getIndex();
209 case MachineOperand::MO_ConstantPoolIndex:
210 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
211 case MachineOperand::MO_JumpTableIndex:
212 return getIndex() == Other.getIndex();
213 case MachineOperand::MO_GlobalAddress:
214 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
215 case MachineOperand::MO_ExternalSymbol:
216 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
217 getOffset() == Other.getOffset();
218 case MachineOperand::MO_BlockAddress:
219 return getBlockAddress() == Other.getBlockAddress();
220 case MO_RegisterMask:
221 return getRegMask() == Other.getRegMask();
222 case MachineOperand::MO_MCSymbol:
223 return getMCSymbol() == Other.getMCSymbol();
224 case MachineOperand::MO_Metadata:
225 return getMetadata() == Other.getMetadata();
227 llvm_unreachable("Invalid machine operand type");
230 /// print - Print the specified machine operand.
232 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
233 // If the instruction is embedded into a basic block, we can find the
234 // target info for the instruction.
236 if (const MachineInstr *MI = getParent())
237 if (const MachineBasicBlock *MBB = MI->getParent())
238 if (const MachineFunction *MF = MBB->getParent())
239 TM = &MF->getTarget();
240 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
243 case MachineOperand::MO_Register:
244 OS << PrintReg(getReg(), TRI, getSubReg());
246 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
247 isInternalRead() || isEarlyClobber()) {
249 bool NeedComma = false;
251 if (NeedComma) OS << ',';
252 if (isEarlyClobber())
253 OS << "earlyclobber,";
258 // <def,read-undef> only makes sense when getSubReg() is set.
259 // Don't clutter the output otherwise.
260 if (isUndef() && getSubReg())
262 } else if (isImplicit()) {
267 if (isKill() || isDead() || (isUndef() && isUse()) || isInternalRead()) {
268 if (NeedComma) OS << ',';
278 if (isUndef() && isUse()) {
279 if (NeedComma) OS << ',';
283 if (isInternalRead()) {
284 if (NeedComma) OS << ',';
292 case MachineOperand::MO_Immediate:
295 case MachineOperand::MO_CImmediate:
296 getCImm()->getValue().print(OS, false);
298 case MachineOperand::MO_FPImmediate:
299 if (getFPImm()->getType()->isFloatTy())
300 OS << getFPImm()->getValueAPF().convertToFloat();
302 OS << getFPImm()->getValueAPF().convertToDouble();
304 case MachineOperand::MO_MachineBasicBlock:
305 OS << "<BB#" << getMBB()->getNumber() << ">";
307 case MachineOperand::MO_FrameIndex:
308 OS << "<fi#" << getIndex() << '>';
310 case MachineOperand::MO_ConstantPoolIndex:
311 OS << "<cp#" << getIndex();
312 if (getOffset()) OS << "+" << getOffset();
315 case MachineOperand::MO_JumpTableIndex:
316 OS << "<jt#" << getIndex() << '>';
318 case MachineOperand::MO_GlobalAddress:
320 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
321 if (getOffset()) OS << "+" << getOffset();
324 case MachineOperand::MO_ExternalSymbol:
325 OS << "<es:" << getSymbolName();
326 if (getOffset()) OS << "+" << getOffset();
329 case MachineOperand::MO_BlockAddress:
331 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
334 case MachineOperand::MO_RegisterMask:
337 case MachineOperand::MO_Metadata:
339 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
342 case MachineOperand::MO_MCSymbol:
343 OS << "<MCSym=" << *getMCSymbol() << '>';
347 if (unsigned TF = getTargetFlags())
348 OS << "[TF=" << TF << ']';
351 //===----------------------------------------------------------------------===//
352 // MachineMemOperand Implementation
353 //===----------------------------------------------------------------------===//
355 /// getAddrSpace - Return the LLVM IR address space number that this pointer
357 unsigned MachinePointerInfo::getAddrSpace() const {
358 if (V == 0) return 0;
359 return cast<PointerType>(V->getType())->getAddressSpace();
362 /// getConstantPool - Return a MachinePointerInfo record that refers to the
364 MachinePointerInfo MachinePointerInfo::getConstantPool() {
365 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
368 /// getFixedStack - Return a MachinePointerInfo record that refers to the
369 /// the specified FrameIndex.
370 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
371 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
374 MachinePointerInfo MachinePointerInfo::getJumpTable() {
375 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
378 MachinePointerInfo MachinePointerInfo::getGOT() {
379 return MachinePointerInfo(PseudoSourceValue::getGOT());
382 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
383 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
386 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
387 uint64_t s, unsigned int a,
388 const MDNode *TBAAInfo,
389 const MDNode *Ranges)
390 : PtrInfo(ptrinfo), Size(s),
391 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
392 TBAAInfo(TBAAInfo), Ranges(Ranges) {
393 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
394 "invalid pointer value");
395 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
396 assert((isLoad() || isStore()) && "Not a load/store!");
399 /// Profile - Gather unique data for the object.
401 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
402 ID.AddInteger(getOffset());
404 ID.AddPointer(getValue());
405 ID.AddInteger(Flags);
408 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
409 // The Value and Offset may differ due to CSE. But the flags and size
410 // should be the same.
411 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
412 assert(MMO->getSize() == getSize() && "Size mismatch!");
414 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
415 // Update the alignment value.
416 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
417 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
418 // Also update the base and offset, because the new alignment may
419 // not be applicable with the old ones.
420 PtrInfo = MMO->PtrInfo;
424 /// getAlignment - Return the minimum known alignment in bytes of the
425 /// actual memory reference.
426 uint64_t MachineMemOperand::getAlignment() const {
427 return MinAlign(getBaseAlignment(), getOffset());
430 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
431 assert((MMO.isLoad() || MMO.isStore()) &&
432 "SV has to be a load, store or both.");
434 if (MMO.isVolatile())
443 // Print the address information.
448 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
450 // If the alignment of the memory reference itself differs from the alignment
451 // of the base pointer, print the base alignment explicitly, next to the base
453 if (MMO.getBaseAlignment() != MMO.getAlignment())
454 OS << "(align=" << MMO.getBaseAlignment() << ")";
456 if (MMO.getOffset() != 0)
457 OS << "+" << MMO.getOffset();
460 // Print the alignment of the reference.
461 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
462 MMO.getBaseAlignment() != MMO.getSize())
463 OS << "(align=" << MMO.getAlignment() << ")";
466 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
468 if (TBAAInfo->getNumOperands() > 0)
469 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
475 // Print nontemporal info.
476 if (MMO.isNonTemporal())
477 OS << "(nontemporal)";
482 //===----------------------------------------------------------------------===//
483 // MachineInstr Implementation
484 //===----------------------------------------------------------------------===//
486 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
487 /// MCID NULL and no operands.
488 MachineInstr::MachineInstr()
489 : MCID(0), Flags(0), AsmPrinterFlags(0),
490 NumMemRefs(0), MemRefs(0),
492 // Make sure that we get added to a machine basicblock
493 LeakDetector::addGarbageObject(this);
496 void MachineInstr::addImplicitDefUseOperands() {
497 if (MCID->ImplicitDefs)
498 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
499 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
500 if (MCID->ImplicitUses)
501 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
502 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
505 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
506 /// implicit operands. It reserves space for the number of operands specified by
508 MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
509 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
510 NumMemRefs(0), MemRefs(0), Parent(0) {
511 unsigned NumImplicitOps = 0;
513 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
514 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
516 addImplicitDefUseOperands();
517 // Make sure that we get added to a machine basicblock
518 LeakDetector::addGarbageObject(this);
521 /// MachineInstr ctor - As above, but with a DebugLoc.
522 MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
524 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
525 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
526 unsigned NumImplicitOps = 0;
528 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
529 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
531 addImplicitDefUseOperands();
532 // Make sure that we get added to a machine basicblock
533 LeakDetector::addGarbageObject(this);
536 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
537 /// that the MachineInstr is created and added to the end of the specified
539 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
540 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
541 NumMemRefs(0), MemRefs(0), Parent(0) {
542 assert(MBB && "Cannot use inserting ctor with null basic block!");
543 unsigned NumImplicitOps =
544 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
545 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
546 addImplicitDefUseOperands();
547 // Make sure that we get added to a machine basicblock
548 LeakDetector::addGarbageObject(this);
549 MBB->push_back(this); // Add instruction to end of basic block!
552 /// MachineInstr ctor - As above, but with a DebugLoc.
554 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
555 const MCInstrDesc &tid)
556 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
557 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
558 assert(MBB && "Cannot use inserting ctor with null basic block!");
559 unsigned NumImplicitOps =
560 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
561 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
562 addImplicitDefUseOperands();
563 // Make sure that we get added to a machine basicblock
564 LeakDetector::addGarbageObject(this);
565 MBB->push_back(this); // Add instruction to end of basic block!
568 /// MachineInstr ctor - Copies MachineInstr arg exactly
570 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
571 : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
572 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
573 Parent(0), debugLoc(MI.getDebugLoc()) {
574 Operands.reserve(MI.getNumOperands());
577 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
578 addOperand(MI.getOperand(i));
580 // Copy all the flags.
583 // Set parent to null.
586 LeakDetector::addGarbageObject(this);
589 MachineInstr::~MachineInstr() {
590 LeakDetector::removeGarbageObject(this);
592 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
593 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
594 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
595 "Reg operand def/use list corrupted");
600 /// getRegInfo - If this instruction is embedded into a MachineFunction,
601 /// return the MachineRegisterInfo object for the current function, otherwise
603 MachineRegisterInfo *MachineInstr::getRegInfo() {
604 if (MachineBasicBlock *MBB = getParent())
605 return &MBB->getParent()->getRegInfo();
609 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
610 /// this instruction from their respective use lists. This requires that the
611 /// operands already be on their use lists.
612 void MachineInstr::RemoveRegOperandsFromUseLists() {
613 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
614 if (Operands[i].isReg())
615 Operands[i].RemoveRegOperandFromRegInfo();
619 /// AddRegOperandsToUseLists - Add all of the register operands in
620 /// this instruction from their respective use lists. This requires that the
621 /// operands not be on their use lists yet.
622 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
623 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
624 if (Operands[i].isReg())
625 Operands[i].AddRegOperandToRegInfo(&RegInfo);
630 /// addOperand - Add the specified operand to the instruction. If it is an
631 /// implicit operand, it is added to the end of the operand list. If it is
632 /// an explicit operand it is added at the end of the explicit operand list
633 /// (before the first implicit operand).
634 void MachineInstr::addOperand(const MachineOperand &Op) {
635 assert(MCID && "Cannot add operands before providing an instr descriptor");
636 bool isImpReg = Op.isReg() && Op.isImplicit();
637 MachineRegisterInfo *RegInfo = getRegInfo();
639 // If the Operands backing store is reallocated, all register operands must
640 // be removed and re-added to RegInfo. It is storing pointers to operands.
641 bool Reallocate = RegInfo &&
642 !Operands.empty() && Operands.size() == Operands.capacity();
644 // Find the insert location for the new operand. Implicit registers go at
645 // the end, everything goes before the implicit regs.
646 unsigned OpNo = Operands.size();
648 // Remove all the implicit operands from RegInfo if they need to be shifted.
649 // FIXME: Allow mixed explicit and implicit operands on inline asm.
650 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
651 // implicit-defs, but they must not be moved around. See the FIXME in
653 if (!isImpReg && !isInlineAsm()) {
654 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
657 Operands[OpNo].RemoveRegOperandFromRegInfo();
661 // OpNo now points as the desired insertion point. Unless this is a variadic
662 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
663 assert((isImpReg || MCID->isVariadic() || OpNo < MCID->getNumOperands()) &&
664 "Trying to add an operand to a machine instr that is already done!");
666 // All operands from OpNo have been removed from RegInfo. If the Operands
667 // backing store needs to be reallocated, we also need to remove any other
668 // register operands.
670 for (unsigned i = 0; i != OpNo; ++i)
671 if (Operands[i].isReg())
672 Operands[i].RemoveRegOperandFromRegInfo();
674 // Insert the new operand at OpNo.
675 Operands.insert(Operands.begin() + OpNo, Op);
676 Operands[OpNo].ParentMI = this;
678 // The Operands backing store has now been reallocated, so we can re-add the
679 // operands before OpNo.
681 for (unsigned i = 0; i != OpNo; ++i)
682 if (Operands[i].isReg())
683 Operands[i].AddRegOperandToRegInfo(RegInfo);
685 // When adding a register operand, tell RegInfo about it.
686 if (Operands[OpNo].isReg()) {
687 // Add the new operand to RegInfo, even when RegInfo is NULL.
688 // This will initialize the linked list pointers.
689 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
690 // If the register operand is flagged as early, mark the operand as such.
691 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
692 Operands[OpNo].setIsEarlyClobber(true);
695 // Re-add all the implicit ops.
697 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
698 assert(Operands[i].isReg() && "Should only be an implicit reg!");
699 Operands[i].AddRegOperandToRegInfo(RegInfo);
704 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
705 /// fewer operand than it started with.
707 void MachineInstr::RemoveOperand(unsigned OpNo) {
708 assert(OpNo < Operands.size() && "Invalid operand number");
710 // Special case removing the last one.
711 if (OpNo == Operands.size()-1) {
712 // If needed, remove from the reg def/use list.
713 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
714 Operands.back().RemoveRegOperandFromRegInfo();
720 // Otherwise, we are removing an interior operand. If we have reginfo to
721 // update, remove all operands that will be shifted down from their reg lists,
722 // move everything down, then re-add them.
723 MachineRegisterInfo *RegInfo = getRegInfo();
725 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
726 if (Operands[i].isReg())
727 Operands[i].RemoveRegOperandFromRegInfo();
731 Operands.erase(Operands.begin()+OpNo);
734 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
735 if (Operands[i].isReg())
736 Operands[i].AddRegOperandToRegInfo(RegInfo);
741 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
742 /// This function should be used only occasionally. The setMemRefs function
743 /// is the primary method for setting up a MachineInstr's MemRefs list.
744 void MachineInstr::addMemOperand(MachineFunction &MF,
745 MachineMemOperand *MO) {
746 mmo_iterator OldMemRefs = MemRefs;
747 uint16_t OldNumMemRefs = NumMemRefs;
749 uint16_t NewNum = NumMemRefs + 1;
750 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
752 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
753 NewMemRefs[NewNum - 1] = MO;
755 MemRefs = NewMemRefs;
759 bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
760 const MachineBasicBlock *MBB = getParent();
761 MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
762 while (MII != MBB->end() && MII->isInsideBundle()) {
763 if (MII->getDesc().getFlags() & Mask) {
764 if (Type == AnyInBundle)
767 if (Type == AllInBundle)
773 return Type == AllInBundle;
776 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
777 MICheckType Check) const {
778 // If opcodes or number of operands are not the same then the two
779 // instructions are obviously not identical.
780 if (Other->getOpcode() != getOpcode() ||
781 Other->getNumOperands() != getNumOperands())
785 // Both instructions are bundles, compare MIs inside the bundle.
786 MachineBasicBlock::const_instr_iterator I1 = *this;
787 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
788 MachineBasicBlock::const_instr_iterator I2 = *Other;
789 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
790 while (++I1 != E1 && I1->isInsideBundle()) {
792 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
797 // Check operands to make sure they match.
798 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
799 const MachineOperand &MO = getOperand(i);
800 const MachineOperand &OMO = Other->getOperand(i);
802 if (!MO.isIdenticalTo(OMO))
807 // Clients may or may not want to ignore defs when testing for equality.
808 // For example, machine CSE pass only cares about finding common
809 // subexpressions, so it's safe to ignore virtual register defs.
811 if (Check == IgnoreDefs)
813 else if (Check == IgnoreVRegDefs) {
814 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
815 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
816 if (MO.getReg() != OMO.getReg())
819 if (!MO.isIdenticalTo(OMO))
821 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
825 if (!MO.isIdenticalTo(OMO))
827 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
831 // If DebugLoc does not match then two dbg.values are not identical.
833 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
834 && getDebugLoc() != Other->getDebugLoc())
839 /// removeFromParent - This method unlinks 'this' from the containing basic
840 /// block, and returns it, but does not delete it.
841 MachineInstr *MachineInstr::removeFromParent() {
842 assert(getParent() && "Not embedded in a basic block!");
844 // If it's a bundle then remove the MIs inside the bundle as well.
846 MachineBasicBlock *MBB = getParent();
847 MachineBasicBlock::instr_iterator MII = *this; ++MII;
848 MachineBasicBlock::instr_iterator E = MBB->instr_end();
849 while (MII != E && MII->isInsideBundle()) {
850 MachineInstr *MI = &*MII;
855 getParent()->remove(this);
860 /// eraseFromParent - This method unlinks 'this' from the containing basic
861 /// block, and deletes it.
862 void MachineInstr::eraseFromParent() {
863 assert(getParent() && "Not embedded in a basic block!");
864 // If it's a bundle then remove the MIs inside the bundle as well.
866 MachineBasicBlock *MBB = getParent();
867 MachineBasicBlock::instr_iterator MII = *this; ++MII;
868 MachineBasicBlock::instr_iterator E = MBB->instr_end();
869 while (MII != E && MII->isInsideBundle()) {
870 MachineInstr *MI = &*MII;
875 // Erase the individual instruction, which may itself be inside a bundle.
876 getParent()->erase_instr(this);
880 /// getNumExplicitOperands - Returns the number of non-implicit operands.
882 unsigned MachineInstr::getNumExplicitOperands() const {
883 unsigned NumOperands = MCID->getNumOperands();
884 if (!MCID->isVariadic())
887 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
888 const MachineOperand &MO = getOperand(i);
889 if (!MO.isReg() || !MO.isImplicit())
895 /// isBundled - Return true if this instruction part of a bundle. This is true
896 /// if either itself or its following instruction is marked "InsideBundle".
897 bool MachineInstr::isBundled() const {
898 if (isInsideBundle())
900 MachineBasicBlock::const_instr_iterator nextMI = this;
902 return nextMI != Parent->instr_end() && nextMI->isInsideBundle();
905 bool MachineInstr::isStackAligningInlineAsm() const {
907 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
908 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
914 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
915 unsigned *GroupNo) const {
916 assert(isInlineAsm() && "Expected an inline asm instruction");
917 assert(OpIdx < getNumOperands() && "OpIdx out of range");
919 // Ignore queries about the initial operands.
920 if (OpIdx < InlineAsm::MIOp_FirstOperand)
925 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
927 const MachineOperand &FlagMO = getOperand(i);
928 // If we reach the implicit register operands, stop looking.
931 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
932 if (i + NumOps > OpIdx) {
942 const TargetRegisterClass*
943 MachineInstr::getRegClassConstraint(unsigned OpIdx,
944 const TargetInstrInfo *TII,
945 const TargetRegisterInfo *TRI) const {
946 assert(getParent() && "Can't have an MBB reference here!");
947 assert(getParent()->getParent() && "Can't have an MF reference here!");
948 const MachineFunction &MF = *getParent()->getParent();
950 // Most opcodes have fixed constraints in their MCInstrDesc.
952 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
954 if (!getOperand(OpIdx).isReg())
957 // For tied uses on inline asm, get the constraint from the def.
959 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
962 // Inline asm stores register class constraints in the flag word.
963 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
967 unsigned Flag = getOperand(FlagIdx).getImm();
969 if (InlineAsm::hasRegClassConstraint(Flag, RCID))
970 return TRI->getRegClass(RCID);
972 // Assume that all registers in a memory operand are pointers.
973 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
974 return TRI->getPointerRegClass(MF);
979 /// getBundleSize - Return the number of instructions inside the MI bundle.
980 unsigned MachineInstr::getBundleSize() const {
981 assert(isBundle() && "Expecting a bundle");
983 MachineBasicBlock::const_instr_iterator I = *this;
985 while ((++I)->isInsideBundle()) {
988 assert(Size > 1 && "Malformed bundle");
993 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
994 /// the specific register or -1 if it is not found. It further tightens
995 /// the search criteria to a use that kills the register if isKill is true.
996 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
997 const TargetRegisterInfo *TRI) const {
998 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
999 const MachineOperand &MO = getOperand(i);
1000 if (!MO.isReg() || !MO.isUse())
1002 unsigned MOReg = MO.getReg();
1007 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1008 TargetRegisterInfo::isPhysicalRegister(Reg) &&
1009 TRI->isSubRegister(MOReg, Reg)))
1010 if (!isKill || MO.isKill())
1016 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1017 /// indicating if this instruction reads or writes Reg. This also considers
1018 /// partial defines.
1019 std::pair<bool,bool>
1020 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1021 SmallVectorImpl<unsigned> *Ops) const {
1022 bool PartDef = false; // Partial redefine.
1023 bool FullDef = false; // Full define.
1026 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1027 const MachineOperand &MO = getOperand(i);
1028 if (!MO.isReg() || MO.getReg() != Reg)
1033 Use |= !MO.isUndef();
1034 else if (MO.getSubReg() && !MO.isUndef())
1035 // A partial <def,undef> doesn't count as reading the register.
1040 // A partial redefine uses Reg unless there is also a full define.
1041 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1044 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1045 /// the specified register or -1 if it is not found. If isDead is true, defs
1046 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1047 /// also checks if there is a def of a super-register.
1049 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1050 const TargetRegisterInfo *TRI) const {
1051 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1052 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1053 const MachineOperand &MO = getOperand(i);
1054 // Accept regmask operands when Overlap is set.
1055 // Ignore them when looking for a specific def operand (Overlap == false).
1056 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1058 if (!MO.isReg() || !MO.isDef())
1060 unsigned MOReg = MO.getReg();
1061 bool Found = (MOReg == Reg);
1062 if (!Found && TRI && isPhys &&
1063 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1065 Found = TRI->regsOverlap(MOReg, Reg);
1067 Found = TRI->isSubRegister(MOReg, Reg);
1069 if (Found && (!isDead || MO.isDead()))
1075 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1076 /// operand list that is used to represent the predicate. It returns -1 if
1078 int MachineInstr::findFirstPredOperandIdx() const {
1079 // Don't call MCID.findFirstPredOperandIdx() because this variant
1080 // is sometimes called on an instruction that's not yet complete, and
1081 // so the number of operands is less than the MCID indicates. In
1082 // particular, the PTX target does this.
1083 const MCInstrDesc &MCID = getDesc();
1084 if (MCID.isPredicable()) {
1085 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1086 if (MCID.OpInfo[i].isPredicate())
1093 /// isRegTiedToUseOperand - Given the index of a register def operand,
1094 /// check if the register def is tied to a source operand, due to either
1095 /// two-address elimination or inline assembly constraints. Returns the
1096 /// first tied use operand index by reference is UseOpIdx is not null.
1098 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
1099 if (isInlineAsm()) {
1100 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
1101 const MachineOperand &MO = getOperand(DefOpIdx);
1102 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
1104 // Determine the actual operand index that corresponds to this index.
1106 int FlagIdx = findInlineAsmFlagIdx(DefOpIdx, &DefNo);
1110 // Which part of the group is DefOpIdx?
1111 unsigned DefPart = DefOpIdx - (FlagIdx + 1);
1113 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
1115 const MachineOperand &FMO = getOperand(i);
1118 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
1121 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
1124 *UseOpIdx = (unsigned)i + 1 + DefPart;
1131 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
1132 const MCInstrDesc &MCID = getDesc();
1133 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
1134 const MachineOperand &MO = getOperand(i);
1135 if (MO.isReg() && MO.isUse() &&
1136 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
1138 *UseOpIdx = (unsigned)i;
1145 /// isRegTiedToDefOperand - Return true if the operand of the specified index
1146 /// is a register use and it is tied to an def operand. It also returns the def
1147 /// operand index by reference.
1149 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
1150 if (isInlineAsm()) {
1151 const MachineOperand &MO = getOperand(UseOpIdx);
1152 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
1155 // Find the flag operand corresponding to UseOpIdx
1156 int FlagIdx = findInlineAsmFlagIdx(UseOpIdx);
1160 const MachineOperand &UFMO = getOperand(FlagIdx);
1162 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1166 unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1167 // Remember to adjust the index. First operand is asm string, second is
1168 // the HasSideEffects and AlignStack bits, then there is a flag for each.
1170 const MachineOperand &FMO = getOperand(DefIdx);
1171 assert(FMO.isImm());
1172 // Skip over this def.
1173 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1176 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1182 const MCInstrDesc &MCID = getDesc();
1183 if (UseOpIdx >= MCID.getNumOperands())
1185 const MachineOperand &MO = getOperand(UseOpIdx);
1186 if (!MO.isReg() || !MO.isUse())
1188 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
1192 *DefOpIdx = (unsigned)DefIdx;
1196 /// clearKillInfo - Clears kill flags on all operands.
1198 void MachineInstr::clearKillInfo() {
1199 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1200 MachineOperand &MO = getOperand(i);
1201 if (MO.isReg() && MO.isUse())
1202 MO.setIsKill(false);
1206 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1208 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1209 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1210 const MachineOperand &MO = MI->getOperand(i);
1211 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1213 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1214 MachineOperand &MOp = getOperand(j);
1215 if (!MOp.isIdenticalTo(MO))
1226 /// copyPredicates - Copies predicate operand(s) from MI.
1227 void MachineInstr::copyPredicates(const MachineInstr *MI) {
1228 assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles");
1230 const MCInstrDesc &MCID = MI->getDesc();
1231 if (!MCID.isPredicable())
1233 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1234 if (MCID.OpInfo[i].isPredicate()) {
1235 // Predicated operands must be last operands.
1236 addOperand(MI->getOperand(i));
1241 void MachineInstr::substituteRegister(unsigned FromReg,
1244 const TargetRegisterInfo &RegInfo) {
1245 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1247 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1248 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1249 MachineOperand &MO = getOperand(i);
1250 if (!MO.isReg() || MO.getReg() != FromReg)
1252 MO.substPhysReg(ToReg, RegInfo);
1255 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1256 MachineOperand &MO = getOperand(i);
1257 if (!MO.isReg() || MO.getReg() != FromReg)
1259 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1264 /// isSafeToMove - Return true if it is safe to move this instruction. If
1265 /// SawStore is set to true, it means that there is a store (or call) between
1266 /// the instruction's location and its intended destination.
1267 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1269 bool &SawStore) const {
1270 // Ignore stuff that we obviously can't move.
1271 if (mayStore() || isCall()) {
1276 if (isLabel() || isDebugValue() ||
1277 isTerminator() || hasUnmodeledSideEffects())
1280 // See if this instruction does a load. If so, we have to guarantee that the
1281 // loaded value doesn't change between the load and the its intended
1282 // destination. The check for isInvariantLoad gives the targe the chance to
1283 // classify the load as always returning a constant, e.g. a constant pool
1285 if (mayLoad() && !isInvariantLoad(AA))
1286 // Otherwise, this is a real load. If there is a store between the load and
1287 // end of block, or if the load is volatile, we can't move it.
1288 return !SawStore && !hasVolatileMemoryRef();
1293 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1294 /// instruction which defined the specified register instead of copying it.
1295 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1297 unsigned DstReg) const {
1298 bool SawStore = false;
1299 if (!TII->isTriviallyReMaterializable(this, AA) ||
1300 !isSafeToMove(TII, AA, SawStore))
1302 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1303 const MachineOperand &MO = getOperand(i);
1306 // FIXME: For now, do not remat any instruction with register operands.
1307 // Later on, we can loosen the restriction is the register operands have
1308 // not been modified between the def and use. Note, this is different from
1309 // MachineSink because the code is no longer in two-address form (at least
1313 else if (!MO.isDead() && MO.getReg() != DstReg)
1319 /// hasVolatileMemoryRef - Return true if this instruction may have a
1320 /// volatile memory reference, or if the information describing the
1321 /// memory reference is not available. Return false if it is known to
1322 /// have no volatile memory references.
1323 bool MachineInstr::hasVolatileMemoryRef() const {
1324 // An instruction known never to access memory won't have a volatile access.
1328 !hasUnmodeledSideEffects())
1331 // Otherwise, if the instruction has no memory reference information,
1332 // conservatively assume it wasn't preserved.
1333 if (memoperands_empty())
1336 // Check the memory reference information for volatile references.
1337 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1338 if ((*I)->isVolatile())
1344 /// isInvariantLoad - Return true if this instruction is loading from a
1345 /// location whose value is invariant across the function. For example,
1346 /// loading a value from the constant pool or from the argument area
1347 /// of a function if it does not change. This should only return true of
1348 /// *all* loads the instruction does are invariant (if it does multiple loads).
1349 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1350 // If the instruction doesn't load at all, it isn't an invariant load.
1354 // If the instruction has lost its memoperands, conservatively assume that
1355 // it may not be an invariant load.
1356 if (memoperands_empty())
1359 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1361 for (mmo_iterator I = memoperands_begin(),
1362 E = memoperands_end(); I != E; ++I) {
1363 if ((*I)->isVolatile()) return false;
1364 if ((*I)->isStore()) return false;
1365 if ((*I)->isInvariant()) return true;
1367 if (const Value *V = (*I)->getValue()) {
1368 // A load from a constant PseudoSourceValue is invariant.
1369 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1370 if (PSV->isConstant(MFI))
1372 // If we have an AliasAnalysis, ask it whether the memory is constant.
1373 if (AA && AA->pointsToConstantMemory(
1374 AliasAnalysis::Location(V, (*I)->getSize(),
1375 (*I)->getTBAAInfo())))
1379 // Otherwise assume conservatively.
1383 // Everything checks out.
1387 /// isConstantValuePHI - If the specified instruction is a PHI that always
1388 /// merges together the same virtual register, return the register, otherwise
1390 unsigned MachineInstr::isConstantValuePHI() const {
1393 assert(getNumOperands() >= 3 &&
1394 "It's illegal to have a PHI without source operands");
1396 unsigned Reg = getOperand(1).getReg();
1397 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1398 if (getOperand(i).getReg() != Reg)
1403 bool MachineInstr::hasUnmodeledSideEffects() const {
1404 if (hasProperty(MCID::UnmodeledSideEffects))
1406 if (isInlineAsm()) {
1407 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1408 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1415 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1417 bool MachineInstr::allDefsAreDead() const {
1418 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1419 const MachineOperand &MO = getOperand(i);
1420 if (!MO.isReg() || MO.isUse())
1428 /// copyImplicitOps - Copy implicit register operands from specified
1429 /// instruction to this instruction.
1430 void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1431 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1433 const MachineOperand &MO = MI->getOperand(i);
1434 if (MO.isReg() && MO.isImplicit())
1439 void MachineInstr::dump() const {
1440 dbgs() << " " << *this;
1443 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1444 raw_ostream &CommentOS) {
1445 const LLVMContext &Ctx = MF->getFunction()->getContext();
1446 if (!DL.isUnknown()) { // Print source line info.
1447 DIScope Scope(DL.getScope(Ctx));
1448 // Omit the directory, because it's likely to be long and uninteresting.
1450 CommentOS << Scope.getFilename();
1452 CommentOS << "<unknown>";
1453 CommentOS << ':' << DL.getLine();
1454 if (DL.getCol() != 0)
1455 CommentOS << ':' << DL.getCol();
1456 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1457 if (!InlinedAtDL.isUnknown()) {
1458 CommentOS << " @[ ";
1459 printDebugLoc(InlinedAtDL, MF, CommentOS);
1465 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1466 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1467 const MachineFunction *MF = 0;
1468 const MachineRegisterInfo *MRI = 0;
1469 if (const MachineBasicBlock *MBB = getParent()) {
1470 MF = MBB->getParent();
1472 TM = &MF->getTarget();
1474 MRI = &MF->getRegInfo();
1477 // Save a list of virtual registers.
1478 SmallVector<unsigned, 8> VirtRegs;
1480 // Print explicitly defined operands on the left of an assignment syntax.
1481 unsigned StartOp = 0, e = getNumOperands();
1482 for (; StartOp < e && getOperand(StartOp).isReg() &&
1483 getOperand(StartOp).isDef() &&
1484 !getOperand(StartOp).isImplicit();
1486 if (StartOp != 0) OS << ", ";
1487 getOperand(StartOp).print(OS, TM);
1488 unsigned Reg = getOperand(StartOp).getReg();
1489 if (TargetRegisterInfo::isVirtualRegister(Reg))
1490 VirtRegs.push_back(Reg);
1496 // Print the opcode name.
1497 if (TM && TM->getInstrInfo())
1498 OS << TM->getInstrInfo()->getName(getOpcode());
1502 // Print the rest of the operands.
1503 bool OmittedAnyCallClobbers = false;
1504 bool FirstOp = true;
1505 unsigned AsmDescOp = ~0u;
1506 unsigned AsmOpCount = 0;
1508 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1509 // Print asm string.
1511 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1513 // Print HasSideEffects, IsAlignStack
1514 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1515 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1516 OS << " [sideeffect]";
1517 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1518 OS << " [alignstack]";
1520 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1525 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1526 const MachineOperand &MO = getOperand(i);
1528 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1529 VirtRegs.push_back(MO.getReg());
1531 // Omit call-clobbered registers which aren't used anywhere. This makes
1532 // call instructions much less noisy on targets where calls clobber lots
1533 // of registers. Don't rely on MO.isDead() because we may be called before
1534 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1535 if (MF && isCall() &&
1536 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1537 unsigned Reg = MO.getReg();
1538 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1539 const MachineRegisterInfo &MRI = MF->getRegInfo();
1540 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1541 bool HasAliasLive = false;
1542 for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
1543 AI.isValid(); ++AI) {
1544 unsigned AliasReg = *AI;
1545 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1546 HasAliasLive = true;
1550 if (!HasAliasLive) {
1551 OmittedAnyCallClobbers = true;
1558 if (FirstOp) FirstOp = false; else OS << ",";
1560 if (i < getDesc().NumOperands) {
1561 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1562 if (MCOI.isPredicate())
1564 if (MCOI.isOptionalDef())
1567 if (isDebugValue() && MO.isMetadata()) {
1568 // Pretty print DBG_VALUE instructions.
1569 const MDNode *MD = MO.getMetadata();
1570 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1571 OS << "!\"" << MDS->getString() << '\"';
1574 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1575 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1576 } else if (i == AsmDescOp && MO.isImm()) {
1577 // Pretty print the inline asm operand descriptor.
1578 OS << '$' << AsmOpCount++;
1579 unsigned Flag = MO.getImm();
1580 switch (InlineAsm::getKind(Flag)) {
1581 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1582 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1583 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1584 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1585 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1586 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1587 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1591 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1593 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1595 OS << ":RC" << RCID;
1598 unsigned TiedTo = 0;
1599 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1600 OS << " tiedto:$" << TiedTo;
1604 // Compute the index of the next operand descriptor.
1605 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1610 // Briefly indicate whether any call clobbers were omitted.
1611 if (OmittedAnyCallClobbers) {
1612 if (!FirstOp) OS << ",";
1616 bool HaveSemi = false;
1618 if (!HaveSemi) OS << ";"; HaveSemi = true;
1621 if (Flags & FrameSetup)
1625 if (!memoperands_empty()) {
1626 if (!HaveSemi) OS << ";"; HaveSemi = true;
1629 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1632 if (llvm::next(i) != e)
1637 // Print the regclass of any virtual registers encountered.
1638 if (MRI && !VirtRegs.empty()) {
1639 if (!HaveSemi) OS << ";"; HaveSemi = true;
1640 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1641 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1642 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1643 for (unsigned j = i+1; j != VirtRegs.size();) {
1644 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1648 if (VirtRegs[i] != VirtRegs[j])
1649 OS << "," << PrintReg(VirtRegs[j]);
1650 VirtRegs.erase(VirtRegs.begin()+j);
1655 // Print debug location information.
1656 if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1657 if (!HaveSemi) OS << ";"; HaveSemi = true;
1658 DIVariable DV(getOperand(e - 1).getMetadata());
1659 OS << " line no:" << DV.getLineNumber();
1660 if (MDNode *InlinedAt = DV.getInlinedAt()) {
1661 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1662 if (!InlinedAtDL.isUnknown()) {
1663 OS << " inlined @[ ";
1664 printDebugLoc(InlinedAtDL, MF, OS);
1668 } else if (!debugLoc.isUnknown() && MF) {
1669 if (!HaveSemi) OS << ";"; HaveSemi = true;
1671 printDebugLoc(debugLoc, MF, OS);
1677 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1678 const TargetRegisterInfo *RegInfo,
1679 bool AddIfNotFound) {
1680 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1681 bool hasAliases = isPhysReg &&
1682 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1684 SmallVector<unsigned,4> DeadOps;
1685 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1686 MachineOperand &MO = getOperand(i);
1687 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1689 unsigned Reg = MO.getReg();
1693 if (Reg == IncomingReg) {
1696 // The register is already marked kill.
1698 if (isPhysReg && isRegTiedToDefOperand(i))
1699 // Two-address uses of physregs must not be marked kill.
1704 } else if (hasAliases && MO.isKill() &&
1705 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1706 // A super-register kill already exists.
1707 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1709 if (RegInfo->isSubRegister(IncomingReg, Reg))
1710 DeadOps.push_back(i);
1714 // Trim unneeded kill operands.
1715 while (!DeadOps.empty()) {
1716 unsigned OpIdx = DeadOps.back();
1717 if (getOperand(OpIdx).isImplicit())
1718 RemoveOperand(OpIdx);
1720 getOperand(OpIdx).setIsKill(false);
1724 // If not found, this means an alias of one of the operands is killed. Add a
1725 // new implicit operand if required.
1726 if (!Found && AddIfNotFound) {
1727 addOperand(MachineOperand::CreateReg(IncomingReg,
1736 void MachineInstr::clearRegisterKills(unsigned Reg,
1737 const TargetRegisterInfo *RegInfo) {
1738 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1740 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1741 MachineOperand &MO = getOperand(i);
1742 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1744 unsigned OpReg = MO.getReg();
1745 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1746 MO.setIsKill(false);
1750 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1751 const TargetRegisterInfo *RegInfo,
1752 bool AddIfNotFound) {
1753 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1754 bool hasAliases = isPhysReg &&
1755 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1757 SmallVector<unsigned,4> DeadOps;
1758 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1759 MachineOperand &MO = getOperand(i);
1760 if (!MO.isReg() || !MO.isDef())
1762 unsigned Reg = MO.getReg();
1766 if (Reg == IncomingReg) {
1769 } else if (hasAliases && MO.isDead() &&
1770 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1771 // There exists a super-register that's marked dead.
1772 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1774 if (RegInfo->isSubRegister(IncomingReg, Reg))
1775 DeadOps.push_back(i);
1779 // Trim unneeded dead operands.
1780 while (!DeadOps.empty()) {
1781 unsigned OpIdx = DeadOps.back();
1782 if (getOperand(OpIdx).isImplicit())
1783 RemoveOperand(OpIdx);
1785 getOperand(OpIdx).setIsDead(false);
1789 // If not found, this means an alias of one of the operands is dead. Add a
1790 // new implicit operand if required.
1791 if (Found || !AddIfNotFound)
1794 addOperand(MachineOperand::CreateReg(IncomingReg,
1802 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1803 const TargetRegisterInfo *RegInfo) {
1804 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1805 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1809 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1810 const MachineOperand &MO = getOperand(i);
1811 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1812 MO.getSubReg() == 0)
1816 addOperand(MachineOperand::CreateReg(IncomingReg,
1821 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1822 const TargetRegisterInfo &TRI) {
1823 bool HasRegMask = false;
1824 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1825 MachineOperand &MO = getOperand(i);
1826 if (MO.isRegMask()) {
1830 if (!MO.isReg() || !MO.isDef()) continue;
1831 unsigned Reg = MO.getReg();
1832 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1834 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1836 if (TRI.regsOverlap(*I, Reg)) {
1840 // If there are no uses, including partial uses, the def is dead.
1841 if (Dead) MO.setIsDead();
1844 // This is a call with a register mask operand.
1845 // Mask clobbers are always dead, so add defs for the non-dead defines.
1847 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1849 addRegisterDefined(*I, &TRI);
1853 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1854 // Build up a buffer of hash code components.
1856 // FIXME: This is a total hack. We should have a hash_value overload for
1857 // MachineOperand, but currently that doesn't work because there are many
1858 // different ideas of "equality" and thus different sets of information that
1859 // contribute to the hash code. This one happens to want to take a specific
1860 // subset. And it's still not clear that this routine uses the *correct*
1861 // subset of information when computing the hash code. The goal is to use the
1862 // same inputs for the hash code here that MachineInstr::isIdenticalTo uses to
1863 // test for equality when passed the 'IgnoreVRegDefs' filter flag. It would
1864 // be very useful to factor the selection of relevant inputs out of the two
1865 // functions and into a common routine, but it's not clear how that can be
1867 SmallVector<size_t, 8> HashComponents;
1868 HashComponents.reserve(MI->getNumOperands() + 1);
1869 HashComponents.push_back(MI->getOpcode());
1870 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1871 const MachineOperand &MO = MI->getOperand(i);
1872 switch (MO.getType()) {
1874 case MachineOperand::MO_Register:
1875 if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1876 continue; // Skip virtual register defs.
1877 HashComponents.push_back(hash_combine(MO.getType(), MO.getReg()));
1879 case MachineOperand::MO_Immediate:
1880 HashComponents.push_back(hash_combine(MO.getType(), MO.getImm()));
1882 case MachineOperand::MO_FrameIndex:
1883 case MachineOperand::MO_ConstantPoolIndex:
1884 case MachineOperand::MO_JumpTableIndex:
1885 HashComponents.push_back(hash_combine(MO.getType(), MO.getIndex()));
1887 case MachineOperand::MO_MachineBasicBlock:
1888 HashComponents.push_back(hash_combine(MO.getType(), MO.getMBB()));
1890 case MachineOperand::MO_GlobalAddress:
1891 HashComponents.push_back(hash_combine(MO.getType(), MO.getGlobal()));
1893 case MachineOperand::MO_BlockAddress:
1894 HashComponents.push_back(hash_combine(MO.getType(),
1895 MO.getBlockAddress()));
1897 case MachineOperand::MO_MCSymbol:
1898 HashComponents.push_back(hash_combine(MO.getType(), MO.getMCSymbol()));
1902 return hash_combine_range(HashComponents.begin(), HashComponents.end());
1905 void MachineInstr::emitError(StringRef Msg) const {
1906 // Find the source location cookie.
1907 unsigned LocCookie = 0;
1908 const MDNode *LocMD = 0;
1909 for (unsigned i = getNumOperands(); i != 0; --i) {
1910 if (getOperand(i-1).isMetadata() &&
1911 (LocMD = getOperand(i-1).getMetadata()) &&
1912 LocMD->getNumOperands() != 0) {
1913 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1914 LocCookie = CI->getZExtValue();
1920 if (const MachineBasicBlock *MBB = getParent())
1921 if (const MachineFunction *MF = MBB->getParent())
1922 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1923 report_fatal_error(Msg);