1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Function.h"
17 #include "llvm/InlineAsm.h"
18 #include "llvm/LLVMContext.h"
19 #include "llvm/Metadata.h"
20 #include "llvm/Module.h"
21 #include "llvm/Type.h"
22 #include "llvm/Value.h"
23 #include "llvm/Assembly/Writer.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCSymbol.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Analysis/AliasAnalysis.h"
36 #include "llvm/Analysis/DebugInfo.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/LeakDetector.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/FoldingSet.h"
45 //===----------------------------------------------------------------------===//
46 // MachineOperand Implementation
47 //===----------------------------------------------------------------------===//
49 /// AddRegOperandToRegInfo - Add this register operand to the specified
50 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
51 /// explicitly nulled out.
52 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
53 assert(isReg() && "Can only add reg operand to use lists");
55 // If the reginfo pointer is null, just explicitly null out or next/prev
56 // pointers, to ensure they are not garbage.
58 Contents.Reg.Prev = 0;
59 Contents.Reg.Next = 0;
63 // Otherwise, add this operand to the head of the registers use/def list.
64 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
66 // For SSA values, we prefer to keep the definition at the start of the list.
67 // we do this by skipping over the definition if it is at the head of the
69 if (*Head && (*Head)->isDef())
70 Head = &(*Head)->Contents.Reg.Next;
72 Contents.Reg.Next = *Head;
73 if (Contents.Reg.Next) {
74 assert(getReg() == Contents.Reg.Next->getReg() &&
75 "Different regs on the same list!");
76 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
79 Contents.Reg.Prev = Head;
83 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
84 /// MachineRegisterInfo it is linked with.
85 void MachineOperand::RemoveRegOperandFromRegInfo() {
86 assert(isOnRegUseList() && "Reg operand is not on a use list");
87 // Unlink this from the doubly linked list of operands.
88 MachineOperand *NextOp = Contents.Reg.Next;
89 *Contents.Reg.Prev = NextOp;
91 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
92 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
94 Contents.Reg.Prev = 0;
95 Contents.Reg.Next = 0;
98 void MachineOperand::setReg(unsigned Reg) {
99 if (getReg() == Reg) return; // No change.
101 // Otherwise, we have to change the register. If this operand is embedded
102 // into a machine function, we need to update the old and new register's
104 if (MachineInstr *MI = getParent())
105 if (MachineBasicBlock *MBB = MI->getParent())
106 if (MachineFunction *MF = MBB->getParent()) {
107 RemoveRegOperandFromRegInfo();
108 SmallContents.RegNo = Reg;
109 AddRegOperandToRegInfo(&MF->getRegInfo());
113 // Otherwise, just change the register, no problem. :)
114 SmallContents.RegNo = Reg;
117 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
118 const TargetRegisterInfo &TRI) {
119 assert(TargetRegisterInfo::isVirtualRegister(Reg));
120 if (SubIdx && getSubReg())
121 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
127 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
128 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
130 Reg = TRI.getSubReg(Reg, getSubReg());
131 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
132 // That won't happen in legal code.
138 /// ChangeToImmediate - Replace this operand with a new immediate operand of
139 /// the specified value. If an operand is known to be an immediate already,
140 /// the setImm method should be used.
141 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
142 // If this operand is currently a register operand, and if this is in a
143 // function, deregister the operand from the register's use/def list.
144 if (isReg() && getParent() && getParent()->getParent() &&
145 getParent()->getParent()->getParent())
146 RemoveRegOperandFromRegInfo();
148 OpKind = MO_Immediate;
149 Contents.ImmVal = ImmVal;
152 /// ChangeToRegister - Replace this operand with a new register operand of
153 /// the specified value. If an operand is known to be an register already,
154 /// the setReg method should be used.
155 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
156 bool isKill, bool isDead, bool isUndef,
158 // If this operand is already a register operand, use setReg to update the
159 // register's use/def lists.
161 assert(!isEarlyClobber());
164 // Otherwise, change this to a register and set the reg#.
165 OpKind = MO_Register;
166 SmallContents.RegNo = Reg;
168 // If this operand is embedded in a function, add the operand to the
169 // register's use/def list.
170 if (MachineInstr *MI = getParent())
171 if (MachineBasicBlock *MBB = MI->getParent())
172 if (MachineFunction *MF = MBB->getParent())
173 AddRegOperandToRegInfo(&MF->getRegInfo());
181 IsEarlyClobber = false;
186 /// isIdenticalTo - Return true if this operand is identical to the specified
188 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
189 if (getType() != Other.getType() ||
190 getTargetFlags() != Other.getTargetFlags())
194 default: llvm_unreachable("Unrecognized operand type");
195 case MachineOperand::MO_Register:
196 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
197 getSubReg() == Other.getSubReg();
198 case MachineOperand::MO_Immediate:
199 return getImm() == Other.getImm();
200 case MachineOperand::MO_CImmediate:
201 return getCImm() == Other.getCImm();
202 case MachineOperand::MO_FPImmediate:
203 return getFPImm() == Other.getFPImm();
204 case MachineOperand::MO_MachineBasicBlock:
205 return getMBB() == Other.getMBB();
206 case MachineOperand::MO_FrameIndex:
207 return getIndex() == Other.getIndex();
208 case MachineOperand::MO_ConstantPoolIndex:
209 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
210 case MachineOperand::MO_JumpTableIndex:
211 return getIndex() == Other.getIndex();
212 case MachineOperand::MO_GlobalAddress:
213 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
214 case MachineOperand::MO_ExternalSymbol:
215 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
216 getOffset() == Other.getOffset();
217 case MachineOperand::MO_BlockAddress:
218 return getBlockAddress() == Other.getBlockAddress();
219 case MachineOperand::MO_MCSymbol:
220 return getMCSymbol() == Other.getMCSymbol();
221 case MachineOperand::MO_Metadata:
222 return getMetadata() == Other.getMetadata();
226 /// print - Print the specified machine operand.
228 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
229 // If the instruction is embedded into a basic block, we can find the
230 // target info for the instruction.
232 if (const MachineInstr *MI = getParent())
233 if (const MachineBasicBlock *MBB = MI->getParent())
234 if (const MachineFunction *MF = MBB->getParent())
235 TM = &MF->getTarget();
236 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
239 case MachineOperand::MO_Register:
240 OS << PrintReg(getReg(), TRI, getSubReg());
242 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
245 bool NeedComma = false;
247 if (NeedComma) OS << ',';
248 if (isEarlyClobber())
249 OS << "earlyclobber,";
254 } else if (isImplicit()) {
259 if (isKill() || isDead() || isUndef()) {
260 if (NeedComma) OS << ',';
261 if (isKill()) OS << "kill";
262 if (isDead()) OS << "dead";
264 if (isKill() || isDead())
272 case MachineOperand::MO_Immediate:
275 case MachineOperand::MO_CImmediate:
276 getCImm()->getValue().print(OS, false);
278 case MachineOperand::MO_FPImmediate:
279 if (getFPImm()->getType()->isFloatTy())
280 OS << getFPImm()->getValueAPF().convertToFloat();
282 OS << getFPImm()->getValueAPF().convertToDouble();
284 case MachineOperand::MO_MachineBasicBlock:
285 OS << "<BB#" << getMBB()->getNumber() << ">";
287 case MachineOperand::MO_FrameIndex:
288 OS << "<fi#" << getIndex() << '>';
290 case MachineOperand::MO_ConstantPoolIndex:
291 OS << "<cp#" << getIndex();
292 if (getOffset()) OS << "+" << getOffset();
295 case MachineOperand::MO_JumpTableIndex:
296 OS << "<jt#" << getIndex() << '>';
298 case MachineOperand::MO_GlobalAddress:
300 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
301 if (getOffset()) OS << "+" << getOffset();
304 case MachineOperand::MO_ExternalSymbol:
305 OS << "<es:" << getSymbolName();
306 if (getOffset()) OS << "+" << getOffset();
309 case MachineOperand::MO_BlockAddress:
311 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
314 case MachineOperand::MO_Metadata:
316 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
319 case MachineOperand::MO_MCSymbol:
320 OS << "<MCSym=" << *getMCSymbol() << '>';
323 llvm_unreachable("Unrecognized operand type");
326 if (unsigned TF = getTargetFlags())
327 OS << "[TF=" << TF << ']';
330 //===----------------------------------------------------------------------===//
331 // MachineMemOperand Implementation
332 //===----------------------------------------------------------------------===//
334 /// getAddrSpace - Return the LLVM IR address space number that this pointer
336 unsigned MachinePointerInfo::getAddrSpace() const {
337 if (V == 0) return 0;
338 return cast<PointerType>(V->getType())->getAddressSpace();
341 /// getConstantPool - Return a MachinePointerInfo record that refers to the
343 MachinePointerInfo MachinePointerInfo::getConstantPool() {
344 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
347 /// getFixedStack - Return a MachinePointerInfo record that refers to the
348 /// the specified FrameIndex.
349 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
350 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
353 MachinePointerInfo MachinePointerInfo::getJumpTable() {
354 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
357 MachinePointerInfo MachinePointerInfo::getGOT() {
358 return MachinePointerInfo(PseudoSourceValue::getGOT());
361 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
362 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
365 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
366 uint64_t s, unsigned int a,
367 const MDNode *TBAAInfo)
368 : PtrInfo(ptrinfo), Size(s),
369 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
371 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
372 "invalid pointer value");
373 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
374 assert((isLoad() || isStore()) && "Not a load/store!");
377 /// Profile - Gather unique data for the object.
379 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
380 ID.AddInteger(getOffset());
382 ID.AddPointer(getValue());
383 ID.AddInteger(Flags);
386 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
387 // The Value and Offset may differ due to CSE. But the flags and size
388 // should be the same.
389 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
390 assert(MMO->getSize() == getSize() && "Size mismatch!");
392 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
393 // Update the alignment value.
394 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
395 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
396 // Also update the base and offset, because the new alignment may
397 // not be applicable with the old ones.
398 PtrInfo = MMO->PtrInfo;
402 /// getAlignment - Return the minimum known alignment in bytes of the
403 /// actual memory reference.
404 uint64_t MachineMemOperand::getAlignment() const {
405 return MinAlign(getBaseAlignment(), getOffset());
408 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
409 assert((MMO.isLoad() || MMO.isStore()) &&
410 "SV has to be a load, store or both.");
412 if (MMO.isVolatile())
421 // Print the address information.
426 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
428 // If the alignment of the memory reference itself differs from the alignment
429 // of the base pointer, print the base alignment explicitly, next to the base
431 if (MMO.getBaseAlignment() != MMO.getAlignment())
432 OS << "(align=" << MMO.getBaseAlignment() << ")";
434 if (MMO.getOffset() != 0)
435 OS << "+" << MMO.getOffset();
438 // Print the alignment of the reference.
439 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
440 MMO.getBaseAlignment() != MMO.getSize())
441 OS << "(align=" << MMO.getAlignment() << ")";
444 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
446 if (TBAAInfo->getNumOperands() > 0)
447 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
453 // Print nontemporal info.
454 if (MMO.isNonTemporal())
455 OS << "(nontemporal)";
460 //===----------------------------------------------------------------------===//
461 // MachineInstr Implementation
462 //===----------------------------------------------------------------------===//
464 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
465 /// MCID NULL and no operands.
466 MachineInstr::MachineInstr()
467 : MCID(0), Flags(0), AsmPrinterFlags(0),
468 MemRefs(0), MemRefsEnd(0),
470 // Make sure that we get added to a machine basicblock
471 LeakDetector::addGarbageObject(this);
474 void MachineInstr::addImplicitDefUseOperands() {
475 if (MCID->ImplicitDefs)
476 for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs)
477 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
478 if (MCID->ImplicitUses)
479 for (const unsigned *ImpUses = MCID->ImplicitUses; *ImpUses; ++ImpUses)
480 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
483 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
484 /// implicit operands. It reserves space for the number of operands specified by
486 MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
487 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
488 MemRefs(0), MemRefsEnd(0), Parent(0) {
489 unsigned NumImplicitOps = 0;
491 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
492 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
494 addImplicitDefUseOperands();
495 // Make sure that we get added to a machine basicblock
496 LeakDetector::addGarbageObject(this);
499 /// MachineInstr ctor - As above, but with a DebugLoc.
500 MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
502 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
503 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
504 unsigned NumImplicitOps = 0;
506 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
507 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
509 addImplicitDefUseOperands();
510 // Make sure that we get added to a machine basicblock
511 LeakDetector::addGarbageObject(this);
514 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
515 /// that the MachineInstr is created and added to the end of the specified
517 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
518 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
519 MemRefs(0), MemRefsEnd(0), Parent(0) {
520 assert(MBB && "Cannot use inserting ctor with null basic block!");
521 unsigned NumImplicitOps =
522 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
523 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
524 addImplicitDefUseOperands();
525 // Make sure that we get added to a machine basicblock
526 LeakDetector::addGarbageObject(this);
527 MBB->push_back(this); // Add instruction to end of basic block!
530 /// MachineInstr ctor - As above, but with a DebugLoc.
532 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
533 const MCInstrDesc &tid)
534 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
535 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
536 assert(MBB && "Cannot use inserting ctor with null basic block!");
537 unsigned NumImplicitOps =
538 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
539 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
540 addImplicitDefUseOperands();
541 // Make sure that we get added to a machine basicblock
542 LeakDetector::addGarbageObject(this);
543 MBB->push_back(this); // Add instruction to end of basic block!
546 /// MachineInstr ctor - Copies MachineInstr arg exactly
548 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
549 : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
550 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
551 Parent(0), debugLoc(MI.getDebugLoc()) {
552 Operands.reserve(MI.getNumOperands());
555 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
556 addOperand(MI.getOperand(i));
558 // Copy all the flags.
561 // Set parent to null.
564 LeakDetector::addGarbageObject(this);
567 MachineInstr::~MachineInstr() {
568 LeakDetector::removeGarbageObject(this);
570 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
571 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
572 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
573 "Reg operand def/use list corrupted");
578 /// getRegInfo - If this instruction is embedded into a MachineFunction,
579 /// return the MachineRegisterInfo object for the current function, otherwise
581 MachineRegisterInfo *MachineInstr::getRegInfo() {
582 if (MachineBasicBlock *MBB = getParent())
583 return &MBB->getParent()->getRegInfo();
587 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
588 /// this instruction from their respective use lists. This requires that the
589 /// operands already be on their use lists.
590 void MachineInstr::RemoveRegOperandsFromUseLists() {
591 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
592 if (Operands[i].isReg())
593 Operands[i].RemoveRegOperandFromRegInfo();
597 /// AddRegOperandsToUseLists - Add all of the register operands in
598 /// this instruction from their respective use lists. This requires that the
599 /// operands not be on their use lists yet.
600 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
601 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
602 if (Operands[i].isReg())
603 Operands[i].AddRegOperandToRegInfo(&RegInfo);
608 /// addOperand - Add the specified operand to the instruction. If it is an
609 /// implicit operand, it is added to the end of the operand list. If it is
610 /// an explicit operand it is added at the end of the explicit operand list
611 /// (before the first implicit operand).
612 void MachineInstr::addOperand(const MachineOperand &Op) {
613 assert(MCID && "Cannot add operands before providing an instr descriptor");
614 bool isImpReg = Op.isReg() && Op.isImplicit();
615 MachineRegisterInfo *RegInfo = getRegInfo();
617 // If the Operands backing store is reallocated, all register operands must
618 // be removed and re-added to RegInfo. It is storing pointers to operands.
619 bool Reallocate = RegInfo &&
620 !Operands.empty() && Operands.size() == Operands.capacity();
622 // Find the insert location for the new operand. Implicit registers go at
623 // the end, everything goes before the implicit regs.
624 unsigned OpNo = Operands.size();
626 // Remove all the implicit operands from RegInfo if they need to be shifted.
627 // FIXME: Allow mixed explicit and implicit operands on inline asm.
628 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
629 // implicit-defs, but they must not be moved around. See the FIXME in
631 if (!isImpReg && !isInlineAsm()) {
632 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
635 Operands[OpNo].RemoveRegOperandFromRegInfo();
639 // OpNo now points as the desired insertion point. Unless this is a variadic
640 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
641 assert((isImpReg || MCID->isVariadic() || OpNo < MCID->getNumOperands()) &&
642 "Trying to add an operand to a machine instr that is already done!");
644 // All operands from OpNo have been removed from RegInfo. If the Operands
645 // backing store needs to be reallocated, we also need to remove any other
646 // register operands.
648 for (unsigned i = 0; i != OpNo; ++i)
649 if (Operands[i].isReg())
650 Operands[i].RemoveRegOperandFromRegInfo();
652 // Insert the new operand at OpNo.
653 Operands.insert(Operands.begin() + OpNo, Op);
654 Operands[OpNo].ParentMI = this;
656 // The Operands backing store has now been reallocated, so we can re-add the
657 // operands before OpNo.
659 for (unsigned i = 0; i != OpNo; ++i)
660 if (Operands[i].isReg())
661 Operands[i].AddRegOperandToRegInfo(RegInfo);
663 // When adding a register operand, tell RegInfo about it.
664 if (Operands[OpNo].isReg()) {
665 // Add the new operand to RegInfo, even when RegInfo is NULL.
666 // This will initialize the linked list pointers.
667 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
668 // If the register operand is flagged as early, mark the operand as such.
669 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
670 Operands[OpNo].setIsEarlyClobber(true);
673 // Re-add all the implicit ops.
675 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
676 assert(Operands[i].isReg() && "Should only be an implicit reg!");
677 Operands[i].AddRegOperandToRegInfo(RegInfo);
682 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
683 /// fewer operand than it started with.
685 void MachineInstr::RemoveOperand(unsigned OpNo) {
686 assert(OpNo < Operands.size() && "Invalid operand number");
688 // Special case removing the last one.
689 if (OpNo == Operands.size()-1) {
690 // If needed, remove from the reg def/use list.
691 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
692 Operands.back().RemoveRegOperandFromRegInfo();
698 // Otherwise, we are removing an interior operand. If we have reginfo to
699 // update, remove all operands that will be shifted down from their reg lists,
700 // move everything down, then re-add them.
701 MachineRegisterInfo *RegInfo = getRegInfo();
703 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
704 if (Operands[i].isReg())
705 Operands[i].RemoveRegOperandFromRegInfo();
709 Operands.erase(Operands.begin()+OpNo);
712 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
713 if (Operands[i].isReg())
714 Operands[i].AddRegOperandToRegInfo(RegInfo);
719 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
720 /// This function should be used only occasionally. The setMemRefs function
721 /// is the primary method for setting up a MachineInstr's MemRefs list.
722 void MachineInstr::addMemOperand(MachineFunction &MF,
723 MachineMemOperand *MO) {
724 mmo_iterator OldMemRefs = MemRefs;
725 mmo_iterator OldMemRefsEnd = MemRefsEnd;
727 size_t NewNum = (MemRefsEnd - MemRefs) + 1;
728 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
729 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
731 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
732 NewMemRefs[NewNum - 1] = MO;
734 MemRefs = NewMemRefs;
735 MemRefsEnd = NewMemRefsEnd;
738 bool MachineInstr::hasProperty(unsigned short MCFlag) const {
739 if (getOpcode() != TargetOpcode::BUNDLE)
740 return getDesc().getFlags() & (1 << MCFlag);
742 const MachineBasicBlock *MBB = getParent();
743 MachineBasicBlock::const_insn_iterator MII = *this; ++MII;
744 while (MII != MBB->end() && MII->isInsideBundle()) {
745 if (MII->getDesc().getFlags() & (1 << MCFlag))
752 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
753 MICheckType Check) const {
754 // If opcodes or number of operands are not the same then the two
755 // instructions are obviously not identical.
756 if (Other->getOpcode() != getOpcode() ||
757 Other->getNumOperands() != getNumOperands())
760 // Check operands to make sure they match.
761 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
762 const MachineOperand &MO = getOperand(i);
763 const MachineOperand &OMO = Other->getOperand(i);
765 if (!MO.isIdenticalTo(OMO))
770 // Clients may or may not want to ignore defs when testing for equality.
771 // For example, machine CSE pass only cares about finding common
772 // subexpressions, so it's safe to ignore virtual register defs.
774 if (Check == IgnoreDefs)
776 else if (Check == IgnoreVRegDefs) {
777 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
778 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
779 if (MO.getReg() != OMO.getReg())
782 if (!MO.isIdenticalTo(OMO))
784 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
788 if (!MO.isIdenticalTo(OMO))
790 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
794 // If DebugLoc does not match then two dbg.values are not identical.
796 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
797 && getDebugLoc() != Other->getDebugLoc())
802 /// removeFromParent - This method unlinks 'this' from the containing basic
803 /// block, and returns it, but does not delete it.
804 MachineInstr *MachineInstr::removeFromParent() {
805 assert(getParent() && "Not embedded in a basic block!");
807 // If it's a bundle then remove the MIs inside the bundle as well.
808 if (getOpcode() == TargetOpcode::BUNDLE) {
809 MachineBasicBlock *MBB = getParent();
810 MachineBasicBlock::insn_iterator MII = *this; ++MII;
811 while (MII != MBB->end() && MII->isInsideBundle()) {
812 MachineInstr *MI = &*MII;
817 getParent()->remove(this);
822 /// eraseFromParent - This method unlinks 'this' from the containing basic
823 /// block, and deletes it.
824 void MachineInstr::eraseFromParent() {
825 assert(getParent() && "Not embedded in a basic block!");
826 // If it's a bundle then remove the MIs inside the bundle as well.
827 if (getOpcode() == TargetOpcode::BUNDLE) {
828 MachineBasicBlock *MBB = getParent();
829 MachineBasicBlock::insn_iterator MII = *this; ++MII;
830 while (MII != MBB->end() && MII->isInsideBundle()) {
831 MachineInstr *MI = &*MII;
836 getParent()->erase(this);
840 /// getNumExplicitOperands - Returns the number of non-implicit operands.
842 unsigned MachineInstr::getNumExplicitOperands() const {
843 unsigned NumOperands = MCID->getNumOperands();
844 if (!MCID->isVariadic())
847 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
848 const MachineOperand &MO = getOperand(i);
849 if (!MO.isReg() || !MO.isImplicit())
855 bool MachineInstr::isStackAligningInlineAsm() const {
857 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
858 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
864 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
865 unsigned *GroupNo) const {
866 assert(isInlineAsm() && "Expected an inline asm instruction");
867 assert(OpIdx < getNumOperands() && "OpIdx out of range");
869 // Ignore queries about the initial operands.
870 if (OpIdx < InlineAsm::MIOp_FirstOperand)
875 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
877 const MachineOperand &FlagMO = getOperand(i);
878 // If we reach the implicit register operands, stop looking.
881 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
882 if (i + NumOps > OpIdx) {
892 const TargetRegisterClass*
893 MachineInstr::getRegClassConstraint(unsigned OpIdx,
894 const TargetInstrInfo *TII,
895 const TargetRegisterInfo *TRI) const {
896 // Most opcodes have fixed constraints in their MCInstrDesc.
898 return TII->getRegClass(getDesc(), OpIdx, TRI);
900 if (!getOperand(OpIdx).isReg())
903 // For tied uses on inline asm, get the constraint from the def.
905 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
908 // Inline asm stores register class constraints in the flag word.
909 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
913 unsigned Flag = getOperand(FlagIdx).getImm();
915 if (InlineAsm::hasRegClassConstraint(Flag, RCID))
916 return TRI->getRegClass(RCID);
918 // Assume that all registers in a memory operand are pointers.
919 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
920 return TRI->getPointerRegClass();
925 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
926 /// the specific register or -1 if it is not found. It further tightens
927 /// the search criteria to a use that kills the register if isKill is true.
928 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
929 const TargetRegisterInfo *TRI) const {
930 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
931 const MachineOperand &MO = getOperand(i);
932 if (!MO.isReg() || !MO.isUse())
934 unsigned MOReg = MO.getReg();
939 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
940 TargetRegisterInfo::isPhysicalRegister(Reg) &&
941 TRI->isSubRegister(MOReg, Reg)))
942 if (!isKill || MO.isKill())
948 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
949 /// indicating if this instruction reads or writes Reg. This also considers
952 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
953 SmallVectorImpl<unsigned> *Ops) const {
954 bool PartDef = false; // Partial redefine.
955 bool FullDef = false; // Full define.
958 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
959 const MachineOperand &MO = getOperand(i);
960 if (!MO.isReg() || MO.getReg() != Reg)
965 Use |= !MO.isUndef();
966 else if (MO.getSubReg() && !MO.isUndef())
967 // A partial <def,undef> doesn't count as reading the register.
972 // A partial redefine uses Reg unless there is also a full define.
973 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
976 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
977 /// the specified register or -1 if it is not found. If isDead is true, defs
978 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
979 /// also checks if there is a def of a super-register.
981 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
982 const TargetRegisterInfo *TRI) const {
983 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
984 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
985 const MachineOperand &MO = getOperand(i);
986 if (!MO.isReg() || !MO.isDef())
988 unsigned MOReg = MO.getReg();
989 bool Found = (MOReg == Reg);
990 if (!Found && TRI && isPhys &&
991 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
993 Found = TRI->regsOverlap(MOReg, Reg);
995 Found = TRI->isSubRegister(MOReg, Reg);
997 if (Found && (!isDead || MO.isDead()))
1003 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1004 /// operand list that is used to represent the predicate. It returns -1 if
1006 int MachineInstr::findFirstPredOperandIdx() const {
1007 // Don't call MCID.findFirstPredOperandIdx() because this variant
1008 // is sometimes called on an instruction that's not yet complete, and
1009 // so the number of operands is less than the MCID indicates. In
1010 // particular, the PTX target does this.
1011 const MCInstrDesc &MCID = getDesc();
1012 if (MCID.isPredicable()) {
1013 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1014 if (MCID.OpInfo[i].isPredicate())
1021 /// isRegTiedToUseOperand - Given the index of a register def operand,
1022 /// check if the register def is tied to a source operand, due to either
1023 /// two-address elimination or inline assembly constraints. Returns the
1024 /// first tied use operand index by reference is UseOpIdx is not null.
1026 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
1027 if (isInlineAsm()) {
1028 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
1029 const MachineOperand &MO = getOperand(DefOpIdx);
1030 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
1032 // Determine the actual operand index that corresponds to this index.
1034 int FlagIdx = findInlineAsmFlagIdx(DefOpIdx, &DefNo);
1038 // Which part of the group is DefOpIdx?
1039 unsigned DefPart = DefOpIdx - (FlagIdx + 1);
1041 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
1043 const MachineOperand &FMO = getOperand(i);
1046 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
1049 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
1052 *UseOpIdx = (unsigned)i + 1 + DefPart;
1059 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
1060 const MCInstrDesc &MCID = getDesc();
1061 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
1062 const MachineOperand &MO = getOperand(i);
1063 if (MO.isReg() && MO.isUse() &&
1064 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
1066 *UseOpIdx = (unsigned)i;
1073 /// isRegTiedToDefOperand - Return true if the operand of the specified index
1074 /// is a register use and it is tied to an def operand. It also returns the def
1075 /// operand index by reference.
1077 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
1078 if (isInlineAsm()) {
1079 const MachineOperand &MO = getOperand(UseOpIdx);
1080 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
1083 // Find the flag operand corresponding to UseOpIdx
1084 int FlagIdx = findInlineAsmFlagIdx(UseOpIdx);
1088 const MachineOperand &UFMO = getOperand(FlagIdx);
1090 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1094 unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1095 // Remember to adjust the index. First operand is asm string, second is
1096 // the HasSideEffects and AlignStack bits, then there is a flag for each.
1098 const MachineOperand &FMO = getOperand(DefIdx);
1099 assert(FMO.isImm());
1100 // Skip over this def.
1101 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1104 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1110 const MCInstrDesc &MCID = getDesc();
1111 if (UseOpIdx >= MCID.getNumOperands())
1113 const MachineOperand &MO = getOperand(UseOpIdx);
1114 if (!MO.isReg() || !MO.isUse())
1116 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
1120 *DefOpIdx = (unsigned)DefIdx;
1124 /// clearKillInfo - Clears kill flags on all operands.
1126 void MachineInstr::clearKillInfo() {
1127 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1128 MachineOperand &MO = getOperand(i);
1129 if (MO.isReg() && MO.isUse())
1130 MO.setIsKill(false);
1134 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1136 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1137 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1138 const MachineOperand &MO = MI->getOperand(i);
1139 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1141 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1142 MachineOperand &MOp = getOperand(j);
1143 if (!MOp.isIdenticalTo(MO))
1154 /// copyPredicates - Copies predicate operand(s) from MI.
1155 void MachineInstr::copyPredicates(const MachineInstr *MI) {
1156 const MCInstrDesc &MCID = MI->getDesc();
1157 if (!MCID.isPredicable())
1159 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1160 if (MCID.OpInfo[i].isPredicate()) {
1161 // Predicated operands must be last operands.
1162 addOperand(MI->getOperand(i));
1167 void MachineInstr::substituteRegister(unsigned FromReg,
1170 const TargetRegisterInfo &RegInfo) {
1171 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1173 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1174 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1175 MachineOperand &MO = getOperand(i);
1176 if (!MO.isReg() || MO.getReg() != FromReg)
1178 MO.substPhysReg(ToReg, RegInfo);
1181 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1182 MachineOperand &MO = getOperand(i);
1183 if (!MO.isReg() || MO.getReg() != FromReg)
1185 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1190 /// isSafeToMove - Return true if it is safe to move this instruction. If
1191 /// SawStore is set to true, it means that there is a store (or call) between
1192 /// the instruction's location and its intended destination.
1193 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1195 bool &SawStore) const {
1196 // Ignore stuff that we obviously can't move.
1197 if (MCID->mayStore() || MCID->isCall()) {
1202 if (isLabel() || isDebugValue() ||
1203 MCID->isTerminator() || hasUnmodeledSideEffects())
1206 // See if this instruction does a load. If so, we have to guarantee that the
1207 // loaded value doesn't change between the load and the its intended
1208 // destination. The check for isInvariantLoad gives the targe the chance to
1209 // classify the load as always returning a constant, e.g. a constant pool
1211 if (MCID->mayLoad() && !isInvariantLoad(AA))
1212 // Otherwise, this is a real load. If there is a store between the load and
1213 // end of block, or if the load is volatile, we can't move it.
1214 return !SawStore && !hasVolatileMemoryRef();
1219 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1220 /// instruction which defined the specified register instead of copying it.
1221 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1223 unsigned DstReg) const {
1224 bool SawStore = false;
1225 if (!TII->isTriviallyReMaterializable(this, AA) ||
1226 !isSafeToMove(TII, AA, SawStore))
1228 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1229 const MachineOperand &MO = getOperand(i);
1232 // FIXME: For now, do not remat any instruction with register operands.
1233 // Later on, we can loosen the restriction is the register operands have
1234 // not been modified between the def and use. Note, this is different from
1235 // MachineSink because the code is no longer in two-address form (at least
1239 else if (!MO.isDead() && MO.getReg() != DstReg)
1245 /// hasVolatileMemoryRef - Return true if this instruction may have a
1246 /// volatile memory reference, or if the information describing the
1247 /// memory reference is not available. Return false if it is known to
1248 /// have no volatile memory references.
1249 bool MachineInstr::hasVolatileMemoryRef() const {
1250 // An instruction known never to access memory won't have a volatile access.
1251 if (!MCID->mayStore() &&
1254 !hasUnmodeledSideEffects())
1257 // Otherwise, if the instruction has no memory reference information,
1258 // conservatively assume it wasn't preserved.
1259 if (memoperands_empty())
1262 // Check the memory reference information for volatile references.
1263 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1264 if ((*I)->isVolatile())
1270 /// isInvariantLoad - Return true if this instruction is loading from a
1271 /// location whose value is invariant across the function. For example,
1272 /// loading a value from the constant pool or from the argument area
1273 /// of a function if it does not change. This should only return true of
1274 /// *all* loads the instruction does are invariant (if it does multiple loads).
1275 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1276 // If the instruction doesn't load at all, it isn't an invariant load.
1277 if (!MCID->mayLoad())
1280 // If the instruction has lost its memoperands, conservatively assume that
1281 // it may not be an invariant load.
1282 if (memoperands_empty())
1285 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1287 for (mmo_iterator I = memoperands_begin(),
1288 E = memoperands_end(); I != E; ++I) {
1289 if ((*I)->isVolatile()) return false;
1290 if ((*I)->isStore()) return false;
1291 if ((*I)->isInvariant()) return true;
1293 if (const Value *V = (*I)->getValue()) {
1294 // A load from a constant PseudoSourceValue is invariant.
1295 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1296 if (PSV->isConstant(MFI))
1298 // If we have an AliasAnalysis, ask it whether the memory is constant.
1299 if (AA && AA->pointsToConstantMemory(
1300 AliasAnalysis::Location(V, (*I)->getSize(),
1301 (*I)->getTBAAInfo())))
1305 // Otherwise assume conservatively.
1309 // Everything checks out.
1313 /// isConstantValuePHI - If the specified instruction is a PHI that always
1314 /// merges together the same virtual register, return the register, otherwise
1316 unsigned MachineInstr::isConstantValuePHI() const {
1319 assert(getNumOperands() >= 3 &&
1320 "It's illegal to have a PHI without source operands");
1322 unsigned Reg = getOperand(1).getReg();
1323 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1324 if (getOperand(i).getReg() != Reg)
1329 bool MachineInstr::hasUnmodeledSideEffects() const {
1330 if (getDesc().hasUnmodeledSideEffects())
1332 if (isInlineAsm()) {
1333 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1334 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1341 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1343 bool MachineInstr::allDefsAreDead() const {
1344 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1345 const MachineOperand &MO = getOperand(i);
1346 if (!MO.isReg() || MO.isUse())
1354 /// copyImplicitOps - Copy implicit register operands from specified
1355 /// instruction to this instruction.
1356 void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1357 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1359 const MachineOperand &MO = MI->getOperand(i);
1360 if (MO.isReg() && MO.isImplicit())
1365 void MachineInstr::dump() const {
1366 dbgs() << " " << *this;
1369 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1370 raw_ostream &CommentOS) {
1371 const LLVMContext &Ctx = MF->getFunction()->getContext();
1372 if (!DL.isUnknown()) { // Print source line info.
1373 DIScope Scope(DL.getScope(Ctx));
1374 // Omit the directory, because it's likely to be long and uninteresting.
1376 CommentOS << Scope.getFilename();
1378 CommentOS << "<unknown>";
1379 CommentOS << ':' << DL.getLine();
1380 if (DL.getCol() != 0)
1381 CommentOS << ':' << DL.getCol();
1382 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1383 if (!InlinedAtDL.isUnknown()) {
1384 CommentOS << " @[ ";
1385 printDebugLoc(InlinedAtDL, MF, CommentOS);
1391 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1392 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1393 const MachineFunction *MF = 0;
1394 const MachineRegisterInfo *MRI = 0;
1395 if (const MachineBasicBlock *MBB = getParent()) {
1396 MF = MBB->getParent();
1398 TM = &MF->getTarget();
1400 MRI = &MF->getRegInfo();
1403 // Save a list of virtual registers.
1404 SmallVector<unsigned, 8> VirtRegs;
1406 // Print explicitly defined operands on the left of an assignment syntax.
1407 unsigned StartOp = 0, e = getNumOperands();
1408 for (; StartOp < e && getOperand(StartOp).isReg() &&
1409 getOperand(StartOp).isDef() &&
1410 !getOperand(StartOp).isImplicit();
1412 if (StartOp != 0) OS << ", ";
1413 getOperand(StartOp).print(OS, TM);
1414 unsigned Reg = getOperand(StartOp).getReg();
1415 if (TargetRegisterInfo::isVirtualRegister(Reg))
1416 VirtRegs.push_back(Reg);
1422 // Print the opcode name.
1423 OS << getDesc().getName();
1425 // Print the rest of the operands.
1426 bool OmittedAnyCallClobbers = false;
1427 bool FirstOp = true;
1428 unsigned AsmDescOp = ~0u;
1429 unsigned AsmOpCount = 0;
1431 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1432 // Print asm string.
1434 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1436 // Print HasSideEffects, IsAlignStack
1437 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1438 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1439 OS << " [sideeffect]";
1440 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1441 OS << " [alignstack]";
1443 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1448 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1449 const MachineOperand &MO = getOperand(i);
1451 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1452 VirtRegs.push_back(MO.getReg());
1454 // Omit call-clobbered registers which aren't used anywhere. This makes
1455 // call instructions much less noisy on targets where calls clobber lots
1456 // of registers. Don't rely on MO.isDead() because we may be called before
1457 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1458 if (MF && getDesc().isCall() &&
1459 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1460 unsigned Reg = MO.getReg();
1461 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1462 const MachineRegisterInfo &MRI = MF->getRegInfo();
1463 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1464 bool HasAliasLive = false;
1465 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1466 unsigned AliasReg = *Alias; ++Alias)
1467 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1468 HasAliasLive = true;
1471 if (!HasAliasLive) {
1472 OmittedAnyCallClobbers = true;
1479 if (FirstOp) FirstOp = false; else OS << ",";
1481 if (i < getDesc().NumOperands) {
1482 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1483 if (MCOI.isPredicate())
1485 if (MCOI.isOptionalDef())
1488 if (isDebugValue() && MO.isMetadata()) {
1489 // Pretty print DBG_VALUE instructions.
1490 const MDNode *MD = MO.getMetadata();
1491 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1492 OS << "!\"" << MDS->getString() << '\"';
1495 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1496 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1497 } else if (i == AsmDescOp && MO.isImm()) {
1498 // Pretty print the inline asm operand descriptor.
1499 OS << '$' << AsmOpCount++;
1500 unsigned Flag = MO.getImm();
1501 switch (InlineAsm::getKind(Flag)) {
1502 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1503 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1504 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1505 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1506 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1507 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1508 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1512 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1514 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1516 OS << ":RC" << RCID;
1519 unsigned TiedTo = 0;
1520 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1521 OS << " tiedto:$" << TiedTo;
1525 // Compute the index of the next operand descriptor.
1526 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1531 // Briefly indicate whether any call clobbers were omitted.
1532 if (OmittedAnyCallClobbers) {
1533 if (!FirstOp) OS << ",";
1537 bool HaveSemi = false;
1539 if (!HaveSemi) OS << ";"; HaveSemi = true;
1542 if (Flags & FrameSetup)
1546 if (!memoperands_empty()) {
1547 if (!HaveSemi) OS << ";"; HaveSemi = true;
1550 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1553 if (llvm::next(i) != e)
1558 // Print the regclass of any virtual registers encountered.
1559 if (MRI && !VirtRegs.empty()) {
1560 if (!HaveSemi) OS << ";"; HaveSemi = true;
1561 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1562 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1563 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1564 for (unsigned j = i+1; j != VirtRegs.size();) {
1565 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1569 if (VirtRegs[i] != VirtRegs[j])
1570 OS << "," << PrintReg(VirtRegs[j]);
1571 VirtRegs.erase(VirtRegs.begin()+j);
1576 // Print debug location information.
1577 if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1578 if (!HaveSemi) OS << ";"; HaveSemi = true;
1579 DIVariable DV(getOperand(e - 1).getMetadata());
1580 OS << " line no:" << DV.getLineNumber();
1581 if (MDNode *InlinedAt = DV.getInlinedAt()) {
1582 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1583 if (!InlinedAtDL.isUnknown()) {
1584 OS << " inlined @[ ";
1585 printDebugLoc(InlinedAtDL, MF, OS);
1589 } else if (!debugLoc.isUnknown() && MF) {
1590 if (!HaveSemi) OS << ";"; HaveSemi = true;
1592 printDebugLoc(debugLoc, MF, OS);
1598 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1599 const TargetRegisterInfo *RegInfo,
1600 bool AddIfNotFound) {
1601 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1602 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1604 SmallVector<unsigned,4> DeadOps;
1605 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1606 MachineOperand &MO = getOperand(i);
1607 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1609 unsigned Reg = MO.getReg();
1613 if (Reg == IncomingReg) {
1616 // The register is already marked kill.
1618 if (isPhysReg && isRegTiedToDefOperand(i))
1619 // Two-address uses of physregs must not be marked kill.
1624 } else if (hasAliases && MO.isKill() &&
1625 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1626 // A super-register kill already exists.
1627 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1629 if (RegInfo->isSubRegister(IncomingReg, Reg))
1630 DeadOps.push_back(i);
1634 // Trim unneeded kill operands.
1635 while (!DeadOps.empty()) {
1636 unsigned OpIdx = DeadOps.back();
1637 if (getOperand(OpIdx).isImplicit())
1638 RemoveOperand(OpIdx);
1640 getOperand(OpIdx).setIsKill(false);
1644 // If not found, this means an alias of one of the operands is killed. Add a
1645 // new implicit operand if required.
1646 if (!Found && AddIfNotFound) {
1647 addOperand(MachineOperand::CreateReg(IncomingReg,
1656 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1657 const TargetRegisterInfo *RegInfo,
1658 bool AddIfNotFound) {
1659 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1660 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1662 SmallVector<unsigned,4> DeadOps;
1663 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1664 MachineOperand &MO = getOperand(i);
1665 if (!MO.isReg() || !MO.isDef())
1667 unsigned Reg = MO.getReg();
1671 if (Reg == IncomingReg) {
1674 } else if (hasAliases && MO.isDead() &&
1675 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1676 // There exists a super-register that's marked dead.
1677 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1679 if (RegInfo->getSubRegisters(IncomingReg) &&
1680 RegInfo->getSuperRegisters(Reg) &&
1681 RegInfo->isSubRegister(IncomingReg, Reg))
1682 DeadOps.push_back(i);
1686 // Trim unneeded dead operands.
1687 while (!DeadOps.empty()) {
1688 unsigned OpIdx = DeadOps.back();
1689 if (getOperand(OpIdx).isImplicit())
1690 RemoveOperand(OpIdx);
1692 getOperand(OpIdx).setIsDead(false);
1696 // If not found, this means an alias of one of the operands is dead. Add a
1697 // new implicit operand if required.
1698 if (Found || !AddIfNotFound)
1701 addOperand(MachineOperand::CreateReg(IncomingReg,
1709 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1710 const TargetRegisterInfo *RegInfo) {
1711 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1712 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1716 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1717 const MachineOperand &MO = getOperand(i);
1718 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1719 MO.getSubReg() == 0)
1723 addOperand(MachineOperand::CreateReg(IncomingReg,
1728 void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
1729 const TargetRegisterInfo &TRI) {
1730 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1731 MachineOperand &MO = getOperand(i);
1732 if (!MO.isReg() || !MO.isDef()) continue;
1733 unsigned Reg = MO.getReg();
1734 if (Reg == 0) continue;
1736 for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
1737 E = UsedRegs.end(); I != E; ++I)
1738 if (TRI.regsOverlap(*I, Reg)) {
1742 // If there are no uses, including partial uses, the def is dead.
1743 if (Dead) MO.setIsDead();
1748 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1749 unsigned Hash = MI->getOpcode() * 37;
1750 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1751 const MachineOperand &MO = MI->getOperand(i);
1752 uint64_t Key = (uint64_t)MO.getType() << 32;
1753 switch (MO.getType()) {
1755 case MachineOperand::MO_Register:
1756 if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1757 continue; // Skip virtual register defs.
1760 case MachineOperand::MO_Immediate:
1763 case MachineOperand::MO_FrameIndex:
1764 case MachineOperand::MO_ConstantPoolIndex:
1765 case MachineOperand::MO_JumpTableIndex:
1766 Key |= MO.getIndex();
1768 case MachineOperand::MO_MachineBasicBlock:
1769 Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1771 case MachineOperand::MO_GlobalAddress:
1772 Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1774 case MachineOperand::MO_BlockAddress:
1775 Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1777 case MachineOperand::MO_MCSymbol:
1778 Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1781 Key += ~(Key << 32);
1783 Key += ~(Key << 13);
1787 Key += ~(Key << 27);
1789 Hash = (unsigned)Key + Hash * 37;
1794 void MachineInstr::emitError(StringRef Msg) const {
1795 // Find the source location cookie.
1796 unsigned LocCookie = 0;
1797 const MDNode *LocMD = 0;
1798 for (unsigned i = getNumOperands(); i != 0; --i) {
1799 if (getOperand(i-1).isMetadata() &&
1800 (LocMD = getOperand(i-1).getMetadata()) &&
1801 LocMD->getNumOperands() != 0) {
1802 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1803 LocCookie = CI->getZExtValue();
1809 if (const MachineBasicBlock *MBB = getParent())
1810 if (const MachineFunction *MF = MBB->getParent())
1811 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1812 report_fatal_error(Msg);