1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Function.h"
17 #include "llvm/InlineAsm.h"
18 #include "llvm/Metadata.h"
19 #include "llvm/Type.h"
20 #include "llvm/Value.h"
21 #include "llvm/Assembly/Writer.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetInstrDesc.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/Analysis/AliasAnalysis.h"
33 #include "llvm/Analysis/DebugInfo.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/LeakDetector.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/ADT/FoldingSet.h"
42 //===----------------------------------------------------------------------===//
43 // MachineOperand Implementation
44 //===----------------------------------------------------------------------===//
46 /// AddRegOperandToRegInfo - Add this register operand to the specified
47 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
48 /// explicitly nulled out.
49 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
50 assert(isReg() && "Can only add reg operand to use lists");
52 // If the reginfo pointer is null, just explicitly null out or next/prev
53 // pointers, to ensure they are not garbage.
55 Contents.Reg.Prev = 0;
56 Contents.Reg.Next = 0;
60 // Otherwise, add this operand to the head of the registers use/def list.
61 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
63 // For SSA values, we prefer to keep the definition at the start of the list.
64 // we do this by skipping over the definition if it is at the head of the
66 if (*Head && (*Head)->isDef())
67 Head = &(*Head)->Contents.Reg.Next;
69 Contents.Reg.Next = *Head;
70 if (Contents.Reg.Next) {
71 assert(getReg() == Contents.Reg.Next->getReg() &&
72 "Different regs on the same list!");
73 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
76 Contents.Reg.Prev = Head;
80 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
81 /// MachineRegisterInfo it is linked with.
82 void MachineOperand::RemoveRegOperandFromRegInfo() {
83 assert(isOnRegUseList() && "Reg operand is not on a use list");
84 // Unlink this from the doubly linked list of operands.
85 MachineOperand *NextOp = Contents.Reg.Next;
86 *Contents.Reg.Prev = NextOp;
88 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
89 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
91 Contents.Reg.Prev = 0;
92 Contents.Reg.Next = 0;
95 void MachineOperand::setReg(unsigned Reg) {
96 if (getReg() == Reg) return; // No change.
98 // Otherwise, we have to change the register. If this operand is embedded
99 // into a machine function, we need to update the old and new register's
101 if (MachineInstr *MI = getParent())
102 if (MachineBasicBlock *MBB = MI->getParent())
103 if (MachineFunction *MF = MBB->getParent()) {
104 RemoveRegOperandFromRegInfo();
105 Contents.Reg.RegNo = Reg;
106 AddRegOperandToRegInfo(&MF->getRegInfo());
110 // Otherwise, just change the register, no problem. :)
111 Contents.Reg.RegNo = Reg;
114 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
115 const TargetRegisterInfo &TRI) {
116 assert(TargetRegisterInfo::isVirtualRegister(Reg));
117 if (SubIdx && getSubReg())
118 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
124 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
125 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
127 Reg = TRI.getSubReg(Reg, getSubReg());
128 assert(Reg && "Invalid SubReg for physical register");
134 /// ChangeToImmediate - Replace this operand with a new immediate operand of
135 /// the specified value. If an operand is known to be an immediate already,
136 /// the setImm method should be used.
137 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
138 // If this operand is currently a register operand, and if this is in a
139 // function, deregister the operand from the register's use/def list.
140 if (isReg() && getParent() && getParent()->getParent() &&
141 getParent()->getParent()->getParent())
142 RemoveRegOperandFromRegInfo();
144 OpKind = MO_Immediate;
145 Contents.ImmVal = ImmVal;
148 /// ChangeToRegister - Replace this operand with a new register operand of
149 /// the specified value. If an operand is known to be an register already,
150 /// the setReg method should be used.
151 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
152 bool isKill, bool isDead, bool isUndef,
154 // If this operand is already a register operand, use setReg to update the
155 // register's use/def lists.
157 assert(!isEarlyClobber());
160 // Otherwise, change this to a register and set the reg#.
161 OpKind = MO_Register;
162 Contents.Reg.RegNo = Reg;
164 // If this operand is embedded in a function, add the operand to the
165 // register's use/def list.
166 if (MachineInstr *MI = getParent())
167 if (MachineBasicBlock *MBB = MI->getParent())
168 if (MachineFunction *MF = MBB->getParent())
169 AddRegOperandToRegInfo(&MF->getRegInfo());
177 IsEarlyClobber = false;
182 /// isIdenticalTo - Return true if this operand is identical to the specified
184 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
185 if (getType() != Other.getType() ||
186 getTargetFlags() != Other.getTargetFlags())
190 default: llvm_unreachable("Unrecognized operand type");
191 case MachineOperand::MO_Register:
192 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
193 getSubReg() == Other.getSubReg();
194 case MachineOperand::MO_Immediate:
195 return getImm() == Other.getImm();
196 case MachineOperand::MO_FPImmediate:
197 return getFPImm() == Other.getFPImm();
198 case MachineOperand::MO_MachineBasicBlock:
199 return getMBB() == Other.getMBB();
200 case MachineOperand::MO_FrameIndex:
201 return getIndex() == Other.getIndex();
202 case MachineOperand::MO_ConstantPoolIndex:
203 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
204 case MachineOperand::MO_JumpTableIndex:
205 return getIndex() == Other.getIndex();
206 case MachineOperand::MO_GlobalAddress:
207 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
208 case MachineOperand::MO_ExternalSymbol:
209 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
210 getOffset() == Other.getOffset();
211 case MachineOperand::MO_BlockAddress:
212 return getBlockAddress() == Other.getBlockAddress();
213 case MachineOperand::MO_MCSymbol:
214 return getMCSymbol() == Other.getMCSymbol();
215 case MachineOperand::MO_Metadata:
216 return getMetadata() == Other.getMetadata();
220 /// print - Print the specified machine operand.
222 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
223 // If the instruction is embedded into a basic block, we can find the
224 // target info for the instruction.
226 if (const MachineInstr *MI = getParent())
227 if (const MachineBasicBlock *MBB = MI->getParent())
228 if (const MachineFunction *MF = MBB->getParent())
229 TM = &MF->getTarget();
232 case MachineOperand::MO_Register:
233 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
234 OS << "%reg" << getReg();
237 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
239 OS << "%physreg" << getReg();
242 if (getSubReg() != 0) {
244 OS << ':' << TM->getRegisterInfo()->getSubRegIndexName(getSubReg());
246 OS << ':' << getSubReg();
249 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
252 bool NeedComma = false;
254 if (NeedComma) OS << ',';
255 if (isEarlyClobber())
256 OS << "earlyclobber,";
261 } else if (isImplicit()) {
266 if (isKill() || isDead() || isUndef()) {
267 if (NeedComma) OS << ',';
268 if (isKill()) OS << "kill";
269 if (isDead()) OS << "dead";
271 if (isKill() || isDead())
279 case MachineOperand::MO_Immediate:
282 case MachineOperand::MO_FPImmediate:
283 if (getFPImm()->getType()->isFloatTy())
284 OS << getFPImm()->getValueAPF().convertToFloat();
286 OS << getFPImm()->getValueAPF().convertToDouble();
288 case MachineOperand::MO_MachineBasicBlock:
289 OS << "<BB#" << getMBB()->getNumber() << ">";
291 case MachineOperand::MO_FrameIndex:
292 OS << "<fi#" << getIndex() << '>';
294 case MachineOperand::MO_ConstantPoolIndex:
295 OS << "<cp#" << getIndex();
296 if (getOffset()) OS << "+" << getOffset();
299 case MachineOperand::MO_JumpTableIndex:
300 OS << "<jt#" << getIndex() << '>';
302 case MachineOperand::MO_GlobalAddress:
304 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
305 if (getOffset()) OS << "+" << getOffset();
308 case MachineOperand::MO_ExternalSymbol:
309 OS << "<es:" << getSymbolName();
310 if (getOffset()) OS << "+" << getOffset();
313 case MachineOperand::MO_BlockAddress:
315 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
318 case MachineOperand::MO_Metadata:
320 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
323 case MachineOperand::MO_MCSymbol:
324 OS << "<MCSym=" << *getMCSymbol() << '>';
327 llvm_unreachable("Unrecognized operand type");
330 if (unsigned TF = getTargetFlags())
331 OS << "[TF=" << TF << ']';
334 //===----------------------------------------------------------------------===//
335 // MachineMemOperand Implementation
336 //===----------------------------------------------------------------------===//
338 /// getAddrSpace - Return the LLVM IR address space number that this pointer
340 unsigned MachinePointerInfo::getAddrSpace() const {
341 if (V == 0) return 0;
342 return cast<PointerType>(V->getType())->getAddressSpace();
346 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
347 uint64_t s, unsigned int a)
348 : PtrInfo(ptrinfo), Size(s),
349 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)) {
350 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
351 "invalid pointer value");
352 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
353 assert((isLoad() || isStore()) && "Not a load/store!");
356 /// Profile - Gather unique data for the object.
358 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
359 ID.AddInteger(getOffset());
361 ID.AddPointer(getValue());
362 ID.AddInteger(Flags);
365 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
366 // The Value and Offset may differ due to CSE. But the flags and size
367 // should be the same.
368 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
369 assert(MMO->getSize() == getSize() && "Size mismatch!");
371 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
372 // Update the alignment value.
373 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
374 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
375 // Also update the base and offset, because the new alignment may
376 // not be applicable with the old ones.
377 PtrInfo = MMO->PtrInfo;
381 /// getAlignment - Return the minimum known alignment in bytes of the
382 /// actual memory reference.
383 uint64_t MachineMemOperand::getAlignment() const {
384 return MinAlign(getBaseAlignment(), getOffset());
387 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
388 assert((MMO.isLoad() || MMO.isStore()) &&
389 "SV has to be a load, store or both.");
391 if (MMO.isVolatile())
400 // Print the address information.
405 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
407 // If the alignment of the memory reference itself differs from the alignment
408 // of the base pointer, print the base alignment explicitly, next to the base
410 if (MMO.getBaseAlignment() != MMO.getAlignment())
411 OS << "(align=" << MMO.getBaseAlignment() << ")";
413 if (MMO.getOffset() != 0)
414 OS << "+" << MMO.getOffset();
417 // Print the alignment of the reference.
418 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
419 MMO.getBaseAlignment() != MMO.getSize())
420 OS << "(align=" << MMO.getAlignment() << ")";
425 //===----------------------------------------------------------------------===//
426 // MachineInstr Implementation
427 //===----------------------------------------------------------------------===//
429 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
430 /// TID NULL and no operands.
431 MachineInstr::MachineInstr()
432 : TID(0), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
434 // Make sure that we get added to a machine basicblock
435 LeakDetector::addGarbageObject(this);
438 void MachineInstr::addImplicitDefUseOperands() {
439 if (TID->ImplicitDefs)
440 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
441 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
442 if (TID->ImplicitUses)
443 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
444 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
447 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
448 /// implicit operands. It reserves space for the number of operands specified by
449 /// the TargetInstrDesc.
450 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
451 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
452 MemRefs(0), MemRefsEnd(0), Parent(0) {
454 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
455 Operands.reserve(NumImplicitOps + TID->getNumOperands());
457 addImplicitDefUseOperands();
458 // Make sure that we get added to a machine basicblock
459 LeakDetector::addGarbageObject(this);
462 /// MachineInstr ctor - As above, but with a DebugLoc.
463 MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
465 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
466 Parent(0), debugLoc(dl) {
468 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
469 Operands.reserve(NumImplicitOps + TID->getNumOperands());
471 addImplicitDefUseOperands();
472 // Make sure that we get added to a machine basicblock
473 LeakDetector::addGarbageObject(this);
476 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
477 /// that the MachineInstr is created and added to the end of the specified
479 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
480 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
481 MemRefs(0), MemRefsEnd(0), Parent(0) {
482 assert(MBB && "Cannot use inserting ctor with null basic block!");
483 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
484 Operands.reserve(NumImplicitOps + TID->getNumOperands());
485 addImplicitDefUseOperands();
486 // Make sure that we get added to a machine basicblock
487 LeakDetector::addGarbageObject(this);
488 MBB->push_back(this); // Add instruction to end of basic block!
491 /// MachineInstr ctor - As above, but with a DebugLoc.
493 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
494 const TargetInstrDesc &tid)
495 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
496 Parent(0), debugLoc(dl) {
497 assert(MBB && "Cannot use inserting ctor with null basic block!");
498 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
499 Operands.reserve(NumImplicitOps + TID->getNumOperands());
500 addImplicitDefUseOperands();
501 // Make sure that we get added to a machine basicblock
502 LeakDetector::addGarbageObject(this);
503 MBB->push_back(this); // Add instruction to end of basic block!
506 /// MachineInstr ctor - Copies MachineInstr arg exactly
508 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
509 : TID(&MI.getDesc()), NumImplicitOps(0), AsmPrinterFlags(0),
510 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
511 Parent(0), debugLoc(MI.getDebugLoc()) {
512 Operands.reserve(MI.getNumOperands());
515 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
516 addOperand(MI.getOperand(i));
517 NumImplicitOps = MI.NumImplicitOps;
519 // Set parent to null.
522 LeakDetector::addGarbageObject(this);
525 MachineInstr::~MachineInstr() {
526 LeakDetector::removeGarbageObject(this);
528 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
529 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
530 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
531 "Reg operand def/use list corrupted");
536 /// getRegInfo - If this instruction is embedded into a MachineFunction,
537 /// return the MachineRegisterInfo object for the current function, otherwise
539 MachineRegisterInfo *MachineInstr::getRegInfo() {
540 if (MachineBasicBlock *MBB = getParent())
541 return &MBB->getParent()->getRegInfo();
545 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
546 /// this instruction from their respective use lists. This requires that the
547 /// operands already be on their use lists.
548 void MachineInstr::RemoveRegOperandsFromUseLists() {
549 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
550 if (Operands[i].isReg())
551 Operands[i].RemoveRegOperandFromRegInfo();
555 /// AddRegOperandsToUseLists - Add all of the register operands in
556 /// this instruction from their respective use lists. This requires that the
557 /// operands not be on their use lists yet.
558 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
559 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
560 if (Operands[i].isReg())
561 Operands[i].AddRegOperandToRegInfo(&RegInfo);
566 /// addOperand - Add the specified operand to the instruction. If it is an
567 /// implicit operand, it is added to the end of the operand list. If it is
568 /// an explicit operand it is added at the end of the explicit operand list
569 /// (before the first implicit operand).
570 void MachineInstr::addOperand(const MachineOperand &Op) {
571 bool isImpReg = Op.isReg() && Op.isImplicit();
572 assert((isImpReg || !OperandsComplete()) &&
573 "Trying to add an operand to a machine instr that is already done!");
575 MachineRegisterInfo *RegInfo = getRegInfo();
577 // If we are adding the operand to the end of the list, our job is simpler.
578 // This is true most of the time, so this is a reasonable optimization.
579 if (isImpReg || NumImplicitOps == 0) {
580 // We can only do this optimization if we know that the operand list won't
582 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
583 Operands.push_back(Op);
585 // Set the parent of the operand.
586 Operands.back().ParentMI = this;
588 // If the operand is a register, update the operand's use list.
590 Operands.back().AddRegOperandToRegInfo(RegInfo);
591 // If the register operand is flagged as early, mark the operand as such
592 unsigned OpNo = Operands.size() - 1;
593 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
594 Operands[OpNo].setIsEarlyClobber(true);
600 // Otherwise, we have to insert a real operand before any implicit ones.
601 unsigned OpNo = Operands.size()-NumImplicitOps;
603 // If this instruction isn't embedded into a function, then we don't need to
604 // update any operand lists.
606 // Simple insertion, no reginfo update needed for other register operands.
607 Operands.insert(Operands.begin()+OpNo, Op);
608 Operands[OpNo].ParentMI = this;
610 // Do explicitly set the reginfo for this operand though, to ensure the
611 // next/prev fields are properly nulled out.
612 if (Operands[OpNo].isReg()) {
613 Operands[OpNo].AddRegOperandToRegInfo(0);
614 // If the register operand is flagged as early, mark the operand as such
615 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
616 Operands[OpNo].setIsEarlyClobber(true);
619 } else if (Operands.size()+1 <= Operands.capacity()) {
620 // Otherwise, we have to remove register operands from their register use
621 // list, add the operand, then add the register operands back to their use
622 // list. This also must handle the case when the operand list reallocates
623 // to somewhere else.
625 // If insertion of this operand won't cause reallocation of the operand
626 // list, just remove the implicit operands, add the operand, then re-add all
627 // the rest of the operands.
628 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
629 assert(Operands[i].isReg() && "Should only be an implicit reg!");
630 Operands[i].RemoveRegOperandFromRegInfo();
633 // Add the operand. If it is a register, add it to the reg list.
634 Operands.insert(Operands.begin()+OpNo, Op);
635 Operands[OpNo].ParentMI = this;
637 if (Operands[OpNo].isReg()) {
638 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
639 // If the register operand is flagged as early, mark the operand as such
640 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
641 Operands[OpNo].setIsEarlyClobber(true);
644 // Re-add all the implicit ops.
645 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
646 assert(Operands[i].isReg() && "Should only be an implicit reg!");
647 Operands[i].AddRegOperandToRegInfo(RegInfo);
650 // Otherwise, we will be reallocating the operand list. Remove all reg
651 // operands from their list, then readd them after the operand list is
653 RemoveRegOperandsFromUseLists();
655 Operands.insert(Operands.begin()+OpNo, Op);
656 Operands[OpNo].ParentMI = this;
658 // Re-add all the operands.
659 AddRegOperandsToUseLists(*RegInfo);
661 // If the register operand is flagged as early, mark the operand as such
662 if (Operands[OpNo].isReg()
663 && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
664 Operands[OpNo].setIsEarlyClobber(true);
668 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
669 /// fewer operand than it started with.
671 void MachineInstr::RemoveOperand(unsigned OpNo) {
672 assert(OpNo < Operands.size() && "Invalid operand number");
674 // Special case removing the last one.
675 if (OpNo == Operands.size()-1) {
676 // If needed, remove from the reg def/use list.
677 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
678 Operands.back().RemoveRegOperandFromRegInfo();
684 // Otherwise, we are removing an interior operand. If we have reginfo to
685 // update, remove all operands that will be shifted down from their reg lists,
686 // move everything down, then re-add them.
687 MachineRegisterInfo *RegInfo = getRegInfo();
689 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
690 if (Operands[i].isReg())
691 Operands[i].RemoveRegOperandFromRegInfo();
695 Operands.erase(Operands.begin()+OpNo);
698 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
699 if (Operands[i].isReg())
700 Operands[i].AddRegOperandToRegInfo(RegInfo);
705 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
706 /// This function should be used only occasionally. The setMemRefs function
707 /// is the primary method for setting up a MachineInstr's MemRefs list.
708 void MachineInstr::addMemOperand(MachineFunction &MF,
709 MachineMemOperand *MO) {
710 mmo_iterator OldMemRefs = MemRefs;
711 mmo_iterator OldMemRefsEnd = MemRefsEnd;
713 size_t NewNum = (MemRefsEnd - MemRefs) + 1;
714 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
715 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
717 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
718 NewMemRefs[NewNum - 1] = MO;
720 MemRefs = NewMemRefs;
721 MemRefsEnd = NewMemRefsEnd;
724 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
725 MICheckType Check) const {
726 // If opcodes or number of operands are not the same then the two
727 // instructions are obviously not identical.
728 if (Other->getOpcode() != getOpcode() ||
729 Other->getNumOperands() != getNumOperands())
732 // Check operands to make sure they match.
733 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
734 const MachineOperand &MO = getOperand(i);
735 const MachineOperand &OMO = Other->getOperand(i);
736 // Clients may or may not want to ignore defs when testing for equality.
737 // For example, machine CSE pass only cares about finding common
738 // subexpressions, so it's safe to ignore virtual register defs.
739 if (Check != CheckDefs && MO.isReg() && MO.isDef()) {
740 if (Check == IgnoreDefs)
742 // Check == IgnoreVRegDefs
743 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
744 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
745 if (MO.getReg() != OMO.getReg())
747 } else if (!MO.isIdenticalTo(OMO))
753 /// removeFromParent - This method unlinks 'this' from the containing basic
754 /// block, and returns it, but does not delete it.
755 MachineInstr *MachineInstr::removeFromParent() {
756 assert(getParent() && "Not embedded in a basic block!");
757 getParent()->remove(this);
762 /// eraseFromParent - This method unlinks 'this' from the containing basic
763 /// block, and deletes it.
764 void MachineInstr::eraseFromParent() {
765 assert(getParent() && "Not embedded in a basic block!");
766 getParent()->erase(this);
770 /// OperandComplete - Return true if it's illegal to add a new operand
772 bool MachineInstr::OperandsComplete() const {
773 unsigned short NumOperands = TID->getNumOperands();
774 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
775 return true; // Broken: we have all the operands of this instruction!
779 /// getNumExplicitOperands - Returns the number of non-implicit operands.
781 unsigned MachineInstr::getNumExplicitOperands() const {
782 unsigned NumOperands = TID->getNumOperands();
783 if (!TID->isVariadic())
786 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
787 const MachineOperand &MO = getOperand(i);
788 if (!MO.isReg() || !MO.isImplicit())
795 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
796 /// the specific register or -1 if it is not found. It further tightens
797 /// the search criteria to a use that kills the register if isKill is true.
798 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
799 const TargetRegisterInfo *TRI) const {
800 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
801 const MachineOperand &MO = getOperand(i);
802 if (!MO.isReg() || !MO.isUse())
804 unsigned MOReg = MO.getReg();
809 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
810 TargetRegisterInfo::isPhysicalRegister(Reg) &&
811 TRI->isSubRegister(MOReg, Reg)))
812 if (!isKill || MO.isKill())
818 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
819 /// indicating if this instruction reads or writes Reg. This also considers
822 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
823 SmallVectorImpl<unsigned> *Ops) const {
824 bool PartDef = false; // Partial redefine.
825 bool FullDef = false; // Full define.
828 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
829 const MachineOperand &MO = getOperand(i);
830 if (!MO.isReg() || MO.getReg() != Reg)
835 Use |= !MO.isUndef();
836 else if (MO.getSubReg())
841 // A partial redefine uses Reg unless there is also a full define.
842 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
845 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
846 /// the specified register or -1 if it is not found. If isDead is true, defs
847 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
848 /// also checks if there is a def of a super-register.
850 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
851 const TargetRegisterInfo *TRI) const {
852 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
853 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
854 const MachineOperand &MO = getOperand(i);
855 if (!MO.isReg() || !MO.isDef())
857 unsigned MOReg = MO.getReg();
858 bool Found = (MOReg == Reg);
859 if (!Found && TRI && isPhys &&
860 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
862 Found = TRI->regsOverlap(MOReg, Reg);
864 Found = TRI->isSubRegister(MOReg, Reg);
866 if (Found && (!isDead || MO.isDead()))
872 /// findFirstPredOperandIdx() - Find the index of the first operand in the
873 /// operand list that is used to represent the predicate. It returns -1 if
875 int MachineInstr::findFirstPredOperandIdx() const {
876 const TargetInstrDesc &TID = getDesc();
877 if (TID.isPredicable()) {
878 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
879 if (TID.OpInfo[i].isPredicate())
886 /// isRegTiedToUseOperand - Given the index of a register def operand,
887 /// check if the register def is tied to a source operand, due to either
888 /// two-address elimination or inline assembly constraints. Returns the
889 /// first tied use operand index by reference is UseOpIdx is not null.
891 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
893 assert(DefOpIdx >= 3);
894 const MachineOperand &MO = getOperand(DefOpIdx);
895 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
897 // Determine the actual operand index that corresponds to this index.
899 unsigned DefPart = 0;
900 for (unsigned i = 2, e = getNumOperands(); i < e; ) {
901 const MachineOperand &FMO = getOperand(i);
902 // After the normal asm operands there may be additional imp-def regs.
905 // Skip over this def.
906 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
907 unsigned PrevDef = i + 1;
908 i = PrevDef + NumOps;
910 DefPart = DefOpIdx - PrevDef;
915 for (unsigned i = 2, e = getNumOperands(); i != e; ++i) {
916 const MachineOperand &FMO = getOperand(i);
919 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
922 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
925 *UseOpIdx = (unsigned)i + 1 + DefPart;
932 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
933 const TargetInstrDesc &TID = getDesc();
934 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
935 const MachineOperand &MO = getOperand(i);
936 if (MO.isReg() && MO.isUse() &&
937 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
939 *UseOpIdx = (unsigned)i;
946 /// isRegTiedToDefOperand - Return true if the operand of the specified index
947 /// is a register use and it is tied to an def operand. It also returns the def
948 /// operand index by reference.
950 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
952 const MachineOperand &MO = getOperand(UseOpIdx);
953 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
956 // Find the flag operand corresponding to UseOpIdx
957 unsigned FlagIdx, NumOps=0;
958 for (FlagIdx = 2; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
959 const MachineOperand &UFMO = getOperand(FlagIdx);
960 // After the normal asm operands there may be additional imp-def regs.
963 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
964 assert(NumOps < getNumOperands() && "Invalid inline asm flag");
965 if (UseOpIdx < FlagIdx+NumOps+1)
968 if (FlagIdx >= UseOpIdx)
970 const MachineOperand &UFMO = getOperand(FlagIdx);
972 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
977 // Remember to adjust the index. First operand is asm string, second is
978 // the AlignStack bit, then there is a flag for each.
980 const MachineOperand &FMO = getOperand(DefIdx);
982 // Skip over this def.
983 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
986 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
992 const TargetInstrDesc &TID = getDesc();
993 if (UseOpIdx >= TID.getNumOperands())
995 const MachineOperand &MO = getOperand(UseOpIdx);
996 if (!MO.isReg() || !MO.isUse())
998 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
1002 *DefOpIdx = (unsigned)DefIdx;
1006 /// clearKillInfo - Clears kill flags on all operands.
1008 void MachineInstr::clearKillInfo() {
1009 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1010 MachineOperand &MO = getOperand(i);
1011 if (MO.isReg() && MO.isUse())
1012 MO.setIsKill(false);
1016 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1018 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1019 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1020 const MachineOperand &MO = MI->getOperand(i);
1021 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1023 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1024 MachineOperand &MOp = getOperand(j);
1025 if (!MOp.isIdenticalTo(MO))
1036 /// copyPredicates - Copies predicate operand(s) from MI.
1037 void MachineInstr::copyPredicates(const MachineInstr *MI) {
1038 const TargetInstrDesc &TID = MI->getDesc();
1039 if (!TID.isPredicable())
1041 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1042 if (TID.OpInfo[i].isPredicate()) {
1043 // Predicated operands must be last operands.
1044 addOperand(MI->getOperand(i));
1049 void MachineInstr::substituteRegister(unsigned FromReg,
1052 const TargetRegisterInfo &RegInfo) {
1053 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1055 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1056 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1057 MachineOperand &MO = getOperand(i);
1058 if (!MO.isReg() || MO.getReg() != FromReg)
1060 MO.substPhysReg(ToReg, RegInfo);
1063 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1064 MachineOperand &MO = getOperand(i);
1065 if (!MO.isReg() || MO.getReg() != FromReg)
1067 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1072 /// isSafeToMove - Return true if it is safe to move this instruction. If
1073 /// SawStore is set to true, it means that there is a store (or call) between
1074 /// the instruction's location and its intended destination.
1075 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1077 bool &SawStore) const {
1078 // Ignore stuff that we obviously can't move.
1079 if (TID->mayStore() || TID->isCall()) {
1083 if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
1086 // See if this instruction does a load. If so, we have to guarantee that the
1087 // loaded value doesn't change between the load and the its intended
1088 // destination. The check for isInvariantLoad gives the targe the chance to
1089 // classify the load as always returning a constant, e.g. a constant pool
1091 if (TID->mayLoad() && !isInvariantLoad(AA))
1092 // Otherwise, this is a real load. If there is a store between the load and
1093 // end of block, or if the load is volatile, we can't move it.
1094 return !SawStore && !hasVolatileMemoryRef();
1099 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1100 /// instruction which defined the specified register instead of copying it.
1101 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1103 unsigned DstReg) const {
1104 bool SawStore = false;
1105 if (!TII->isTriviallyReMaterializable(this, AA) ||
1106 !isSafeToMove(TII, AA, SawStore))
1108 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1109 const MachineOperand &MO = getOperand(i);
1112 // FIXME: For now, do not remat any instruction with register operands.
1113 // Later on, we can loosen the restriction is the register operands have
1114 // not been modified between the def and use. Note, this is different from
1115 // MachineSink because the code is no longer in two-address form (at least
1119 else if (!MO.isDead() && MO.getReg() != DstReg)
1125 /// hasVolatileMemoryRef - Return true if this instruction may have a
1126 /// volatile memory reference, or if the information describing the
1127 /// memory reference is not available. Return false if it is known to
1128 /// have no volatile memory references.
1129 bool MachineInstr::hasVolatileMemoryRef() const {
1130 // An instruction known never to access memory won't have a volatile access.
1131 if (!TID->mayStore() &&
1134 !TID->hasUnmodeledSideEffects())
1137 // Otherwise, if the instruction has no memory reference information,
1138 // conservatively assume it wasn't preserved.
1139 if (memoperands_empty())
1142 // Check the memory reference information for volatile references.
1143 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1144 if ((*I)->isVolatile())
1150 /// isInvariantLoad - Return true if this instruction is loading from a
1151 /// location whose value is invariant across the function. For example,
1152 /// loading a value from the constant pool or from the argument area
1153 /// of a function if it does not change. This should only return true of
1154 /// *all* loads the instruction does are invariant (if it does multiple loads).
1155 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1156 // If the instruction doesn't load at all, it isn't an invariant load.
1157 if (!TID->mayLoad())
1160 // If the instruction has lost its memoperands, conservatively assume that
1161 // it may not be an invariant load.
1162 if (memoperands_empty())
1165 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1167 for (mmo_iterator I = memoperands_begin(),
1168 E = memoperands_end(); I != E; ++I) {
1169 if ((*I)->isVolatile()) return false;
1170 if ((*I)->isStore()) return false;
1172 if (const Value *V = (*I)->getValue()) {
1173 // A load from a constant PseudoSourceValue is invariant.
1174 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1175 if (PSV->isConstant(MFI))
1177 // If we have an AliasAnalysis, ask it whether the memory is constant.
1178 if (AA && AA->pointsToConstantMemory(V))
1182 // Otherwise assume conservatively.
1186 // Everything checks out.
1190 /// isConstantValuePHI - If the specified instruction is a PHI that always
1191 /// merges together the same virtual register, return the register, otherwise
1193 unsigned MachineInstr::isConstantValuePHI() const {
1196 assert(getNumOperands() >= 3 &&
1197 "It's illegal to have a PHI without source operands");
1199 unsigned Reg = getOperand(1).getReg();
1200 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1201 if (getOperand(i).getReg() != Reg)
1206 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1208 bool MachineInstr::allDefsAreDead() const {
1209 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1210 const MachineOperand &MO = getOperand(i);
1211 if (!MO.isReg() || MO.isUse())
1219 void MachineInstr::dump() const {
1220 dbgs() << " " << *this;
1223 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1224 raw_ostream &CommentOS) {
1225 const LLVMContext &Ctx = MF->getFunction()->getContext();
1226 if (!DL.isUnknown()) { // Print source line info.
1227 DIScope Scope(DL.getScope(Ctx));
1228 // Omit the directory, because it's likely to be long and uninteresting.
1230 CommentOS << Scope.getFilename();
1232 CommentOS << "<unknown>";
1233 CommentOS << ':' << DL.getLine();
1234 if (DL.getCol() != 0)
1235 CommentOS << ':' << DL.getCol();
1236 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1237 if (!InlinedAtDL.isUnknown()) {
1238 CommentOS << " @[ ";
1239 printDebugLoc(InlinedAtDL, MF, CommentOS);
1245 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1246 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1247 const MachineFunction *MF = 0;
1248 const MachineRegisterInfo *MRI = 0;
1249 if (const MachineBasicBlock *MBB = getParent()) {
1250 MF = MBB->getParent();
1252 TM = &MF->getTarget();
1254 MRI = &MF->getRegInfo();
1257 // Save a list of virtual registers.
1258 SmallVector<unsigned, 8> VirtRegs;
1260 // Print explicitly defined operands on the left of an assignment syntax.
1261 unsigned StartOp = 0, e = getNumOperands();
1262 for (; StartOp < e && getOperand(StartOp).isReg() &&
1263 getOperand(StartOp).isDef() &&
1264 !getOperand(StartOp).isImplicit();
1266 if (StartOp != 0) OS << ", ";
1267 getOperand(StartOp).print(OS, TM);
1268 unsigned Reg = getOperand(StartOp).getReg();
1269 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg))
1270 VirtRegs.push_back(Reg);
1276 // Print the opcode name.
1277 OS << getDesc().getName();
1279 // Print the rest of the operands.
1280 bool OmittedAnyCallClobbers = false;
1281 bool FirstOp = true;
1282 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1283 const MachineOperand &MO = getOperand(i);
1285 if (MO.isReg() && MO.getReg() &&
1286 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1287 VirtRegs.push_back(MO.getReg());
1289 // Omit call-clobbered registers which aren't used anywhere. This makes
1290 // call instructions much less noisy on targets where calls clobber lots
1291 // of registers. Don't rely on MO.isDead() because we may be called before
1292 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1293 if (MF && getDesc().isCall() &&
1294 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1295 unsigned Reg = MO.getReg();
1296 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
1297 const MachineRegisterInfo &MRI = MF->getRegInfo();
1298 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1299 bool HasAliasLive = false;
1300 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1301 unsigned AliasReg = *Alias; ++Alias)
1302 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1303 HasAliasLive = true;
1306 if (!HasAliasLive) {
1307 OmittedAnyCallClobbers = true;
1314 if (FirstOp) FirstOp = false; else OS << ",";
1316 if (i < getDesc().NumOperands) {
1317 const TargetOperandInfo &TOI = getDesc().OpInfo[i];
1318 if (TOI.isPredicate())
1320 if (TOI.isOptionalDef())
1323 if (isDebugValue() && MO.isMetadata()) {
1324 // Pretty print DBG_VALUE instructions.
1325 const MDNode *MD = MO.getMetadata();
1326 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1327 OS << "!\"" << MDS->getString() << '\"';
1330 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1331 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1336 // Briefly indicate whether any call clobbers were omitted.
1337 if (OmittedAnyCallClobbers) {
1338 if (!FirstOp) OS << ",";
1342 bool HaveSemi = false;
1343 if (!memoperands_empty()) {
1344 if (!HaveSemi) OS << ";"; HaveSemi = true;
1347 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1350 if (llvm::next(i) != e)
1355 // Print the regclass of any virtual registers encountered.
1356 if (MRI && !VirtRegs.empty()) {
1357 if (!HaveSemi) OS << ";"; HaveSemi = true;
1358 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1359 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1360 OS << " " << RC->getName() << ":%reg" << VirtRegs[i];
1361 for (unsigned j = i+1; j != VirtRegs.size();) {
1362 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1366 if (VirtRegs[i] != VirtRegs[j])
1367 OS << "," << VirtRegs[j];
1368 VirtRegs.erase(VirtRegs.begin()+j);
1373 if (!debugLoc.isUnknown() && MF) {
1374 if (!HaveSemi) OS << ";";
1376 printDebugLoc(debugLoc, MF, OS);
1382 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1383 const TargetRegisterInfo *RegInfo,
1384 bool AddIfNotFound) {
1385 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1386 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1388 SmallVector<unsigned,4> DeadOps;
1389 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1390 MachineOperand &MO = getOperand(i);
1391 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1393 unsigned Reg = MO.getReg();
1397 if (Reg == IncomingReg) {
1400 // The register is already marked kill.
1402 if (isPhysReg && isRegTiedToDefOperand(i))
1403 // Two-address uses of physregs must not be marked kill.
1408 } else if (hasAliases && MO.isKill() &&
1409 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1410 // A super-register kill already exists.
1411 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1413 if (RegInfo->isSubRegister(IncomingReg, Reg))
1414 DeadOps.push_back(i);
1418 // Trim unneeded kill operands.
1419 while (!DeadOps.empty()) {
1420 unsigned OpIdx = DeadOps.back();
1421 if (getOperand(OpIdx).isImplicit())
1422 RemoveOperand(OpIdx);
1424 getOperand(OpIdx).setIsKill(false);
1428 // If not found, this means an alias of one of the operands is killed. Add a
1429 // new implicit operand if required.
1430 if (!Found && AddIfNotFound) {
1431 addOperand(MachineOperand::CreateReg(IncomingReg,
1440 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1441 const TargetRegisterInfo *RegInfo,
1442 bool AddIfNotFound) {
1443 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1444 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1446 SmallVector<unsigned,4> DeadOps;
1447 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1448 MachineOperand &MO = getOperand(i);
1449 if (!MO.isReg() || !MO.isDef())
1451 unsigned Reg = MO.getReg();
1455 if (Reg == IncomingReg) {
1458 // The register is already marked dead.
1463 } else if (hasAliases && MO.isDead() &&
1464 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1465 // There exists a super-register that's marked dead.
1466 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1468 if (RegInfo->getSubRegisters(IncomingReg) &&
1469 RegInfo->getSuperRegisters(Reg) &&
1470 RegInfo->isSubRegister(IncomingReg, Reg))
1471 DeadOps.push_back(i);
1475 // Trim unneeded dead operands.
1476 while (!DeadOps.empty()) {
1477 unsigned OpIdx = DeadOps.back();
1478 if (getOperand(OpIdx).isImplicit())
1479 RemoveOperand(OpIdx);
1481 getOperand(OpIdx).setIsDead(false);
1485 // If not found, this means an alias of one of the operands is dead. Add a
1486 // new implicit operand if required.
1487 if (Found || !AddIfNotFound)
1490 addOperand(MachineOperand::CreateReg(IncomingReg,
1498 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1499 const TargetRegisterInfo *RegInfo) {
1500 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1501 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1505 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1506 const MachineOperand &MO = getOperand(i);
1507 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1508 MO.getSubReg() == 0)
1512 addOperand(MachineOperand::CreateReg(IncomingReg,
1517 void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
1518 const TargetRegisterInfo &TRI) {
1519 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1520 MachineOperand &MO = getOperand(i);
1521 if (!MO.isReg() || !MO.isDef()) continue;
1522 unsigned Reg = MO.getReg();
1523 if (Reg == 0) continue;
1525 for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
1526 E = UsedRegs.end(); I != E; ++I)
1527 if (TRI.regsOverlap(*I, Reg)) {
1531 // If there are no uses, including partial uses, the def is dead.
1532 if (Dead) MO.setIsDead();
1537 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1538 unsigned Hash = MI->getOpcode() * 37;
1539 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1540 const MachineOperand &MO = MI->getOperand(i);
1541 uint64_t Key = (uint64_t)MO.getType() << 32;
1542 switch (MO.getType()) {
1544 case MachineOperand::MO_Register:
1545 if (MO.isDef() && MO.getReg() &&
1546 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1547 continue; // Skip virtual register defs.
1550 case MachineOperand::MO_Immediate:
1553 case MachineOperand::MO_FrameIndex:
1554 case MachineOperand::MO_ConstantPoolIndex:
1555 case MachineOperand::MO_JumpTableIndex:
1556 Key |= MO.getIndex();
1558 case MachineOperand::MO_MachineBasicBlock:
1559 Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1561 case MachineOperand::MO_GlobalAddress:
1562 Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1564 case MachineOperand::MO_BlockAddress:
1565 Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1567 case MachineOperand::MO_MCSymbol:
1568 Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1571 Key += ~(Key << 32);
1573 Key += ~(Key << 13);
1577 Key += ~(Key << 27);
1579 Hash = (unsigned)Key + Hash * 37;