1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "llvm/CodeGen/MachineInstr.h"
6 #include "llvm/CodeGen/MachineBasicBlock.h"
7 #include "llvm/Value.h"
8 #include "llvm/Target/TargetMachine.h"
9 #include "llvm/Target/TargetInstrInfo.h"
10 #include "llvm/Target/MRegisterInfo.h"
14 // Global variable holding an array of descriptors for machine instructions.
15 // The actual object needs to be created separately for each target machine.
16 // This variable is initialized and reset by class TargetInstrInfo.
18 // FIXME: This should be a property of the target so that more than one target
19 // at a time can be active...
21 extern const TargetInstrDescriptor *TargetInstrDescriptors;
23 // Constructor for instructions with variable #operands
24 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
27 operands(numOperands, MachineOperand()),
32 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
33 /// not a resize for them. It is expected that if you use this that you call
34 /// add* methods below to fill up the operands, instead of the Set methods.
35 /// Eventually, the "resizing" ctors will be phased out.
37 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
43 operands.reserve(numOperands);
46 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
47 /// MachineInstr is created and added to the end of the specified basic block.
49 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
55 assert(MBB && "Cannot use inserting ctor with null basic block!");
56 operands.reserve(numOperands);
57 MBB->push_back(this); // Add instruction to end of basic block!
61 // OperandComplete - Return true if it's illegal to add a new operand
62 bool MachineInstr::OperandsComplete() const
64 int NumOperands = TargetInstrDescriptors[opCode].numOperands;
65 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
66 return true; // Broken: we have all the operands of this instruction!
72 // Support for replacing opcode and operands of a MachineInstr in place.
73 // This only resets the size of the operand vector and initializes it.
74 // The new operands must be set explicitly later.
76 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
78 assert(getNumImplicitRefs() == 0 &&
79 "This is probably broken because implicit refs are going to be lost.");
82 operands.resize(numOperands, MachineOperand());
86 MachineInstr::SetMachineOperandVal(unsigned i,
87 MachineOperand::MachineOperandType opType,
92 assert(i < operands.size()); // may be explicit or implicit op
93 operands[i].opType = opType;
94 operands[i].value = V;
95 operands[i].regNum = -1;
98 operands[i].flags = MachineOperand::DEFUSEFLAG;
99 else if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
100 operands[i].flags = MachineOperand::DEFONLYFLAG;
102 operands[i].flags = 0;
106 MachineInstr::SetMachineOperandConst(unsigned i,
107 MachineOperand::MachineOperandType operandType,
110 assert(i < getNumOperands()); // must be explicit op
111 assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
112 "immed. constant cannot be defined");
114 operands[i].opType = operandType;
115 operands[i].value = NULL;
116 operands[i].immedVal = intValue;
117 operands[i].regNum = -1;
118 operands[i].flags = 0;
122 MachineInstr::SetMachineOperandReg(unsigned i,
125 assert(i < getNumOperands()); // must be explicit op
127 operands[i].opType = MachineOperand::MO_MachineRegister;
128 operands[i].value = NULL;
129 operands[i].regNum = regNum;
131 if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
132 operands[i].flags = MachineOperand::DEFONLYFLAG;
134 operands[i].flags = 0;
136 insertUsedReg(regNum);
140 MachineInstr::SetRegForOperand(unsigned i, int regNum)
142 assert(i < getNumOperands()); // must be explicit op
143 operands[i].setRegForValue(regNum);
144 insertUsedReg(regNum);
148 MachineInstr::SetRegForImplicitRef(unsigned i, int regNum)
150 getImplicitOp(i).setRegForValue(regNum);
151 insertUsedReg(regNum);
155 // Subsitute all occurrences of Value* oldVal with newVal in all operands
156 // and all implicit refs.
157 // If defsOnly == true, substitute defs only.
159 MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
160 bool defsOnly, bool notDefsAndUses,
161 bool& someArgsWereIgnored)
163 assert((defsOnly || !notDefsAndUses) &&
164 "notDefsAndUses is irrelevant if defsOnly == false.");
166 unsigned numSubst = 0;
168 // Subsitute operands
169 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
172 notDefsAndUses && O.isDefOnly() ||
173 !notDefsAndUses && !O.isUseOnly())
175 O.getMachineOperand().value = newVal;
179 someArgsWereIgnored = true;
181 // Subsitute implicit refs
182 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
183 if (getImplicitRef(i) == oldVal)
185 notDefsAndUses && getImplicitOp(i).opIsDefOnly() ||
186 !notDefsAndUses && !getImplicitOp(i).opIsUse())
188 getImplicitOp(i).value = newVal;
192 someArgsWereIgnored = true;
199 MachineInstr::dump() const
201 cerr << " " << *this;
204 static inline std::ostream&
205 OutputValue(std::ostream &os, const Value* val)
208 os << (void*) val; // print address always
209 if (val && val->hasName())
210 os << " " << val->getName() << ")"; // print name also, if available
214 static inline void OutputReg(std::ostream &os, unsigned RegNo,
215 const MRegisterInfo *MRI = 0) {
217 if (RegNo < MRegisterInfo::FirstVirtualRegister)
218 os << "%" << MRI->get(RegNo).Name;
220 os << "%reg" << RegNo;
222 os << "%mreg(" << RegNo << ")";
225 static void print(const MachineOperand &MO, std::ostream &OS,
226 const TargetMachine &TM) {
227 const MRegisterInfo *MRI = TM.getRegisterInfo();
228 bool CloseParen = true;
231 else if (MO.opLoBits32())
233 else if (MO.opHiBits64())
235 else if (MO.opLoBits64())
240 switch (MO.getType()) {
241 case MachineOperand::MO_VirtualRegister:
242 if (MO.getVRegValue()) {
244 OutputValue(OS, MO.getVRegValue());
245 if (MO.hasAllocatedReg())
248 if (MO.hasAllocatedReg())
249 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
251 case MachineOperand::MO_CCRegister:
253 OutputValue(OS, MO.getVRegValue());
254 if (MO.hasAllocatedReg()) {
256 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
259 case MachineOperand::MO_MachineRegister:
260 OutputReg(OS, MO.getMachineRegNum(), MRI);
262 case MachineOperand::MO_SignExtendedImmed:
263 OS << (long)MO.getImmedValue();
265 case MachineOperand::MO_UnextendedImmed:
266 OS << (long)MO.getImmedValue();
268 case MachineOperand::MO_PCRelativeDisp: {
269 const Value* opVal = MO.getVRegValue();
270 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
271 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
272 if (opVal->hasName())
273 OS << opVal->getName();
275 OS << (const void*) opVal;
279 case MachineOperand::MO_MachineBasicBlock:
281 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
282 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
284 case MachineOperand::MO_FrameIndex:
285 OS << "<fi#" << MO.getFrameIndex() << ">";
287 case MachineOperand::MO_ConstantPoolIndex:
288 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
290 case MachineOperand::MO_GlobalAddress:
291 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
293 case MachineOperand::MO_ExternalSymbol:
294 OS << "<es:" << MO.getSymbolName() << ">";
297 assert(0 && "Unrecognized operand type");
304 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
305 unsigned StartOp = 0;
307 // Specialize printing if op#0 is definition
308 if (getNumOperands() &&
309 (getOperand(0).opIsDefOnly() || getOperand(0).opIsDefAndUse())) {
310 ::print(getOperand(0), OS, TM);
312 ++StartOp; // Don't print this operand again!
314 OS << TM.getInstrInfo().getName(getOpcode());
316 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
317 const MachineOperand& mop = getOperand(i);
321 ::print(mop, OS, TM);
323 if (mop.opIsDefAndUse())
325 else if (mop.opIsDefOnly())
329 // code for printing implict references
330 if (getNumImplicitRefs()) {
331 OS << "\tImplicitRefs: ";
332 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
334 OutputValue(OS, getImplicitRef(i));
335 if (getImplicitOp(i).opIsDefAndUse())
337 else if (getImplicitOp(i).opIsDefOnly())
346 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
348 os << TargetInstrDescriptors[MI.opCode].Name;
350 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
351 os << "\t" << MI.getOperand(i);
352 if (MI.getOperand(i).opIsDefOnly())
354 if (MI.getOperand(i).opIsDefAndUse())
358 // code for printing implict references
359 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
360 if (NumOfImpRefs > 0) {
361 os << "\tImplicit: ";
362 for (unsigned z=0; z < NumOfImpRefs; z++) {
363 OutputValue(os, MI.getImplicitRef(z));
364 if (MI.getImplicitOp(z).opIsDefOnly()) os << "<d>";
365 if (MI.getImplicitOp(z).opIsDefAndUse()) os << "<d&u>";
373 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
377 else if (MO.opLoBits32())
379 else if (MO.opHiBits64())
381 else if (MO.opLoBits64())
384 switch (MO.getType())
386 case MachineOperand::MO_VirtualRegister:
387 if (MO.hasAllocatedReg())
388 OutputReg(OS, MO.getAllocatedRegNum());
390 if (MO.getVRegValue()) {
391 if (MO.hasAllocatedReg()) OS << "==";
393 OutputValue(OS, MO.getVRegValue());
396 case MachineOperand::MO_CCRegister:
398 OutputValue(OS, MO.getVRegValue());
399 if (MO.hasAllocatedReg()) {
401 OutputReg(OS, MO.getAllocatedRegNum());
404 case MachineOperand::MO_MachineRegister:
405 OutputReg(OS, MO.getMachineRegNum());
407 case MachineOperand::MO_SignExtendedImmed:
408 OS << (long)MO.getImmedValue();
410 case MachineOperand::MO_UnextendedImmed:
411 OS << (long)MO.getImmedValue();
413 case MachineOperand::MO_PCRelativeDisp:
415 const Value* opVal = MO.getVRegValue();
416 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
417 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
418 if (opVal->hasName())
419 OS << opVal->getName();
421 OS << (const void*) opVal;
425 case MachineOperand::MO_MachineBasicBlock:
427 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
428 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
430 case MachineOperand::MO_FrameIndex:
431 OS << "<fi#" << MO.getFrameIndex() << ">";
433 case MachineOperand::MO_ConstantPoolIndex:
434 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
436 case MachineOperand::MO_GlobalAddress:
437 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
439 case MachineOperand::MO_ExternalSymbol:
440 OS << "<es:" << MO.getSymbolName() << ">";
443 assert(0 && "Unrecognized operand type");
448 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
449 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))