1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "llvm/CodeGen/MachineInstr.h"
6 #include "llvm/CodeGen/MachineBasicBlock.h"
7 #include "llvm/Value.h"
8 #include "llvm/Target/TargetMachine.h"
9 #include "llvm/Target/TargetInstrInfo.h"
10 #include "llvm/Target/MRegisterInfo.h"
12 // Global variable holding an array of descriptors for machine instructions.
13 // The actual object needs to be created separately for each target machine.
14 // This variable is initialized and reset by class TargetInstrInfo.
16 // FIXME: This should be a property of the target so that more than one target
17 // at a time can be active...
19 extern const TargetInstrDescriptor *TargetInstrDescriptors;
21 // Constructor for instructions with variable #operands
22 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
25 operands(numOperands, MachineOperand()),
30 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
31 /// not a resize for them. It is expected that if you use this that you call
32 /// add* methods below to fill up the operands, instead of the Set methods.
33 /// Eventually, the "resizing" ctors will be phased out.
35 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
41 operands.reserve(numOperands);
44 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
45 /// MachineInstr is created and added to the end of the specified basic block.
47 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
53 assert(MBB && "Cannot use inserting ctor with null basic block!");
54 operands.reserve(numOperands);
55 MBB->push_back(this); // Add instruction to end of basic block!
59 // OperandComplete - Return true if it's illegal to add a new operand
60 bool MachineInstr::OperandsComplete() const
62 int NumOperands = TargetInstrDescriptors[opCode].numOperands;
63 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
64 return true; // Broken: we have all the operands of this instruction!
70 // Support for replacing opcode and operands of a MachineInstr in place.
71 // This only resets the size of the operand vector and initializes it.
72 // The new operands must be set explicitly later.
74 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
76 assert(getNumImplicitRefs() == 0 &&
77 "This is probably broken because implicit refs are going to be lost.");
80 operands.resize(numOperands, MachineOperand());
83 void MachineInstr::SetMachineOperandVal(unsigned i,
84 MachineOperand::MachineOperandType opTy,
86 assert(i < operands.size()); // may be explicit or implicit op
87 operands[i].opType = opTy;
88 operands[i].value = V;
89 operands[i].regNum = -1;
93 MachineInstr::SetMachineOperandConst(unsigned i,
94 MachineOperand::MachineOperandType operandType,
97 assert(i < getNumOperands()); // must be explicit op
98 assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
99 "immed. constant cannot be defined");
101 operands[i].opType = operandType;
102 operands[i].value = NULL;
103 operands[i].immedVal = intValue;
104 operands[i].regNum = -1;
105 operands[i].flags = 0;
108 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
109 assert(i < getNumOperands()); // must be explicit op
111 operands[i].opType = MachineOperand::MO_MachineRegister;
112 operands[i].value = NULL;
113 operands[i].regNum = regNum;
117 MachineInstr::SetRegForOperand(unsigned i, int regNum)
119 assert(i < getNumOperands()); // must be explicit op
120 operands[i].setRegForValue(regNum);
124 MachineInstr::SetRegForImplicitRef(unsigned i, int regNum)
126 getImplicitOp(i).setRegForValue(regNum);
130 // Substitute all occurrences of Value* oldVal with newVal in all operands
131 // and all implicit refs.
132 // If defsOnly == true, substitute defs only.
134 MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
135 bool defsOnly, bool notDefsAndUses,
136 bool& someArgsWereIgnored)
138 assert((!defsOnly || !notDefsAndUses) &&
139 "notDefsAndUses is irrelevant if defsOnly == true.");
141 unsigned numSubst = 0;
143 // Substitute operands
144 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
147 notDefsAndUses && O.isDefOnly() ||
148 !notDefsAndUses && !O.isUseOnly())
150 O.getMachineOperand().value = newVal;
154 someArgsWereIgnored = true;
156 // Substitute implicit refs
157 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
158 if (getImplicitRef(i) == oldVal)
160 notDefsAndUses && getImplicitOp(i).opIsDefOnly() ||
161 !notDefsAndUses && !getImplicitOp(i).opIsUse())
163 getImplicitOp(i).value = newVal;
167 someArgsWereIgnored = true;
174 MachineInstr::dump() const
176 std::cerr << " " << *this;
179 static inline std::ostream&
180 OutputValue(std::ostream &os, const Value* val)
183 os << (void*) val; // print address always
184 if (val && val->hasName())
185 os << " " << val->getName() << ")"; // print name also, if available
189 static inline void OutputReg(std::ostream &os, unsigned RegNo,
190 const MRegisterInfo *MRI = 0) {
192 if (RegNo < MRegisterInfo::FirstVirtualRegister)
193 os << "%" << MRI->get(RegNo).Name;
195 os << "%reg" << RegNo;
197 os << "%mreg(" << RegNo << ")";
200 static void print(const MachineOperand &MO, std::ostream &OS,
201 const TargetMachine &TM) {
202 const MRegisterInfo *MRI = TM.getRegisterInfo();
203 bool CloseParen = true;
206 else if (MO.opLoBits32())
208 else if (MO.opHiBits64())
210 else if (MO.opLoBits64())
215 switch (MO.getType()) {
216 case MachineOperand::MO_VirtualRegister:
217 if (MO.getVRegValue()) {
219 OutputValue(OS, MO.getVRegValue());
220 if (MO.hasAllocatedReg())
223 if (MO.hasAllocatedReg())
224 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
226 case MachineOperand::MO_CCRegister:
228 OutputValue(OS, MO.getVRegValue());
229 if (MO.hasAllocatedReg()) {
231 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
234 case MachineOperand::MO_MachineRegister:
235 OutputReg(OS, MO.getMachineRegNum(), MRI);
237 case MachineOperand::MO_SignExtendedImmed:
238 OS << (long)MO.getImmedValue();
240 case MachineOperand::MO_UnextendedImmed:
241 OS << (long)MO.getImmedValue();
243 case MachineOperand::MO_PCRelativeDisp: {
244 const Value* opVal = MO.getVRegValue();
245 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
246 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
247 if (opVal->hasName())
248 OS << opVal->getName();
250 OS << (const void*) opVal;
254 case MachineOperand::MO_MachineBasicBlock:
256 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
257 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
259 case MachineOperand::MO_FrameIndex:
260 OS << "<fi#" << MO.getFrameIndex() << ">";
262 case MachineOperand::MO_ConstantPoolIndex:
263 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
265 case MachineOperand::MO_GlobalAddress:
266 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
268 case MachineOperand::MO_ExternalSymbol:
269 OS << "<es:" << MO.getSymbolName() << ">";
272 assert(0 && "Unrecognized operand type");
279 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
280 unsigned StartOp = 0;
282 // Specialize printing if op#0 is definition
283 if (getNumOperands() &&
284 (getOperand(0).opIsDefOnly() || getOperand(0).opIsDefAndUse())) {
285 ::print(getOperand(0), OS, TM);
287 ++StartOp; // Don't print this operand again!
289 OS << TM.getInstrInfo().getName(getOpcode());
291 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
292 const MachineOperand& mop = getOperand(i);
296 ::print(mop, OS, TM);
298 if (mop.opIsDefAndUse())
300 else if (mop.opIsDefOnly())
304 // code for printing implicit references
305 if (getNumImplicitRefs()) {
306 OS << "\tImplicitRefs: ";
307 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
309 OutputValue(OS, getImplicitRef(i));
310 if (getImplicitOp(i).opIsDefAndUse())
312 else if (getImplicitOp(i).opIsDefOnly())
321 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
323 os << TargetInstrDescriptors[MI.opCode].Name;
325 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
326 os << "\t" << MI.getOperand(i);
327 if (MI.getOperand(i).opIsDefOnly())
329 if (MI.getOperand(i).opIsDefAndUse())
333 // code for printing implicit references
334 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
335 if (NumOfImpRefs > 0) {
336 os << "\tImplicit: ";
337 for (unsigned z=0; z < NumOfImpRefs; z++) {
338 OutputValue(os, MI.getImplicitRef(z));
339 if (MI.getImplicitOp(z).opIsDefOnly()) os << "<d>";
340 if (MI.getImplicitOp(z).opIsDefAndUse()) os << "<d&u>";
348 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
352 else if (MO.opLoBits32())
354 else if (MO.opHiBits64())
356 else if (MO.opLoBits64())
359 switch (MO.getType())
361 case MachineOperand::MO_VirtualRegister:
362 if (MO.hasAllocatedReg())
363 OutputReg(OS, MO.getAllocatedRegNum());
365 if (MO.getVRegValue()) {
366 if (MO.hasAllocatedReg()) OS << "==";
368 OutputValue(OS, MO.getVRegValue());
371 case MachineOperand::MO_CCRegister:
373 OutputValue(OS, MO.getVRegValue());
374 if (MO.hasAllocatedReg()) {
376 OutputReg(OS, MO.getAllocatedRegNum());
379 case MachineOperand::MO_MachineRegister:
380 OutputReg(OS, MO.getMachineRegNum());
382 case MachineOperand::MO_SignExtendedImmed:
383 OS << (long)MO.getImmedValue();
385 case MachineOperand::MO_UnextendedImmed:
386 OS << (long)MO.getImmedValue();
388 case MachineOperand::MO_PCRelativeDisp:
390 const Value* opVal = MO.getVRegValue();
391 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
392 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
393 if (opVal->hasName())
394 OS << opVal->getName();
396 OS << (const void*) opVal;
400 case MachineOperand::MO_MachineBasicBlock:
402 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
403 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
405 case MachineOperand::MO_FrameIndex:
406 OS << "<fi#" << MO.getFrameIndex() << ">";
408 case MachineOperand::MO_ConstantPoolIndex:
409 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
411 case MachineOperand::MO_GlobalAddress:
412 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
414 case MachineOperand::MO_ExternalSymbol:
415 OS << "<es:" << MO.getSymbolName() << ">";
418 assert(0 && "Unrecognized operand type");
423 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
424 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))