1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/InlineAsm.h"
17 #include "llvm/Value.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetInstrDesc.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Analysis/DebugInfo.h"
26 #include "llvm/Support/LeakDetector.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/Streams.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/ADT/FoldingSet.h"
33 //===----------------------------------------------------------------------===//
34 // MachineOperand Implementation
35 //===----------------------------------------------------------------------===//
37 /// AddRegOperandToRegInfo - Add this register operand to the specified
38 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
39 /// explicitly nulled out.
40 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
41 assert(isReg() && "Can only add reg operand to use lists");
43 // If the reginfo pointer is null, just explicitly null out or next/prev
44 // pointers, to ensure they are not garbage.
46 Contents.Reg.Prev = 0;
47 Contents.Reg.Next = 0;
51 // Otherwise, add this operand to the head of the registers use/def list.
52 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
54 // For SSA values, we prefer to keep the definition at the start of the list.
55 // we do this by skipping over the definition if it is at the head of the
57 if (*Head && (*Head)->isDef())
58 Head = &(*Head)->Contents.Reg.Next;
60 Contents.Reg.Next = *Head;
61 if (Contents.Reg.Next) {
62 assert(getReg() == Contents.Reg.Next->getReg() &&
63 "Different regs on the same list!");
64 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
67 Contents.Reg.Prev = Head;
71 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
72 /// MachineRegisterInfo it is linked with.
73 void MachineOperand::RemoveRegOperandFromRegInfo() {
74 assert(isOnRegUseList() && "Reg operand is not on a use list");
75 // Unlink this from the doubly linked list of operands.
76 MachineOperand *NextOp = Contents.Reg.Next;
77 *Contents.Reg.Prev = NextOp;
79 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
80 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
82 Contents.Reg.Prev = 0;
83 Contents.Reg.Next = 0;
86 void MachineOperand::setReg(unsigned Reg) {
87 if (getReg() == Reg) return; // No change.
89 // Otherwise, we have to change the register. If this operand is embedded
90 // into a machine function, we need to update the old and new register's
92 if (MachineInstr *MI = getParent())
93 if (MachineBasicBlock *MBB = MI->getParent())
94 if (MachineFunction *MF = MBB->getParent()) {
95 RemoveRegOperandFromRegInfo();
96 Contents.Reg.RegNo = Reg;
97 AddRegOperandToRegInfo(&MF->getRegInfo());
101 // Otherwise, just change the register, no problem. :)
102 Contents.Reg.RegNo = Reg;
105 /// ChangeToImmediate - Replace this operand with a new immediate operand of
106 /// the specified value. If an operand is known to be an immediate already,
107 /// the setImm method should be used.
108 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
109 // If this operand is currently a register operand, and if this is in a
110 // function, deregister the operand from the register's use/def list.
111 if (isReg() && getParent() && getParent()->getParent() &&
112 getParent()->getParent()->getParent())
113 RemoveRegOperandFromRegInfo();
115 OpKind = MO_Immediate;
116 Contents.ImmVal = ImmVal;
119 /// ChangeToRegister - Replace this operand with a new register operand of
120 /// the specified value. If an operand is known to be an register already,
121 /// the setReg method should be used.
122 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
123 bool isKill, bool isDead) {
124 // If this operand is already a register operand, use setReg to update the
125 // register's use/def lists.
127 assert(!isEarlyClobber());
130 // Otherwise, change this to a register and set the reg#.
131 OpKind = MO_Register;
132 Contents.Reg.RegNo = Reg;
134 // If this operand is embedded in a function, add the operand to the
135 // register's use/def list.
136 if (MachineInstr *MI = getParent())
137 if (MachineBasicBlock *MBB = MI->getParent())
138 if (MachineFunction *MF = MBB->getParent())
139 AddRegOperandToRegInfo(&MF->getRegInfo());
146 IsEarlyClobber = false;
150 /// isIdenticalTo - Return true if this operand is identical to the specified
152 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
153 if (getType() != Other.getType() ||
154 getTargetFlags() != Other.getTargetFlags())
158 default: assert(0 && "Unrecognized operand type");
159 case MachineOperand::MO_Register:
160 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
161 getSubReg() == Other.getSubReg();
162 case MachineOperand::MO_Immediate:
163 return getImm() == Other.getImm();
164 case MachineOperand::MO_FPImmediate:
165 return getFPImm() == Other.getFPImm();
166 case MachineOperand::MO_MachineBasicBlock:
167 return getMBB() == Other.getMBB();
168 case MachineOperand::MO_FrameIndex:
169 return getIndex() == Other.getIndex();
170 case MachineOperand::MO_ConstantPoolIndex:
171 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
172 case MachineOperand::MO_JumpTableIndex:
173 return getIndex() == Other.getIndex();
174 case MachineOperand::MO_GlobalAddress:
175 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
176 case MachineOperand::MO_ExternalSymbol:
177 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
178 getOffset() == Other.getOffset();
182 /// print - Print the specified machine operand.
184 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
185 raw_os_ostream RawOS(OS);
189 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
191 case MachineOperand::MO_Register:
192 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
193 OS << "%reg" << getReg();
195 // If the instruction is embedded into a basic block, we can find the
196 // target info for the instruction.
198 if (const MachineInstr *MI = getParent())
199 if (const MachineBasicBlock *MBB = MI->getParent())
200 if (const MachineFunction *MF = MBB->getParent())
201 TM = &MF->getTarget();
204 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
206 OS << "%mreg" << getReg();
209 if (getSubReg() != 0) {
210 OS << ':' << getSubReg();
213 if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) {
215 bool NeedComma = false;
217 if (NeedComma) OS << ',';
218 OS << (isDef() ? "imp-def" : "imp-use");
220 } else if (isDef()) {
221 if (NeedComma) OS << ',';
222 if (isEarlyClobber())
223 OS << "earlyclobber,";
227 if (isKill() || isDead()) {
228 if (NeedComma) OS << ',';
229 if (isKill()) OS << "kill";
230 if (isDead()) OS << "dead";
235 case MachineOperand::MO_Immediate:
238 case MachineOperand::MO_FPImmediate:
239 if (getFPImm()->getType() == Type::FloatTy)
240 OS << getFPImm()->getValueAPF().convertToFloat();
242 OS << getFPImm()->getValueAPF().convertToDouble();
244 case MachineOperand::MO_MachineBasicBlock:
246 << ((Value*)getMBB()->getBasicBlock())->getName()
247 << "," << (void*)getMBB() << '>';
249 case MachineOperand::MO_FrameIndex:
250 OS << "<fi#" << getIndex() << '>';
252 case MachineOperand::MO_ConstantPoolIndex:
253 OS << "<cp#" << getIndex();
254 if (getOffset()) OS << "+" << getOffset();
257 case MachineOperand::MO_JumpTableIndex:
258 OS << "<jt#" << getIndex() << '>';
260 case MachineOperand::MO_GlobalAddress:
261 OS << "<ga:" << ((Value*)getGlobal())->getName();
262 if (getOffset()) OS << "+" << getOffset();
265 case MachineOperand::MO_ExternalSymbol:
266 OS << "<es:" << getSymbolName();
267 if (getOffset()) OS << "+" << getOffset();
271 assert(0 && "Unrecognized operand type");
274 if (unsigned TF = getTargetFlags())
275 OS << "[TF=" << TF << ']';
278 //===----------------------------------------------------------------------===//
279 // MachineMemOperand Implementation
280 //===----------------------------------------------------------------------===//
282 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
283 int64_t o, uint64_t s, unsigned int a)
284 : Offset(o), Size(s), V(v),
285 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
286 assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
287 assert((isLoad() || isStore()) && "Not a load/store!");
290 /// Profile - Gather unique data for the object.
292 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
293 ID.AddInteger(Offset);
296 ID.AddInteger(Flags);
299 //===----------------------------------------------------------------------===//
300 // MachineInstr Implementation
301 //===----------------------------------------------------------------------===//
303 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
304 /// TID NULL and no operands.
305 MachineInstr::MachineInstr()
306 : TID(0), NumImplicitOps(0), Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
307 // Make sure that we get added to a machine basicblock
308 LeakDetector::addGarbageObject(this);
311 void MachineInstr::addImplicitDefUseOperands() {
312 if (TID->ImplicitDefs)
313 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
314 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
315 if (TID->ImplicitUses)
316 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
317 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
320 /// MachineInstr ctor - This constructor create a MachineInstr and add the
321 /// implicit operands. It reserves space for number of operands specified by
322 /// TargetInstrDesc or the numOperands if it is not zero. (for
323 /// instructions with variable number of operands).
324 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
325 : TID(&tid), NumImplicitOps(0), Parent(0),
326 debugLoc(DebugLoc::getUnknownLoc()) {
327 if (!NoImp && TID->getImplicitDefs())
328 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
330 if (!NoImp && TID->getImplicitUses())
331 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
333 Operands.reserve(NumImplicitOps + TID->getNumOperands());
335 addImplicitDefUseOperands();
336 // Make sure that we get added to a machine basicblock
337 LeakDetector::addGarbageObject(this);
340 /// MachineInstr ctor - As above, but with a DebugLoc.
341 MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
343 : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
344 if (!NoImp && TID->getImplicitDefs())
345 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
347 if (!NoImp && TID->getImplicitUses())
348 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
350 Operands.reserve(NumImplicitOps + TID->getNumOperands());
352 addImplicitDefUseOperands();
353 // Make sure that we get added to a machine basicblock
354 LeakDetector::addGarbageObject(this);
357 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
358 /// that the MachineInstr is created and added to the end of the specified
361 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
362 : TID(&tid), NumImplicitOps(0), Parent(0),
363 debugLoc(DebugLoc::getUnknownLoc()) {
364 assert(MBB && "Cannot use inserting ctor with null basic block!");
365 if (TID->ImplicitDefs)
366 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
368 if (TID->ImplicitUses)
369 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
371 Operands.reserve(NumImplicitOps + TID->getNumOperands());
372 addImplicitDefUseOperands();
373 // Make sure that we get added to a machine basicblock
374 LeakDetector::addGarbageObject(this);
375 MBB->push_back(this); // Add instruction to end of basic block!
378 /// MachineInstr ctor - As above, but with a DebugLoc.
380 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
381 const TargetInstrDesc &tid)
382 : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
383 assert(MBB && "Cannot use inserting ctor with null basic block!");
384 if (TID->ImplicitDefs)
385 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
387 if (TID->ImplicitUses)
388 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
390 Operands.reserve(NumImplicitOps + TID->getNumOperands());
391 addImplicitDefUseOperands();
392 // Make sure that we get added to a machine basicblock
393 LeakDetector::addGarbageObject(this);
394 MBB->push_back(this); // Add instruction to end of basic block!
397 /// MachineInstr ctor - Copies MachineInstr arg exactly
399 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
400 : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0),
401 debugLoc(MI.getDebugLoc()) {
402 Operands.reserve(MI.getNumOperands());
405 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
406 addOperand(MI.getOperand(i));
407 NumImplicitOps = MI.NumImplicitOps;
409 // Add memory operands.
410 for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
411 j = MI.memoperands_end(); i != j; ++i)
412 addMemOperand(MF, *i);
414 // Set parent to null.
417 LeakDetector::addGarbageObject(this);
420 MachineInstr::~MachineInstr() {
421 LeakDetector::removeGarbageObject(this);
422 assert(MemOperands.empty() &&
423 "MachineInstr being deleted with live memoperands!");
425 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
426 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
427 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
428 "Reg operand def/use list corrupted");
433 /// getRegInfo - If this instruction is embedded into a MachineFunction,
434 /// return the MachineRegisterInfo object for the current function, otherwise
436 MachineRegisterInfo *MachineInstr::getRegInfo() {
437 if (MachineBasicBlock *MBB = getParent())
438 return &MBB->getParent()->getRegInfo();
442 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
443 /// this instruction from their respective use lists. This requires that the
444 /// operands already be on their use lists.
445 void MachineInstr::RemoveRegOperandsFromUseLists() {
446 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
447 if (Operands[i].isReg())
448 Operands[i].RemoveRegOperandFromRegInfo();
452 /// AddRegOperandsToUseLists - Add all of the register operands in
453 /// this instruction from their respective use lists. This requires that the
454 /// operands not be on their use lists yet.
455 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
456 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
457 if (Operands[i].isReg())
458 Operands[i].AddRegOperandToRegInfo(&RegInfo);
463 /// addOperand - Add the specified operand to the instruction. If it is an
464 /// implicit operand, it is added to the end of the operand list. If it is
465 /// an explicit operand it is added at the end of the explicit operand list
466 /// (before the first implicit operand).
467 void MachineInstr::addOperand(const MachineOperand &Op) {
468 bool isImpReg = Op.isReg() && Op.isImplicit();
469 assert((isImpReg || !OperandsComplete()) &&
470 "Trying to add an operand to a machine instr that is already done!");
472 MachineRegisterInfo *RegInfo = getRegInfo();
474 // If we are adding the operand to the end of the list, our job is simpler.
475 // This is true most of the time, so this is a reasonable optimization.
476 if (isImpReg || NumImplicitOps == 0) {
477 // We can only do this optimization if we know that the operand list won't
479 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
480 Operands.push_back(Op);
482 // Set the parent of the operand.
483 Operands.back().ParentMI = this;
485 // If the operand is a register, update the operand's use list.
487 Operands.back().AddRegOperandToRegInfo(RegInfo);
492 // Otherwise, we have to insert a real operand before any implicit ones.
493 unsigned OpNo = Operands.size()-NumImplicitOps;
495 // If this instruction isn't embedded into a function, then we don't need to
496 // update any operand lists.
498 // Simple insertion, no reginfo update needed for other register operands.
499 Operands.insert(Operands.begin()+OpNo, Op);
500 Operands[OpNo].ParentMI = this;
502 // Do explicitly set the reginfo for this operand though, to ensure the
503 // next/prev fields are properly nulled out.
504 if (Operands[OpNo].isReg())
505 Operands[OpNo].AddRegOperandToRegInfo(0);
507 } else if (Operands.size()+1 <= Operands.capacity()) {
508 // Otherwise, we have to remove register operands from their register use
509 // list, add the operand, then add the register operands back to their use
510 // list. This also must handle the case when the operand list reallocates
511 // to somewhere else.
513 // If insertion of this operand won't cause reallocation of the operand
514 // list, just remove the implicit operands, add the operand, then re-add all
515 // the rest of the operands.
516 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
517 assert(Operands[i].isReg() && "Should only be an implicit reg!");
518 Operands[i].RemoveRegOperandFromRegInfo();
521 // Add the operand. If it is a register, add it to the reg list.
522 Operands.insert(Operands.begin()+OpNo, Op);
523 Operands[OpNo].ParentMI = this;
525 if (Operands[OpNo].isReg())
526 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
528 // Re-add all the implicit ops.
529 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
530 assert(Operands[i].isReg() && "Should only be an implicit reg!");
531 Operands[i].AddRegOperandToRegInfo(RegInfo);
534 // Otherwise, we will be reallocating the operand list. Remove all reg
535 // operands from their list, then readd them after the operand list is
537 RemoveRegOperandsFromUseLists();
539 Operands.insert(Operands.begin()+OpNo, Op);
540 Operands[OpNo].ParentMI = this;
542 // Re-add all the operands.
543 AddRegOperandsToUseLists(*RegInfo);
547 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
548 /// fewer operand than it started with.
550 void MachineInstr::RemoveOperand(unsigned OpNo) {
551 assert(OpNo < Operands.size() && "Invalid operand number");
553 // Special case removing the last one.
554 if (OpNo == Operands.size()-1) {
555 // If needed, remove from the reg def/use list.
556 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
557 Operands.back().RemoveRegOperandFromRegInfo();
563 // Otherwise, we are removing an interior operand. If we have reginfo to
564 // update, remove all operands that will be shifted down from their reg lists,
565 // move everything down, then re-add them.
566 MachineRegisterInfo *RegInfo = getRegInfo();
568 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
569 if (Operands[i].isReg())
570 Operands[i].RemoveRegOperandFromRegInfo();
574 Operands.erase(Operands.begin()+OpNo);
577 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
578 if (Operands[i].isReg())
579 Operands[i].AddRegOperandToRegInfo(RegInfo);
584 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
585 /// referencing arbitrary storage.
586 void MachineInstr::addMemOperand(MachineFunction &MF,
587 const MachineMemOperand &MO) {
588 MemOperands.push_back(MO);
591 /// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
592 void MachineInstr::clearMemOperands(MachineFunction &MF) {
597 /// removeFromParent - This method unlinks 'this' from the containing basic
598 /// block, and returns it, but does not delete it.
599 MachineInstr *MachineInstr::removeFromParent() {
600 assert(getParent() && "Not embedded in a basic block!");
601 getParent()->remove(this);
606 /// eraseFromParent - This method unlinks 'this' from the containing basic
607 /// block, and deletes it.
608 void MachineInstr::eraseFromParent() {
609 assert(getParent() && "Not embedded in a basic block!");
610 getParent()->erase(this);
614 /// OperandComplete - Return true if it's illegal to add a new operand
616 bool MachineInstr::OperandsComplete() const {
617 unsigned short NumOperands = TID->getNumOperands();
618 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
619 return true; // Broken: we have all the operands of this instruction!
623 /// getNumExplicitOperands - Returns the number of non-implicit operands.
625 unsigned MachineInstr::getNumExplicitOperands() const {
626 unsigned NumOperands = TID->getNumOperands();
627 if (!TID->isVariadic())
630 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
631 const MachineOperand &MO = getOperand(i);
632 if (!MO.isReg() || !MO.isImplicit())
639 /// isLabel - Returns true if the MachineInstr represents a label.
641 bool MachineInstr::isLabel() const {
642 return getOpcode() == TargetInstrInfo::DBG_LABEL ||
643 getOpcode() == TargetInstrInfo::EH_LABEL ||
644 getOpcode() == TargetInstrInfo::GC_LABEL;
647 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
649 bool MachineInstr::isDebugLabel() const {
650 return getOpcode() == TargetInstrInfo::DBG_LABEL;
653 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
654 /// the specific register or -1 if it is not found. It further tightening
655 /// the search criteria to a use that kills the register if isKill is true.
656 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
657 const TargetRegisterInfo *TRI) const {
658 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
659 const MachineOperand &MO = getOperand(i);
660 if (!MO.isReg() || !MO.isUse())
662 unsigned MOReg = MO.getReg();
667 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
668 TargetRegisterInfo::isPhysicalRegister(Reg) &&
669 TRI->isSubRegister(MOReg, Reg)))
670 if (!isKill || MO.isKill())
676 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
677 /// the specified register or -1 if it is not found. If isDead is true, defs
678 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
679 /// also checks if there is a def of a super-register.
680 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
681 const TargetRegisterInfo *TRI) const {
682 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
683 const MachineOperand &MO = getOperand(i);
684 if (!MO.isReg() || !MO.isDef())
686 unsigned MOReg = MO.getReg();
689 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
690 TargetRegisterInfo::isPhysicalRegister(Reg) &&
691 TRI->isSubRegister(MOReg, Reg)))
692 if (!isDead || MO.isDead())
698 /// findFirstPredOperandIdx() - Find the index of the first operand in the
699 /// operand list that is used to represent the predicate. It returns -1 if
701 int MachineInstr::findFirstPredOperandIdx() const {
702 const TargetInstrDesc &TID = getDesc();
703 if (TID.isPredicable()) {
704 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
705 if (TID.OpInfo[i].isPredicate())
712 /// isRegTiedToUseOperand - Given the index of a register def operand,
713 /// check if the register def is tied to a source operand, due to either
714 /// two-address elimination or inline assembly constraints. Returns the
715 /// first tied use operand index by reference is UseOpIdx is not null.
717 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
718 if (getOpcode() == TargetInstrInfo::INLINEASM) {
719 assert(DefOpIdx >= 2);
720 const MachineOperand &MO = getOperand(DefOpIdx);
721 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
723 // Determine the actual operand index that corresponds to this index.
725 unsigned DefPart = 0;
726 for (unsigned i = 1, e = getNumOperands(); i < e; ) {
727 const MachineOperand &FMO = getOperand(i);
729 // Skip over this def.
730 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
731 unsigned PrevDef = i + 1;
732 i = PrevDef + NumOps;
734 DefPart = DefOpIdx - PrevDef;
739 for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
740 const MachineOperand &FMO = getOperand(i);
743 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
746 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
749 *UseOpIdx = (unsigned)i + 1 + DefPart;
756 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
757 const TargetInstrDesc &TID = getDesc();
758 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
759 const MachineOperand &MO = getOperand(i);
760 if (MO.isReg() && MO.isUse() &&
761 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
763 *UseOpIdx = (unsigned)i;
770 /// isRegTiedToDefOperand - Return true if the operand of the specified index
771 /// is a register use and it is tied to an def operand. It also returns the def
772 /// operand index by reference.
774 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
775 if (getOpcode() == TargetInstrInfo::INLINEASM) {
776 const MachineOperand &MO = getOperand(UseOpIdx);
777 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
779 int FlagIdx = UseOpIdx - 1;
782 while (!getOperand(FlagIdx).isImm()) {
786 const MachineOperand &UFMO = getOperand(FlagIdx);
787 if (FlagIdx + InlineAsm::getNumOperandRegisters(UFMO.getImm()) < UseOpIdx)
790 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
795 // Remember to adjust the index. First operand is asm string, then there
796 // is a flag for each.
798 const MachineOperand &FMO = getOperand(DefIdx);
800 // Skip over this def.
801 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
804 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
810 const TargetInstrDesc &TID = getDesc();
811 if (UseOpIdx >= TID.getNumOperands())
813 const MachineOperand &MO = getOperand(UseOpIdx);
814 if (!MO.isReg() || !MO.isUse())
816 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
820 *DefOpIdx = (unsigned)DefIdx;
824 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
826 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
827 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
828 const MachineOperand &MO = MI->getOperand(i);
829 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
831 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
832 MachineOperand &MOp = getOperand(j);
833 if (!MOp.isIdenticalTo(MO))
844 /// copyPredicates - Copies predicate operand(s) from MI.
845 void MachineInstr::copyPredicates(const MachineInstr *MI) {
846 const TargetInstrDesc &TID = MI->getDesc();
847 if (!TID.isPredicable())
849 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
850 if (TID.OpInfo[i].isPredicate()) {
851 // Predicated operands must be last operands.
852 addOperand(MI->getOperand(i));
857 /// isSafeToMove - Return true if it is safe to move this instruction. If
858 /// SawStore is set to true, it means that there is a store (or call) between
859 /// the instruction's location and its intended destination.
860 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
861 bool &SawStore) const {
862 // Ignore stuff that we obviously can't move.
863 if (TID->mayStore() || TID->isCall()) {
867 if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
870 // See if this instruction does a load. If so, we have to guarantee that the
871 // loaded value doesn't change between the load and the its intended
872 // destination. The check for isInvariantLoad gives the targe the chance to
873 // classify the load as always returning a constant, e.g. a constant pool
875 if (TID->mayLoad() && !TII->isInvariantLoad(this))
876 // Otherwise, this is a real load. If there is a store between the load and
877 // end of block, or if the laod is volatile, we can't move it.
878 return !SawStore && !hasVolatileMemoryRef();
883 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
884 /// instruction which defined the specified register instead of copying it.
885 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
886 unsigned DstReg) const {
887 bool SawStore = false;
888 if (!getDesc().isRematerializable() ||
889 !TII->isTriviallyReMaterializable(this) ||
890 !isSafeToMove(TII, SawStore))
892 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
893 const MachineOperand &MO = getOperand(i);
896 // FIXME: For now, do not remat any instruction with register operands.
897 // Later on, we can loosen the restriction is the register operands have
898 // not been modified between the def and use. Note, this is different from
899 // MachineSink because the code is no longer in two-address form (at least
903 else if (!MO.isDead() && MO.getReg() != DstReg)
909 /// hasVolatileMemoryRef - Return true if this instruction may have a
910 /// volatile memory reference, or if the information describing the
911 /// memory reference is not available. Return false if it is known to
912 /// have no volatile memory references.
913 bool MachineInstr::hasVolatileMemoryRef() const {
914 // An instruction known never to access memory won't have a volatile access.
915 if (!TID->mayStore() &&
918 !TID->hasUnmodeledSideEffects())
921 // Otherwise, if the instruction has no memory reference information,
922 // conservatively assume it wasn't preserved.
923 if (memoperands_empty())
926 // Check the memory reference information for volatile references.
927 for (std::list<MachineMemOperand>::const_iterator I = memoperands_begin(),
928 E = memoperands_end(); I != E; ++I)
935 void MachineInstr::dump() const {
936 cerr << " " << *this;
939 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
940 raw_os_ostream RawOS(OS);
944 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
945 // Specialize printing if op#0 is definition
946 unsigned StartOp = 0;
947 if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
948 getOperand(0).print(OS, TM);
950 ++StartOp; // Don't print this operand again!
953 OS << getDesc().getName();
955 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
959 getOperand(i).print(OS, TM);
962 if (!memoperands_empty()) {
964 for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(),
965 e = memoperands_end(); i != e; ++i) {
966 const MachineMemOperand &MRO = *i;
967 const Value *V = MRO.getValue();
969 assert((MRO.isLoad() || MRO.isStore()) &&
970 "SV has to be a load, store or both.");
972 if (MRO.isVolatile())
980 OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
984 else if (!V->getName().empty())
986 else if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
991 OS << " + " << MRO.getOffset() << "]";
995 if (!debugLoc.isUnknown()) {
996 const MachineFunction *MF = getParent()->getParent();
997 DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc);
998 DICompileUnit CU(DLT.CompileUnit);
1001 << CU.getDirectory(Dir) << '/' << CU.getFilename(Fn) << ","
1009 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1010 const TargetRegisterInfo *RegInfo,
1011 bool AddIfNotFound) {
1012 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1013 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1015 SmallVector<unsigned,4> DeadOps;
1016 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1017 MachineOperand &MO = getOperand(i);
1018 if (!MO.isReg() || !MO.isUse())
1020 unsigned Reg = MO.getReg();
1024 if (Reg == IncomingReg) {
1027 // The register is already marked kill.
1032 } else if (hasAliases && MO.isKill() &&
1033 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1034 // A super-register kill already exists.
1035 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1037 if (RegInfo->isSubRegister(IncomingReg, Reg))
1038 DeadOps.push_back(i);
1042 // Trim unneeded kill operands.
1043 while (!DeadOps.empty()) {
1044 unsigned OpIdx = DeadOps.back();
1045 if (getOperand(OpIdx).isImplicit())
1046 RemoveOperand(OpIdx);
1048 getOperand(OpIdx).setIsKill(false);
1052 // If not found, this means an alias of one of the operands is killed. Add a
1053 // new implicit operand if required.
1054 if (!Found && AddIfNotFound) {
1055 addOperand(MachineOperand::CreateReg(IncomingReg,
1064 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1065 const TargetRegisterInfo *RegInfo,
1066 bool AddIfNotFound) {
1067 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1068 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1070 SmallVector<unsigned,4> DeadOps;
1071 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1072 MachineOperand &MO = getOperand(i);
1073 if (!MO.isReg() || !MO.isDef())
1075 unsigned Reg = MO.getReg();
1079 if (Reg == IncomingReg) {
1082 // The register is already marked dead.
1087 } else if (hasAliases && MO.isDead() &&
1088 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1089 // There exists a super-register that's marked dead.
1090 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1092 if (RegInfo->getSubRegisters(IncomingReg) &&
1093 RegInfo->getSuperRegisters(Reg) &&
1094 RegInfo->isSubRegister(IncomingReg, Reg))
1095 DeadOps.push_back(i);
1099 // Trim unneeded dead operands.
1100 while (!DeadOps.empty()) {
1101 unsigned OpIdx = DeadOps.back();
1102 if (getOperand(OpIdx).isImplicit())
1103 RemoveOperand(OpIdx);
1105 getOperand(OpIdx).setIsDead(false);
1109 // If not found, this means an alias of one of the operands is dead. Add a
1110 // new implicit operand if required.
1111 if (Found || !AddIfNotFound)
1114 addOperand(MachineOperand::CreateReg(IncomingReg,