1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 #include "llvm/CodeGen/MachineInstr.h"
13 #include "llvm/CodeGen/MachineBasicBlock.h"
14 #include "llvm/Value.h"
15 #include "llvm/Target/TargetMachine.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Target/MRegisterInfo.h"
21 // Global variable holding an array of descriptors for machine instructions.
22 // The actual object needs to be created separately for each target machine.
23 // This variable is initialized and reset by class TargetInstrInfo.
25 // FIXME: This should be a property of the target so that more than one target
26 // at a time can be active...
28 extern const TargetInstrDescriptor *TargetInstrDescriptors;
30 // Constructor for instructions with variable #operands
31 MachineInstr::MachineInstr(short opcode, unsigned numOperands)
34 operands(numOperands, MachineOperand()),
38 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
39 /// not a resize for them. It is expected that if you use this that you call
40 /// add* methods below to fill up the operands, instead of the Set methods.
41 /// Eventually, the "resizing" ctors will be phased out.
43 MachineInstr::MachineInstr(short opcode, unsigned numOperands,
48 operands.reserve(numOperands);
51 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
52 /// MachineInstr is created and added to the end of the specified basic block.
54 MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
59 assert(MBB && "Cannot use inserting ctor with null basic block!");
60 operands.reserve(numOperands);
61 MBB->push_back(this); // Add instruction to end of basic block!
65 // OperandComplete - Return true if it's illegal to add a new operand
66 bool MachineInstr::OperandsComplete() const {
67 int NumOperands = TargetInstrDescriptors[Opcode].numOperands;
68 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
69 return true; // Broken: we have all the operands of this instruction!
75 // Support for replacing opcode and operands of a MachineInstr in place.
76 // This only resets the size of the operand vector and initializes it.
77 // The new operands must be set explicitly later.
79 void MachineInstr::replace(short opcode, unsigned numOperands) {
80 assert(getNumImplicitRefs() == 0 &&
81 "This is probably broken because implicit refs are going to be lost.");
84 operands.resize(numOperands, MachineOperand());
87 void MachineInstr::SetMachineOperandVal(unsigned i,
88 MachineOperand::MachineOperandType opTy,
90 assert(i < operands.size()); // may be explicit or implicit op
91 operands[i].opType = opTy;
92 operands[i].value = V;
93 operands[i].regNum = -1;
97 MachineInstr::SetMachineOperandConst(unsigned i,
98 MachineOperand::MachineOperandType operandType,
100 assert(i < getNumOperands()); // must be explicit op
101 assert(TargetInstrDescriptors[Opcode].resultPos != (int) i &&
102 "immed. constant cannot be defined");
104 operands[i].opType = operandType;
105 operands[i].value = NULL;
106 operands[i].immedVal = intValue;
107 operands[i].regNum = -1;
108 operands[i].flags = 0;
111 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
112 assert(i < getNumOperands()); // must be explicit op
114 operands[i].opType = MachineOperand::MO_MachineRegister;
115 operands[i].value = NULL;
116 operands[i].regNum = regNum;
119 void MachineInstr::SetRegForOperand(unsigned i, int regNum) {
120 assert(i < getNumOperands()); // must be explicit op
121 operands[i].setRegForValue(regNum);
124 void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) {
125 getImplicitOp(i).setRegForValue(regNum);
129 // Substitute all occurrences of Value* oldVal with newVal in all operands
130 // and all implicit refs.
131 // If defsOnly == true, substitute defs only.
133 MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
134 bool defsOnly, bool notDefsAndUses,
135 bool& someArgsWereIgnored)
137 assert((!defsOnly || !notDefsAndUses) &&
138 "notDefsAndUses is irrelevant if defsOnly == true.");
140 unsigned numSubst = 0;
142 // Substitute operands
143 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
146 notDefsAndUses && (O.isDef() && !O.isUse()) ||
147 !notDefsAndUses && O.isDef())
149 O.getMachineOperand().value = newVal;
153 someArgsWereIgnored = true;
155 // Substitute implicit refs
156 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
157 if (getImplicitRef(i) == oldVal)
159 notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
160 !notDefsAndUses && getImplicitOp(i).isDef())
162 getImplicitOp(i).value = newVal;
166 someArgsWereIgnored = true;
173 MachineInstr::dump() const
175 std::cerr << " " << *this;
178 static inline std::ostream&
179 OutputValue(std::ostream &os, const Value* val)
182 os << (void*) val; // print address always
183 if (val && val->hasName())
184 os << " " << val->getName() << ")"; // print name also, if available
188 static inline void OutputReg(std::ostream &os, unsigned RegNo,
189 const MRegisterInfo *MRI = 0) {
191 if (RegNo < MRegisterInfo::FirstVirtualRegister)
192 os << "%" << MRI->get(RegNo).Name;
194 os << "%reg" << RegNo;
196 os << "%mreg(" << RegNo << ")";
199 static void print(const MachineOperand &MO, std::ostream &OS,
200 const TargetMachine &TM) {
201 const MRegisterInfo *MRI = TM.getRegisterInfo();
202 bool CloseParen = true;
205 else if (MO.isLoBits32())
207 else if (MO.isHiBits64())
209 else if (MO.isLoBits64())
214 switch (MO.getType()) {
215 case MachineOperand::MO_VirtualRegister:
216 if (MO.getVRegValue()) {
218 OutputValue(OS, MO.getVRegValue());
219 if (MO.hasAllocatedReg())
222 if (MO.hasAllocatedReg())
223 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
225 case MachineOperand::MO_CCRegister:
227 OutputValue(OS, MO.getVRegValue());
228 if (MO.hasAllocatedReg()) {
230 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
233 case MachineOperand::MO_MachineRegister:
234 OutputReg(OS, MO.getMachineRegNum(), MRI);
236 case MachineOperand::MO_SignExtendedImmed:
237 OS << (long)MO.getImmedValue();
239 case MachineOperand::MO_UnextendedImmed:
240 OS << (long)MO.getImmedValue();
242 case MachineOperand::MO_PCRelativeDisp: {
243 const Value* opVal = MO.getVRegValue();
244 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
245 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
246 if (opVal->hasName())
247 OS << opVal->getName();
249 OS << (const void*) opVal;
253 case MachineOperand::MO_MachineBasicBlock:
255 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
256 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
258 case MachineOperand::MO_FrameIndex:
259 OS << "<fi#" << MO.getFrameIndex() << ">";
261 case MachineOperand::MO_ConstantPoolIndex:
262 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
264 case MachineOperand::MO_GlobalAddress:
265 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
267 case MachineOperand::MO_ExternalSymbol:
268 OS << "<es:" << MO.getSymbolName() << ">";
271 assert(0 && "Unrecognized operand type");
278 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
279 unsigned StartOp = 0;
281 // Specialize printing if op#0 is definition
282 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
283 llvm::print(getOperand(0), OS, TM);
285 ++StartOp; // Don't print this operand again!
287 OS << TM.getInstrInfo().getName(getOpcode());
289 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
290 const MachineOperand& mop = getOperand(i);
294 llvm::print(mop, OS, TM);
303 // code for printing implicit references
304 if (getNumImplicitRefs()) {
305 OS << "\tImplicitRefs: ";
306 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
308 OutputValue(OS, getImplicitRef(i));
309 if (getImplicitOp(i).isDef())
310 if (getImplicitOp(i).isUse())
321 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
323 os << TargetInstrDescriptors[MI.getOpcode()].Name;
325 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
326 os << "\t" << MI.getOperand(i);
327 if (MI.getOperand(i).isDef())
328 if (MI.getOperand(i).isUse())
334 // code for printing implicit references
335 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
336 if (NumOfImpRefs > 0) {
337 os << "\tImplicit: ";
338 for (unsigned z=0; z < NumOfImpRefs; z++) {
339 OutputValue(os, MI.getImplicitRef(z));
340 if (MI.getImplicitOp(z).isDef())
341 if (MI.getImplicitOp(z).isUse())
352 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
356 else if (MO.isLoBits32())
358 else if (MO.isHiBits64())
360 else if (MO.isLoBits64())
363 switch (MO.getType())
365 case MachineOperand::MO_VirtualRegister:
366 if (MO.hasAllocatedReg())
367 OutputReg(OS, MO.getAllocatedRegNum());
369 if (MO.getVRegValue()) {
370 if (MO.hasAllocatedReg()) OS << "==";
372 OutputValue(OS, MO.getVRegValue());
375 case MachineOperand::MO_CCRegister:
377 OutputValue(OS, MO.getVRegValue());
378 if (MO.hasAllocatedReg()) {
380 OutputReg(OS, MO.getAllocatedRegNum());
383 case MachineOperand::MO_MachineRegister:
384 OutputReg(OS, MO.getMachineRegNum());
386 case MachineOperand::MO_SignExtendedImmed:
387 OS << (long)MO.getImmedValue();
389 case MachineOperand::MO_UnextendedImmed:
390 OS << (long)MO.getImmedValue();
392 case MachineOperand::MO_PCRelativeDisp:
394 const Value* opVal = MO.getVRegValue();
395 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
396 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
397 if (opVal->hasName())
398 OS << opVal->getName();
400 OS << (const void*) opVal;
404 case MachineOperand::MO_MachineBasicBlock:
406 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
407 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
409 case MachineOperand::MO_FrameIndex:
410 OS << "<fi#" << MO.getFrameIndex() << ">";
412 case MachineOperand::MO_ConstantPoolIndex:
413 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
415 case MachineOperand::MO_GlobalAddress:
416 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
418 case MachineOperand::MO_ExternalSymbol:
419 OS << "<es:" << MO.getSymbolName() << ">";
422 assert(0 && "Unrecognized operand type");
427 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
428 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))
434 } // End llvm namespace