1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Constants.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/Value.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetInstrDesc.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Support/LeakDetector.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/Streams.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/ADT/FoldingSet.h"
32 //===----------------------------------------------------------------------===//
33 // MachineOperand Implementation
34 //===----------------------------------------------------------------------===//
36 /// AddRegOperandToRegInfo - Add this register operand to the specified
37 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
38 /// explicitly nulled out.
39 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
40 assert(isReg() && "Can only add reg operand to use lists");
42 // If the reginfo pointer is null, just explicitly null out or next/prev
43 // pointers, to ensure they are not garbage.
45 Contents.Reg.Prev = 0;
46 Contents.Reg.Next = 0;
50 // Otherwise, add this operand to the head of the registers use/def list.
51 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
53 // For SSA values, we prefer to keep the definition at the start of the list.
54 // we do this by skipping over the definition if it is at the head of the
56 if (*Head && (*Head)->isDef())
57 Head = &(*Head)->Contents.Reg.Next;
59 Contents.Reg.Next = *Head;
60 if (Contents.Reg.Next) {
61 assert(getReg() == Contents.Reg.Next->getReg() &&
62 "Different regs on the same list!");
63 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
66 Contents.Reg.Prev = Head;
70 void MachineOperand::setReg(unsigned Reg) {
71 if (getReg() == Reg) return; // No change.
73 // Otherwise, we have to change the register. If this operand is embedded
74 // into a machine function, we need to update the old and new register's
76 if (MachineInstr *MI = getParent())
77 if (MachineBasicBlock *MBB = MI->getParent())
78 if (MachineFunction *MF = MBB->getParent()) {
79 RemoveRegOperandFromRegInfo();
80 Contents.Reg.RegNo = Reg;
81 AddRegOperandToRegInfo(&MF->getRegInfo());
85 // Otherwise, just change the register, no problem. :)
86 Contents.Reg.RegNo = Reg;
89 /// ChangeToImmediate - Replace this operand with a new immediate operand of
90 /// the specified value. If an operand is known to be an immediate already,
91 /// the setImm method should be used.
92 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
93 // If this operand is currently a register operand, and if this is in a
94 // function, deregister the operand from the register's use/def list.
95 if (isReg() && getParent() && getParent()->getParent() &&
96 getParent()->getParent()->getParent())
97 RemoveRegOperandFromRegInfo();
99 OpKind = MO_Immediate;
100 Contents.ImmVal = ImmVal;
103 /// ChangeToRegister - Replace this operand with a new register operand of
104 /// the specified value. If an operand is known to be an register already,
105 /// the setReg method should be used.
106 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
107 bool isKill, bool isDead) {
108 // If this operand is already a register operand, use setReg to update the
109 // register's use/def lists.
111 assert(!isEarlyClobber());
114 // Otherwise, change this to a register and set the reg#.
115 OpKind = MO_Register;
116 Contents.Reg.RegNo = Reg;
118 // If this operand is embedded in a function, add the operand to the
119 // register's use/def list.
120 if (MachineInstr *MI = getParent())
121 if (MachineBasicBlock *MBB = MI->getParent())
122 if (MachineFunction *MF = MBB->getParent())
123 AddRegOperandToRegInfo(&MF->getRegInfo());
130 IsEarlyClobber = false;
134 /// isIdenticalTo - Return true if this operand is identical to the specified
136 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
137 if (getType() != Other.getType()) return false;
140 default: assert(0 && "Unrecognized operand type");
141 case MachineOperand::MO_Register:
142 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
143 getSubReg() == Other.getSubReg();
144 case MachineOperand::MO_Immediate:
145 return getImm() == Other.getImm();
146 case MachineOperand::MO_FPImmediate:
147 return getFPImm() == Other.getFPImm();
148 case MachineOperand::MO_MachineBasicBlock:
149 return getMBB() == Other.getMBB();
150 case MachineOperand::MO_FrameIndex:
151 return getIndex() == Other.getIndex();
152 case MachineOperand::MO_ConstantPoolIndex:
153 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
154 case MachineOperand::MO_JumpTableIndex:
155 return getIndex() == Other.getIndex();
156 case MachineOperand::MO_GlobalAddress:
157 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
158 case MachineOperand::MO_ExternalSymbol:
159 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
160 getOffset() == Other.getOffset();
164 /// print - Print the specified machine operand.
166 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
167 raw_os_ostream RawOS(OS);
171 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
173 case MachineOperand::MO_Register:
174 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
175 OS << "%reg" << getReg();
177 // If the instruction is embedded into a basic block, we can find the
178 // target info for the instruction.
180 if (const MachineInstr *MI = getParent())
181 if (const MachineBasicBlock *MBB = MI->getParent())
182 if (const MachineFunction *MF = MBB->getParent())
183 TM = &MF->getTarget();
186 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
188 OS << "%mreg" << getReg();
191 if (getSubReg() != 0) {
192 OS << ":" << getSubReg();
195 if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) {
197 bool NeedComma = false;
199 if (NeedComma) OS << ",";
200 OS << (isDef() ? "imp-def" : "imp-use");
202 } else if (isDef()) {
203 if (NeedComma) OS << ",";
204 if (isEarlyClobber())
205 OS << "earlyclobber,";
209 if (isKill() || isDead()) {
210 if (NeedComma) OS << ",";
211 if (isKill()) OS << "kill";
212 if (isDead()) OS << "dead";
217 case MachineOperand::MO_Immediate:
220 case MachineOperand::MO_FPImmediate:
221 if (getFPImm()->getType() == Type::FloatTy) {
222 OS << getFPImm()->getValueAPF().convertToFloat();
224 OS << getFPImm()->getValueAPF().convertToDouble();
227 case MachineOperand::MO_MachineBasicBlock:
229 << ((Value*)getMBB()->getBasicBlock())->getName()
230 << "," << (void*)getMBB() << ">";
232 case MachineOperand::MO_FrameIndex:
233 OS << "<fi#" << getIndex() << ">";
235 case MachineOperand::MO_ConstantPoolIndex:
236 OS << "<cp#" << getIndex();
237 if (getOffset()) OS << "+" << getOffset();
240 case MachineOperand::MO_JumpTableIndex:
241 OS << "<jt#" << getIndex() << ">";
243 case MachineOperand::MO_GlobalAddress:
244 OS << "<ga:" << ((Value*)getGlobal())->getName();
245 if (getOffset()) OS << "+" << getOffset();
248 case MachineOperand::MO_ExternalSymbol:
249 OS << "<es:" << getSymbolName();
250 if (getOffset()) OS << "+" << getOffset();
254 assert(0 && "Unrecognized operand type");
258 //===----------------------------------------------------------------------===//
259 // MachineMemOperand Implementation
260 //===----------------------------------------------------------------------===//
262 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
263 int64_t o, uint64_t s, unsigned int a)
264 : Offset(o), Size(s), V(v),
265 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
266 assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
267 assert((isLoad() || isStore()) && "Not a load/store!");
270 /// Profile - Gather unique data for the object.
272 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
273 ID.AddInteger(Offset);
276 ID.AddInteger(Flags);
279 //===----------------------------------------------------------------------===//
280 // MachineInstr Implementation
281 //===----------------------------------------------------------------------===//
283 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
284 /// TID NULL and no operands.
285 MachineInstr::MachineInstr()
286 : TID(0), NumImplicitOps(0), Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
287 // Make sure that we get added to a machine basicblock
288 LeakDetector::addGarbageObject(this);
291 void MachineInstr::addImplicitDefUseOperands() {
292 if (TID->ImplicitDefs)
293 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
294 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
295 if (TID->ImplicitUses)
296 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
297 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
300 /// MachineInstr ctor - This constructor create a MachineInstr and add the
301 /// implicit operands. It reserves space for number of operands specified by
302 /// TargetInstrDesc or the numOperands if it is not zero. (for
303 /// instructions with variable number of operands).
304 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
305 : TID(&tid), NumImplicitOps(0), Parent(0),
306 debugLoc(DebugLoc::getUnknownLoc()) {
307 if (!NoImp && TID->getImplicitDefs())
308 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
310 if (!NoImp && TID->getImplicitUses())
311 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
313 Operands.reserve(NumImplicitOps + TID->getNumOperands());
315 addImplicitDefUseOperands();
316 // Make sure that we get added to a machine basicblock
317 LeakDetector::addGarbageObject(this);
320 /// MachineInstr ctor - As above, but with a DebugLoc.
321 MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
323 : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
324 if (!NoImp && TID->getImplicitDefs())
325 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
327 if (!NoImp && TID->getImplicitUses())
328 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
330 Operands.reserve(NumImplicitOps + TID->getNumOperands());
332 addImplicitDefUseOperands();
333 // Make sure that we get added to a machine basicblock
334 LeakDetector::addGarbageObject(this);
337 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
338 /// that the MachineInstr is created and added to the end of the specified
341 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
342 : TID(&tid), NumImplicitOps(0), Parent(0),
343 debugLoc(DebugLoc::getUnknownLoc()) {
344 assert(MBB && "Cannot use inserting ctor with null basic block!");
345 if (TID->ImplicitDefs)
346 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
348 if (TID->ImplicitUses)
349 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
351 Operands.reserve(NumImplicitOps + TID->getNumOperands());
352 addImplicitDefUseOperands();
353 // Make sure that we get added to a machine basicblock
354 LeakDetector::addGarbageObject(this);
355 MBB->push_back(this); // Add instruction to end of basic block!
358 /// MachineInstr ctor - As above, but with a DebugLoc.
360 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
361 const TargetInstrDesc &tid)
362 : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
363 assert(MBB && "Cannot use inserting ctor with null basic block!");
364 if (TID->ImplicitDefs)
365 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
367 if (TID->ImplicitUses)
368 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
370 Operands.reserve(NumImplicitOps + TID->getNumOperands());
371 addImplicitDefUseOperands();
372 // Make sure that we get added to a machine basicblock
373 LeakDetector::addGarbageObject(this);
374 MBB->push_back(this); // Add instruction to end of basic block!
377 /// MachineInstr ctor - Copies MachineInstr arg exactly
379 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
380 : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0),
381 debugLoc(MI.getDebugLoc()) {
382 Operands.reserve(MI.getNumOperands());
385 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
386 addOperand(MI.getOperand(i));
387 NumImplicitOps = MI.NumImplicitOps;
389 // Add memory operands.
390 for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
391 j = MI.memoperands_end(); i != j; ++i)
392 addMemOperand(MF, *i);
394 // Set parent to null.
397 LeakDetector::addGarbageObject(this);
400 MachineInstr::~MachineInstr() {
401 LeakDetector::removeGarbageObject(this);
402 assert(MemOperands.empty() &&
403 "MachineInstr being deleted with live memoperands!");
405 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
406 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
407 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
408 "Reg operand def/use list corrupted");
413 /// getRegInfo - If this instruction is embedded into a MachineFunction,
414 /// return the MachineRegisterInfo object for the current function, otherwise
416 MachineRegisterInfo *MachineInstr::getRegInfo() {
417 if (MachineBasicBlock *MBB = getParent())
418 return &MBB->getParent()->getRegInfo();
422 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
423 /// this instruction from their respective use lists. This requires that the
424 /// operands already be on their use lists.
425 void MachineInstr::RemoveRegOperandsFromUseLists() {
426 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
427 if (Operands[i].isReg())
428 Operands[i].RemoveRegOperandFromRegInfo();
432 /// AddRegOperandsToUseLists - Add all of the register operands in
433 /// this instruction from their respective use lists. This requires that the
434 /// operands not be on their use lists yet.
435 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
436 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
437 if (Operands[i].isReg())
438 Operands[i].AddRegOperandToRegInfo(&RegInfo);
443 /// addOperand - Add the specified operand to the instruction. If it is an
444 /// implicit operand, it is added to the end of the operand list. If it is
445 /// an explicit operand it is added at the end of the explicit operand list
446 /// (before the first implicit operand).
447 void MachineInstr::addOperand(const MachineOperand &Op) {
448 bool isImpReg = Op.isReg() && Op.isImplicit();
449 assert((isImpReg || !OperandsComplete()) &&
450 "Trying to add an operand to a machine instr that is already done!");
452 MachineRegisterInfo *RegInfo = getRegInfo();
454 // If we are adding the operand to the end of the list, our job is simpler.
455 // This is true most of the time, so this is a reasonable optimization.
456 if (isImpReg || NumImplicitOps == 0) {
457 // We can only do this optimization if we know that the operand list won't
459 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
460 Operands.push_back(Op);
462 // Set the parent of the operand.
463 Operands.back().ParentMI = this;
465 // If the operand is a register, update the operand's use list.
467 Operands.back().AddRegOperandToRegInfo(RegInfo);
472 // Otherwise, we have to insert a real operand before any implicit ones.
473 unsigned OpNo = Operands.size()-NumImplicitOps;
475 // If this instruction isn't embedded into a function, then we don't need to
476 // update any operand lists.
478 // Simple insertion, no reginfo update needed for other register operands.
479 Operands.insert(Operands.begin()+OpNo, Op);
480 Operands[OpNo].ParentMI = this;
482 // Do explicitly set the reginfo for this operand though, to ensure the
483 // next/prev fields are properly nulled out.
484 if (Operands[OpNo].isReg())
485 Operands[OpNo].AddRegOperandToRegInfo(0);
487 } else if (Operands.size()+1 <= Operands.capacity()) {
488 // Otherwise, we have to remove register operands from their register use
489 // list, add the operand, then add the register operands back to their use
490 // list. This also must handle the case when the operand list reallocates
491 // to somewhere else.
493 // If insertion of this operand won't cause reallocation of the operand
494 // list, just remove the implicit operands, add the operand, then re-add all
495 // the rest of the operands.
496 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
497 assert(Operands[i].isReg() && "Should only be an implicit reg!");
498 Operands[i].RemoveRegOperandFromRegInfo();
501 // Add the operand. If it is a register, add it to the reg list.
502 Operands.insert(Operands.begin()+OpNo, Op);
503 Operands[OpNo].ParentMI = this;
505 if (Operands[OpNo].isReg())
506 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
508 // Re-add all the implicit ops.
509 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
510 assert(Operands[i].isReg() && "Should only be an implicit reg!");
511 Operands[i].AddRegOperandToRegInfo(RegInfo);
514 // Otherwise, we will be reallocating the operand list. Remove all reg
515 // operands from their list, then readd them after the operand list is
517 RemoveRegOperandsFromUseLists();
519 Operands.insert(Operands.begin()+OpNo, Op);
520 Operands[OpNo].ParentMI = this;
522 // Re-add all the operands.
523 AddRegOperandsToUseLists(*RegInfo);
527 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
528 /// fewer operand than it started with.
530 void MachineInstr::RemoveOperand(unsigned OpNo) {
531 assert(OpNo < Operands.size() && "Invalid operand number");
533 // Special case removing the last one.
534 if (OpNo == Operands.size()-1) {
535 // If needed, remove from the reg def/use list.
536 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
537 Operands.back().RemoveRegOperandFromRegInfo();
543 // Otherwise, we are removing an interior operand. If we have reginfo to
544 // update, remove all operands that will be shifted down from their reg lists,
545 // move everything down, then re-add them.
546 MachineRegisterInfo *RegInfo = getRegInfo();
548 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
549 if (Operands[i].isReg())
550 Operands[i].RemoveRegOperandFromRegInfo();
554 Operands.erase(Operands.begin()+OpNo);
557 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
558 if (Operands[i].isReg())
559 Operands[i].AddRegOperandToRegInfo(RegInfo);
564 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
565 /// referencing arbitrary storage.
566 void MachineInstr::addMemOperand(MachineFunction &MF,
567 const MachineMemOperand &MO) {
568 MemOperands.push_back(MO);
571 /// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
572 void MachineInstr::clearMemOperands(MachineFunction &MF) {
577 /// removeFromParent - This method unlinks 'this' from the containing basic
578 /// block, and returns it, but does not delete it.
579 MachineInstr *MachineInstr::removeFromParent() {
580 assert(getParent() && "Not embedded in a basic block!");
581 getParent()->remove(this);
586 /// eraseFromParent - This method unlinks 'this' from the containing basic
587 /// block, and deletes it.
588 void MachineInstr::eraseFromParent() {
589 assert(getParent() && "Not embedded in a basic block!");
590 getParent()->erase(this);
594 /// OperandComplete - Return true if it's illegal to add a new operand
596 bool MachineInstr::OperandsComplete() const {
597 unsigned short NumOperands = TID->getNumOperands();
598 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
599 return true; // Broken: we have all the operands of this instruction!
603 /// getNumExplicitOperands - Returns the number of non-implicit operands.
605 unsigned MachineInstr::getNumExplicitOperands() const {
606 unsigned NumOperands = TID->getNumOperands();
607 if (!TID->isVariadic())
610 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
611 const MachineOperand &MO = getOperand(NumOperands);
612 if (!MO.isReg() || !MO.isImplicit())
619 /// isLabel - Returns true if the MachineInstr represents a label.
621 bool MachineInstr::isLabel() const {
622 return getOpcode() == TargetInstrInfo::DBG_LABEL ||
623 getOpcode() == TargetInstrInfo::EH_LABEL ||
624 getOpcode() == TargetInstrInfo::GC_LABEL;
627 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
629 bool MachineInstr::isDebugLabel() const {
630 return getOpcode() == TargetInstrInfo::DBG_LABEL;
633 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
634 /// the specific register or -1 if it is not found. It further tightening
635 /// the search criteria to a use that kills the register if isKill is true.
636 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
637 const TargetRegisterInfo *TRI) const {
638 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
639 const MachineOperand &MO = getOperand(i);
640 if (!MO.isReg() || !MO.isUse())
642 unsigned MOReg = MO.getReg();
647 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
648 TargetRegisterInfo::isPhysicalRegister(Reg) &&
649 TRI->isSubRegister(MOReg, Reg)))
650 if (!isKill || MO.isKill())
656 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
657 /// the specified register or -1 if it is not found. If isDead is true, defs
658 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
659 /// also checks if there is a def of a super-register.
660 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
661 const TargetRegisterInfo *TRI) const {
662 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
663 const MachineOperand &MO = getOperand(i);
664 if (!MO.isReg() || !MO.isDef())
666 unsigned MOReg = MO.getReg();
669 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
670 TargetRegisterInfo::isPhysicalRegister(Reg) &&
671 TRI->isSubRegister(MOReg, Reg)))
672 if (!isDead || MO.isDead())
678 /// findFirstPredOperandIdx() - Find the index of the first operand in the
679 /// operand list that is used to represent the predicate. It returns -1 if
681 int MachineInstr::findFirstPredOperandIdx() const {
682 const TargetInstrDesc &TID = getDesc();
683 if (TID.isPredicable()) {
684 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
685 if (TID.OpInfo[i].isPredicate())
692 /// isRegReDefinedByTwoAddr - Given the index of a register operand,
693 /// check if the register def is a re-definition due to two addr elimination.
694 bool MachineInstr::isRegReDefinedByTwoAddr(unsigned DefIdx) const{
695 assert(getOperand(DefIdx).isDef() && "DefIdx is not a def!");
696 const TargetInstrDesc &TID = getDesc();
697 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
698 const MachineOperand &MO = getOperand(i);
699 if (MO.isReg() && MO.isUse() &&
700 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
706 /// isRegTiedToDefOperand - Return true if the operand of the specified index
707 /// is a register use and it is tied to an def operand. It also returns the def
708 /// operand index by reference.
709 bool MachineInstr::isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx){
710 const TargetInstrDesc &TID = getDesc();
711 if (UseOpIdx >= TID.getNumOperands())
713 const MachineOperand &MO = getOperand(UseOpIdx);
714 if (!MO.isReg() || !MO.isUse())
716 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
720 *DefOpIdx = (unsigned)DefIdx;
724 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
726 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
727 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
728 const MachineOperand &MO = MI->getOperand(i);
729 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
731 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
732 MachineOperand &MOp = getOperand(j);
733 if (!MOp.isIdenticalTo(MO))
744 /// copyPredicates - Copies predicate operand(s) from MI.
745 void MachineInstr::copyPredicates(const MachineInstr *MI) {
746 const TargetInstrDesc &TID = MI->getDesc();
747 if (!TID.isPredicable())
749 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
750 if (TID.OpInfo[i].isPredicate()) {
751 // Predicated operands must be last operands.
752 addOperand(MI->getOperand(i));
757 /// isSafeToMove - Return true if it is safe to move this instruction. If
758 /// SawStore is set to true, it means that there is a store (or call) between
759 /// the instruction's location and its intended destination.
760 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
761 bool &SawStore) const {
762 // Ignore stuff that we obviously can't move.
763 if (TID->mayStore() || TID->isCall()) {
767 if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
770 // See if this instruction does a load. If so, we have to guarantee that the
771 // loaded value doesn't change between the load and the its intended
772 // destination. The check for isInvariantLoad gives the targe the chance to
773 // classify the load as always returning a constant, e.g. a constant pool
775 if (TID->mayLoad() && !TII->isInvariantLoad(this))
776 // Otherwise, this is a real load. If there is a store between the load and
777 // end of block, or if the laod is volatile, we can't move it.
778 return !SawStore && !hasVolatileMemoryRef();
783 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
784 /// instruction which defined the specified register instead of copying it.
785 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
786 unsigned DstReg) const {
787 bool SawStore = false;
788 if (!getDesc().isRematerializable() ||
789 !TII->isTriviallyReMaterializable(this) ||
790 !isSafeToMove(TII, SawStore))
792 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
793 const MachineOperand &MO = getOperand(i);
796 // FIXME: For now, do not remat any instruction with register operands.
797 // Later on, we can loosen the restriction is the register operands have
798 // not been modified between the def and use. Note, this is different from
799 // MachineSink because the code is no longer in two-address form (at least
803 else if (!MO.isDead() && MO.getReg() != DstReg)
809 /// hasVolatileMemoryRef - Return true if this instruction may have a
810 /// volatile memory reference, or if the information describing the
811 /// memory reference is not available. Return false if it is known to
812 /// have no volatile memory references.
813 bool MachineInstr::hasVolatileMemoryRef() const {
814 // An instruction known never to access memory won't have a volatile access.
815 if (!TID->mayStore() &&
818 !TID->hasUnmodeledSideEffects())
821 // Otherwise, if the instruction has no memory reference information,
822 // conservatively assume it wasn't preserved.
823 if (memoperands_empty())
826 // Check the memory reference information for volatile references.
827 for (std::list<MachineMemOperand>::const_iterator I = memoperands_begin(),
828 E = memoperands_end(); I != E; ++I)
835 void MachineInstr::dump() const {
836 cerr << " " << *this;
839 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
840 raw_os_ostream RawOS(OS);
844 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
845 // Specialize printing if op#0 is definition
846 unsigned StartOp = 0;
847 if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
848 getOperand(0).print(OS, TM);
850 ++StartOp; // Don't print this operand again!
853 OS << getDesc().getName();
855 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
859 getOperand(i).print(OS, TM);
862 if (!memoperands_empty()) {
864 for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(),
865 e = memoperands_end(); i != e; ++i) {
866 const MachineMemOperand &MRO = *i;
867 const Value *V = MRO.getValue();
869 assert((MRO.isLoad() || MRO.isStore()) &&
870 "SV has to be a load, store or both.");
872 if (MRO.isVolatile())
880 OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
884 else if (!V->getName().empty())
886 else if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
891 OS << " + " << MRO.getOffset() << "]";
895 if (!debugLoc.isUnknown()) {
896 const MachineFunction *MF = getParent()->getParent();
897 DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc);
907 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
908 const TargetRegisterInfo *RegInfo,
909 bool AddIfNotFound) {
910 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
911 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
913 SmallVector<unsigned,4> DeadOps;
914 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
915 MachineOperand &MO = getOperand(i);
916 if (!MO.isReg() || !MO.isUse())
918 unsigned Reg = MO.getReg();
922 if (Reg == IncomingReg) {
925 // The register is already marked kill.
930 } else if (hasAliases && MO.isKill() &&
931 TargetRegisterInfo::isPhysicalRegister(Reg)) {
932 // A super-register kill already exists.
933 if (RegInfo->isSuperRegister(IncomingReg, Reg))
935 if (RegInfo->isSubRegister(IncomingReg, Reg))
936 DeadOps.push_back(i);
940 // Trim unneeded kill operands.
941 while (!DeadOps.empty()) {
942 unsigned OpIdx = DeadOps.back();
943 if (getOperand(OpIdx).isImplicit())
944 RemoveOperand(OpIdx);
946 getOperand(OpIdx).setIsKill(false);
950 // If not found, this means an alias of one of the operands is killed. Add a
951 // new implicit operand if required.
952 if (!Found && AddIfNotFound) {
953 addOperand(MachineOperand::CreateReg(IncomingReg,
962 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
963 const TargetRegisterInfo *RegInfo,
964 bool AddIfNotFound) {
965 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
966 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
968 SmallVector<unsigned,4> DeadOps;
969 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
970 MachineOperand &MO = getOperand(i);
971 if (!MO.isReg() || !MO.isDef())
973 unsigned Reg = MO.getReg();
977 if (Reg == IncomingReg) {
980 // The register is already marked dead.
985 } else if (hasAliases && MO.isDead() &&
986 TargetRegisterInfo::isPhysicalRegister(Reg)) {
987 // There exists a super-register that's marked dead.
988 if (RegInfo->isSuperRegister(IncomingReg, Reg))
990 if (RegInfo->getSubRegisters(IncomingReg) &&
991 RegInfo->getSuperRegisters(Reg) &&
992 RegInfo->isSubRegister(IncomingReg, Reg))
993 DeadOps.push_back(i);
997 // Trim unneeded dead operands.
998 while (!DeadOps.empty()) {
999 unsigned OpIdx = DeadOps.back();
1000 if (getOperand(OpIdx).isImplicit())
1001 RemoveOperand(OpIdx);
1003 getOperand(OpIdx).setIsDead(false);
1007 // If not found, this means an alias of one of the operands is dead. Add a
1008 // new implicit operand if required.
1009 if (!Found && AddIfNotFound) {
1010 addOperand(MachineOperand::CreateReg(IncomingReg,