1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Constants.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/Value.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetInstrDesc.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Support/LeakDetector.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/Streams.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/ADT/FoldingSet.h"
32 //===----------------------------------------------------------------------===//
33 // MachineOperand Implementation
34 //===----------------------------------------------------------------------===//
36 /// AddRegOperandToRegInfo - Add this register operand to the specified
37 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
38 /// explicitly nulled out.
39 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
40 assert(isReg() && "Can only add reg operand to use lists");
42 // If the reginfo pointer is null, just explicitly null out or next/prev
43 // pointers, to ensure they are not garbage.
45 Contents.Reg.Prev = 0;
46 Contents.Reg.Next = 0;
50 // Otherwise, add this operand to the head of the registers use/def list.
51 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
53 // For SSA values, we prefer to keep the definition at the start of the list.
54 // we do this by skipping over the definition if it is at the head of the
56 if (*Head && (*Head)->isDef())
57 Head = &(*Head)->Contents.Reg.Next;
59 Contents.Reg.Next = *Head;
60 if (Contents.Reg.Next) {
61 assert(getReg() == Contents.Reg.Next->getReg() &&
62 "Different regs on the same list!");
63 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
66 Contents.Reg.Prev = Head;
70 void MachineOperand::setReg(unsigned Reg) {
71 if (getReg() == Reg) return; // No change.
73 // Otherwise, we have to change the register. If this operand is embedded
74 // into a machine function, we need to update the old and new register's
76 if (MachineInstr *MI = getParent())
77 if (MachineBasicBlock *MBB = MI->getParent())
78 if (MachineFunction *MF = MBB->getParent()) {
79 RemoveRegOperandFromRegInfo();
80 Contents.Reg.RegNo = Reg;
81 AddRegOperandToRegInfo(&MF->getRegInfo());
85 // Otherwise, just change the register, no problem. :)
86 Contents.Reg.RegNo = Reg;
89 /// ChangeToImmediate - Replace this operand with a new immediate operand of
90 /// the specified value. If an operand is known to be an immediate already,
91 /// the setImm method should be used.
92 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
93 // If this operand is currently a register operand, and if this is in a
94 // function, deregister the operand from the register's use/def list.
95 if (isReg() && getParent() && getParent()->getParent() &&
96 getParent()->getParent()->getParent())
97 RemoveRegOperandFromRegInfo();
99 OpKind = MO_Immediate;
100 Contents.ImmVal = ImmVal;
103 /// ChangeToRegister - Replace this operand with a new register operand of
104 /// the specified value. If an operand is known to be an register already,
105 /// the setReg method should be used.
106 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
107 bool isKill, bool isDead) {
108 // If this operand is already a register operand, use setReg to update the
109 // register's use/def lists.
113 // Otherwise, change this to a register and set the reg#.
114 OpKind = MO_Register;
115 Contents.Reg.RegNo = Reg;
117 // If this operand is embedded in a function, add the operand to the
118 // register's use/def list.
119 if (MachineInstr *MI = getParent())
120 if (MachineBasicBlock *MBB = MI->getParent())
121 if (MachineFunction *MF = MBB->getParent())
122 AddRegOperandToRegInfo(&MF->getRegInfo());
132 /// isIdenticalTo - Return true if this operand is identical to the specified
134 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
135 if (getType() != Other.getType()) return false;
138 default: assert(0 && "Unrecognized operand type");
139 case MachineOperand::MO_Register:
140 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
141 getSubReg() == Other.getSubReg();
142 case MachineOperand::MO_Immediate:
143 return getImm() == Other.getImm();
144 case MachineOperand::MO_FPImmediate:
145 return getFPImm() == Other.getFPImm();
146 case MachineOperand::MO_MachineBasicBlock:
147 return getMBB() == Other.getMBB();
148 case MachineOperand::MO_FrameIndex:
149 return getIndex() == Other.getIndex();
150 case MachineOperand::MO_ConstantPoolIndex:
151 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
152 case MachineOperand::MO_JumpTableIndex:
153 return getIndex() == Other.getIndex();
154 case MachineOperand::MO_GlobalAddress:
155 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
156 case MachineOperand::MO_ExternalSymbol:
157 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
158 getOffset() == Other.getOffset();
162 /// print - Print the specified machine operand.
164 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
166 case MachineOperand::MO_Register:
167 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
168 OS << "%reg" << getReg();
170 // If the instruction is embedded into a basic block, we can find the
171 // target info for the instruction.
173 if (const MachineInstr *MI = getParent())
174 if (const MachineBasicBlock *MBB = MI->getParent())
175 if (const MachineFunction *MF = MBB->getParent())
176 TM = &MF->getTarget();
179 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
181 OS << "%mreg" << getReg();
184 if (isDef() || isKill() || isDead() || isImplicit()) {
186 bool NeedComma = false;
188 OS << (isDef() ? "imp-def" : "imp-use");
190 } else if (isDef()) {
194 if (isKill() || isDead()) {
195 if (NeedComma) OS << ",";
196 if (isKill()) OS << "kill";
197 if (isDead()) OS << "dead";
202 case MachineOperand::MO_Immediate:
205 case MachineOperand::MO_FPImmediate:
206 if (getFPImm()->getType() == Type::FloatTy) {
207 OS << getFPImm()->getValueAPF().convertToFloat();
209 OS << getFPImm()->getValueAPF().convertToDouble();
212 case MachineOperand::MO_MachineBasicBlock:
214 << ((Value*)getMBB()->getBasicBlock())->getName()
215 << "," << (void*)getMBB() << ">";
217 case MachineOperand::MO_FrameIndex:
218 OS << "<fi#" << getIndex() << ">";
220 case MachineOperand::MO_ConstantPoolIndex:
221 OS << "<cp#" << getIndex();
222 if (getOffset()) OS << "+" << getOffset();
225 case MachineOperand::MO_JumpTableIndex:
226 OS << "<jt#" << getIndex() << ">";
228 case MachineOperand::MO_GlobalAddress:
229 OS << "<ga:" << ((Value*)getGlobal())->getName();
230 if (getOffset()) OS << "+" << getOffset();
233 case MachineOperand::MO_ExternalSymbol:
234 OS << "<es:" << getSymbolName();
235 if (getOffset()) OS << "+" << getOffset();
239 assert(0 && "Unrecognized operand type");
243 //===----------------------------------------------------------------------===//
244 // MachineMemOperand Implementation
245 //===----------------------------------------------------------------------===//
247 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
248 int64_t o, uint64_t s, unsigned int a)
249 : Offset(o), Size(s), V(v),
250 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
251 assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
252 assert((isLoad() || isStore()) && "Not a load/store!");
255 /// Profile - Gather unique data for the object.
257 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
258 ID.AddInteger(Offset);
261 ID.AddInteger(Flags);
264 //===----------------------------------------------------------------------===//
265 // MachineInstr Implementation
266 //===----------------------------------------------------------------------===//
268 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
269 /// TID NULL and no operands.
270 MachineInstr::MachineInstr()
271 : TID(0), NumImplicitOps(0), Parent(0) {
272 // Make sure that we get added to a machine basicblock
273 LeakDetector::addGarbageObject(this);
276 void MachineInstr::addImplicitDefUseOperands() {
277 if (TID->ImplicitDefs)
278 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
279 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
280 if (TID->ImplicitUses)
281 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
282 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
285 /// MachineInstr ctor - This constructor create a MachineInstr and add the
286 /// implicit operands. It reserves space for number of operands specified by
287 /// TargetInstrDesc or the numOperands if it is not zero. (for
288 /// instructions with variable number of operands).
289 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
290 : TID(&tid), NumImplicitOps(0), Parent(0) {
291 if (!NoImp && TID->getImplicitDefs())
292 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
294 if (!NoImp && TID->getImplicitUses())
295 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
297 Operands.reserve(NumImplicitOps + TID->getNumOperands());
299 addImplicitDefUseOperands();
300 // Make sure that we get added to a machine basicblock
301 LeakDetector::addGarbageObject(this);
304 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
305 /// MachineInstr is created and added to the end of the specified basic block.
307 MachineInstr::MachineInstr(MachineBasicBlock *MBB,
308 const TargetInstrDesc &tid)
309 : TID(&tid), NumImplicitOps(0), Parent(0) {
310 assert(MBB && "Cannot use inserting ctor with null basic block!");
311 if (TID->ImplicitDefs)
312 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
314 if (TID->ImplicitUses)
315 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
317 Operands.reserve(NumImplicitOps + TID->getNumOperands());
318 addImplicitDefUseOperands();
319 // Make sure that we get added to a machine basicblock
320 LeakDetector::addGarbageObject(this);
321 MBB->push_back(this); // Add instruction to end of basic block!
324 /// MachineInstr ctor - Copies MachineInstr arg exactly
326 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
327 : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0) {
328 Operands.reserve(MI.getNumOperands());
331 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
332 addOperand(MI.getOperand(i));
333 NumImplicitOps = MI.NumImplicitOps;
335 // Add memory operands.
336 for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
337 j = MI.memoperands_end(); i != j; ++i)
338 addMemOperand(MF, *i);
340 // Set parent to null.
343 LeakDetector::addGarbageObject(this);
346 MachineInstr::~MachineInstr() {
347 LeakDetector::removeGarbageObject(this);
348 assert(MemOperands.empty() &&
349 "MachineInstr being deleted with live memoperands!");
351 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
352 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
353 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
354 "Reg operand def/use list corrupted");
359 /// getRegInfo - If this instruction is embedded into a MachineFunction,
360 /// return the MachineRegisterInfo object for the current function, otherwise
362 MachineRegisterInfo *MachineInstr::getRegInfo() {
363 if (MachineBasicBlock *MBB = getParent())
364 return &MBB->getParent()->getRegInfo();
368 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
369 /// this instruction from their respective use lists. This requires that the
370 /// operands already be on their use lists.
371 void MachineInstr::RemoveRegOperandsFromUseLists() {
372 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
373 if (Operands[i].isReg())
374 Operands[i].RemoveRegOperandFromRegInfo();
378 /// AddRegOperandsToUseLists - Add all of the register operands in
379 /// this instruction from their respective use lists. This requires that the
380 /// operands not be on their use lists yet.
381 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
382 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
383 if (Operands[i].isReg())
384 Operands[i].AddRegOperandToRegInfo(&RegInfo);
389 /// addOperand - Add the specified operand to the instruction. If it is an
390 /// implicit operand, it is added to the end of the operand list. If it is
391 /// an explicit operand it is added at the end of the explicit operand list
392 /// (before the first implicit operand).
393 void MachineInstr::addOperand(const MachineOperand &Op) {
394 bool isImpReg = Op.isReg() && Op.isImplicit();
395 assert((isImpReg || !OperandsComplete()) &&
396 "Trying to add an operand to a machine instr that is already done!");
398 // If we are adding the operand to the end of the list, our job is simpler.
399 // This is true most of the time, so this is a reasonable optimization.
400 if (isImpReg || NumImplicitOps == 0) {
401 // We can only do this optimization if we know that the operand list won't
403 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
404 Operands.push_back(Op);
406 // Set the parent of the operand.
407 Operands.back().ParentMI = this;
409 // If the operand is a register, update the operand's use list.
411 Operands.back().AddRegOperandToRegInfo(getRegInfo());
416 // Otherwise, we have to insert a real operand before any implicit ones.
417 unsigned OpNo = Operands.size()-NumImplicitOps;
419 MachineRegisterInfo *RegInfo = getRegInfo();
421 // If this instruction isn't embedded into a function, then we don't need to
422 // update any operand lists.
424 // Simple insertion, no reginfo update needed for other register operands.
425 Operands.insert(Operands.begin()+OpNo, Op);
426 Operands[OpNo].ParentMI = this;
428 // Do explicitly set the reginfo for this operand though, to ensure the
429 // next/prev fields are properly nulled out.
430 if (Operands[OpNo].isReg())
431 Operands[OpNo].AddRegOperandToRegInfo(0);
433 } else if (Operands.size()+1 <= Operands.capacity()) {
434 // Otherwise, we have to remove register operands from their register use
435 // list, add the operand, then add the register operands back to their use
436 // list. This also must handle the case when the operand list reallocates
437 // to somewhere else.
439 // If insertion of this operand won't cause reallocation of the operand
440 // list, just remove the implicit operands, add the operand, then re-add all
441 // the rest of the operands.
442 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
443 assert(Operands[i].isReg() && "Should only be an implicit reg!");
444 Operands[i].RemoveRegOperandFromRegInfo();
447 // Add the operand. If it is a register, add it to the reg list.
448 Operands.insert(Operands.begin()+OpNo, Op);
449 Operands[OpNo].ParentMI = this;
451 if (Operands[OpNo].isReg())
452 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
454 // Re-add all the implicit ops.
455 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
456 assert(Operands[i].isReg() && "Should only be an implicit reg!");
457 Operands[i].AddRegOperandToRegInfo(RegInfo);
460 // Otherwise, we will be reallocating the operand list. Remove all reg
461 // operands from their list, then readd them after the operand list is
463 RemoveRegOperandsFromUseLists();
465 Operands.insert(Operands.begin()+OpNo, Op);
466 Operands[OpNo].ParentMI = this;
468 // Re-add all the operands.
469 AddRegOperandsToUseLists(*RegInfo);
473 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
474 /// fewer operand than it started with.
476 void MachineInstr::RemoveOperand(unsigned OpNo) {
477 assert(OpNo < Operands.size() && "Invalid operand number");
479 // Special case removing the last one.
480 if (OpNo == Operands.size()-1) {
481 // If needed, remove from the reg def/use list.
482 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
483 Operands.back().RemoveRegOperandFromRegInfo();
489 // Otherwise, we are removing an interior operand. If we have reginfo to
490 // update, remove all operands that will be shifted down from their reg lists,
491 // move everything down, then re-add them.
492 MachineRegisterInfo *RegInfo = getRegInfo();
494 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
495 if (Operands[i].isReg())
496 Operands[i].RemoveRegOperandFromRegInfo();
500 Operands.erase(Operands.begin()+OpNo);
503 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
504 if (Operands[i].isReg())
505 Operands[i].AddRegOperandToRegInfo(RegInfo);
510 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
511 /// referencing arbitrary storage.
512 void MachineInstr::addMemOperand(MachineFunction &MF,
513 const MachineMemOperand &MO) {
514 MemOperands.push_back(MO);
517 /// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
518 void MachineInstr::clearMemOperands(MachineFunction &MF) {
523 /// removeFromParent - This method unlinks 'this' from the containing basic
524 /// block, and returns it, but does not delete it.
525 MachineInstr *MachineInstr::removeFromParent() {
526 assert(getParent() && "Not embedded in a basic block!");
527 getParent()->remove(this);
532 /// eraseFromParent - This method unlinks 'this' from the containing basic
533 /// block, and deletes it.
534 void MachineInstr::eraseFromParent() {
535 assert(getParent() && "Not embedded in a basic block!");
536 getParent()->erase(this);
540 /// OperandComplete - Return true if it's illegal to add a new operand
542 bool MachineInstr::OperandsComplete() const {
543 unsigned short NumOperands = TID->getNumOperands();
544 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
545 return true; // Broken: we have all the operands of this instruction!
549 /// getNumExplicitOperands - Returns the number of non-implicit operands.
551 unsigned MachineInstr::getNumExplicitOperands() const {
552 unsigned NumOperands = TID->getNumOperands();
553 if (!TID->isVariadic())
556 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
557 const MachineOperand &MO = getOperand(NumOperands);
558 if (!MO.isRegister() || !MO.isImplicit())
565 /// isLabel - Returns true if the MachineInstr represents a label.
567 bool MachineInstr::isLabel() const {
568 return getOpcode() == TargetInstrInfo::DBG_LABEL ||
569 getOpcode() == TargetInstrInfo::EH_LABEL ||
570 getOpcode() == TargetInstrInfo::GC_LABEL;
573 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
575 bool MachineInstr::isDebugLabel() const {
576 return getOpcode() == TargetInstrInfo::DBG_LABEL;
579 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
580 /// the specific register or -1 if it is not found. It further tightening
581 /// the search criteria to a use that kills the register if isKill is true.
582 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
583 const TargetRegisterInfo *TRI) const {
584 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
585 const MachineOperand &MO = getOperand(i);
586 if (!MO.isRegister() || !MO.isUse())
588 unsigned MOReg = MO.getReg();
593 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
594 TargetRegisterInfo::isPhysicalRegister(Reg) &&
595 TRI->isSubRegister(MOReg, Reg)))
596 if (!isKill || MO.isKill())
602 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
603 /// the specified register or -1 if it is not found. If isDead is true, defs
604 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
605 /// also checks if there is a def of a super-register.
606 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
607 const TargetRegisterInfo *TRI) const {
608 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
609 const MachineOperand &MO = getOperand(i);
610 if (!MO.isRegister() || !MO.isDef())
612 unsigned MOReg = MO.getReg();
615 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
616 TargetRegisterInfo::isPhysicalRegister(Reg) &&
617 TRI->isSubRegister(MOReg, Reg)))
618 if (!isDead || MO.isDead())
624 /// findFirstPredOperandIdx() - Find the index of the first operand in the
625 /// operand list that is used to represent the predicate. It returns -1 if
627 int MachineInstr::findFirstPredOperandIdx() const {
628 const TargetInstrDesc &TID = getDesc();
629 if (TID.isPredicable()) {
630 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
631 if (TID.OpInfo[i].isPredicate())
638 /// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
639 /// check if the register def is a re-definition due to two addr elimination.
640 bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const{
641 const TargetInstrDesc &TID = getDesc();
642 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
643 const MachineOperand &MO = getOperand(i);
644 if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg &&
645 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
651 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
653 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
654 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
655 const MachineOperand &MO = MI->getOperand(i);
656 if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
658 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
659 MachineOperand &MOp = getOperand(j);
660 if (!MOp.isIdenticalTo(MO))
671 /// copyPredicates - Copies predicate operand(s) from MI.
672 void MachineInstr::copyPredicates(const MachineInstr *MI) {
673 const TargetInstrDesc &TID = MI->getDesc();
674 if (!TID.isPredicable())
676 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
677 if (TID.OpInfo[i].isPredicate()) {
678 // Predicated operands must be last operands.
679 addOperand(MI->getOperand(i));
684 /// isSafeToMove - Return true if it is safe to move this instruction. If
685 /// SawStore is set to true, it means that there is a store (or call) between
686 /// the instruction's location and its intended destination.
687 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) {
688 // Ignore stuff that we obviously can't move.
689 if (TID->mayStore() || TID->isCall()) {
693 if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects())
696 // See if this instruction does a load. If so, we have to guarantee that the
697 // loaded value doesn't change between the load and the its intended
698 // destination. The check for isInvariantLoad gives the targe the chance to
699 // classify the load as always returning a constant, e.g. a constant pool
701 if (TID->mayLoad() && !TII->isInvariantLoad(this)) {
702 // Otherwise, this is a real load. If there is a store between the load and
703 // end of block, we can't sink the load.
705 // FIXME: we can't do this transformation until we know that the load is
706 // not volatile, and machineinstrs don't keep this info. :(
714 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
715 /// instruction which defined the specified register instead of copying it.
716 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, unsigned DstReg) {
717 bool SawStore = false;
718 if (!getDesc().isRematerializable() ||
719 !TII->isTriviallyReMaterializable(this) ||
720 !isSafeToMove(TII, SawStore))
722 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
723 MachineOperand &MO = getOperand(i);
724 if (!MO.isRegister())
726 // FIXME: For now, do not remat any instruction with register operands.
727 // Later on, we can loosen the restriction is the register operands have
728 // not been modified between the def and use. Note, this is different from
729 // MachineSink because the code is no longer in two-address form (at least
733 else if (!MO.isDead() && MO.getReg() != DstReg)
739 void MachineInstr::dump() const {
740 cerr << " " << *this;
743 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
744 // Specialize printing if op#0 is definition
745 unsigned StartOp = 0;
746 if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
747 getOperand(0).print(OS, TM);
749 ++StartOp; // Don't print this operand again!
752 OS << getDesc().getName();
754 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
758 getOperand(i).print(OS, TM);
761 if (!memoperands_empty()) {
763 for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(),
764 e = memoperands_end(); i != e; ++i) {
765 const MachineMemOperand &MRO = *i;
766 const Value *V = MRO.getValue();
768 assert((MRO.isLoad() || MRO.isStore()) &&
769 "SV has to be a load, store or both.");
771 if (MRO.isVolatile())
779 OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
783 else if (!V->getName().empty())
785 else if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
786 raw_os_ostream OSS(OS);
791 OS << " + " << MRO.getOffset() << "]";
798 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
799 const TargetRegisterInfo *RegInfo,
800 bool AddIfNotFound) {
801 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
802 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
803 SmallVector<unsigned,4> DeadOps;
804 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
805 MachineOperand &MO = getOperand(i);
806 if (!MO.isRegister() || !MO.isUse())
808 unsigned Reg = MO.getReg();
812 if (Reg == IncomingReg) {
816 if (hasAliases && MO.isKill() &&
817 TargetRegisterInfo::isPhysicalRegister(Reg)) {
818 // A super-register kill already exists.
819 if (RegInfo->isSuperRegister(IncomingReg, Reg))
821 if (RegInfo->isSubRegister(IncomingReg, Reg))
822 DeadOps.push_back(i);
826 // Trim unneeded kill operands.
827 while (!DeadOps.empty()) {
828 unsigned OpIdx = DeadOps.back();
829 if (getOperand(OpIdx).isImplicit())
830 RemoveOperand(OpIdx);
832 getOperand(OpIdx).setIsKill(false);
836 // If not found, this means an alias of one of the operands is killed. Add a
837 // new implicit operand if required.
839 addOperand(MachineOperand::CreateReg(IncomingReg,
848 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
849 const TargetRegisterInfo *RegInfo,
850 bool AddIfNotFound) {
851 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
852 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
853 SmallVector<unsigned,4> DeadOps;
854 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
855 MachineOperand &MO = getOperand(i);
856 if (!MO.isRegister() || !MO.isDef())
858 unsigned Reg = MO.getReg();
859 if (Reg == IncomingReg) {
863 if (hasAliases && MO.isDead() &&
864 TargetRegisterInfo::isPhysicalRegister(Reg)) {
865 // There exists a super-register that's marked dead.
866 if (RegInfo->isSuperRegister(IncomingReg, Reg))
868 if (RegInfo->getSubRegisters(IncomingReg) &&
869 RegInfo->getSuperRegisters(Reg) &&
870 RegInfo->isSubRegister(IncomingReg, Reg))
871 DeadOps.push_back(i);
875 // Trim unneeded dead operands.
876 while (!DeadOps.empty()) {
877 unsigned OpIdx = DeadOps.back();
878 if (getOperand(OpIdx).isImplicit())
879 RemoveOperand(OpIdx);
881 getOperand(OpIdx).setIsDead(false);
885 // If not found, this means an alias of one of the operand is dead. Add a
886 // new implicit operand.
888 addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/,
889 true/*IsImp*/,false/*IsKill*/,