1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Function.h"
17 #include "llvm/InlineAsm.h"
18 #include "llvm/LLVMContext.h"
19 #include "llvm/Metadata.h"
20 #include "llvm/Module.h"
21 #include "llvm/Type.h"
22 #include "llvm/Value.h"
23 #include "llvm/Assembly/Writer.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCSymbol.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Analysis/AliasAnalysis.h"
36 #include "llvm/Analysis/DebugInfo.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/LeakDetector.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/FoldingSet.h"
45 //===----------------------------------------------------------------------===//
46 // MachineOperand Implementation
47 //===----------------------------------------------------------------------===//
49 /// AddRegOperandToRegInfo - Add this register operand to the specified
50 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
51 /// explicitly nulled out.
52 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
53 assert(isReg() && "Can only add reg operand to use lists");
55 // If the reginfo pointer is null, just explicitly null out or next/prev
56 // pointers, to ensure they are not garbage.
58 Contents.Reg.Prev = 0;
59 Contents.Reg.Next = 0;
63 // Otherwise, add this operand to the head of the registers use/def list.
64 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
66 // For SSA values, we prefer to keep the definition at the start of the list.
67 // we do this by skipping over the definition if it is at the head of the
69 if (*Head && (*Head)->isDef())
70 Head = &(*Head)->Contents.Reg.Next;
72 Contents.Reg.Next = *Head;
73 if (Contents.Reg.Next) {
74 assert(getReg() == Contents.Reg.Next->getReg() &&
75 "Different regs on the same list!");
76 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
79 Contents.Reg.Prev = Head;
83 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
84 /// MachineRegisterInfo it is linked with.
85 void MachineOperand::RemoveRegOperandFromRegInfo() {
86 assert(isOnRegUseList() && "Reg operand is not on a use list");
87 // Unlink this from the doubly linked list of operands.
88 MachineOperand *NextOp = Contents.Reg.Next;
89 *Contents.Reg.Prev = NextOp;
91 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
92 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
94 Contents.Reg.Prev = 0;
95 Contents.Reg.Next = 0;
98 void MachineOperand::setReg(unsigned Reg) {
99 if (getReg() == Reg) return; // No change.
101 // Otherwise, we have to change the register. If this operand is embedded
102 // into a machine function, we need to update the old and new register's
104 if (MachineInstr *MI = getParent())
105 if (MachineBasicBlock *MBB = MI->getParent())
106 if (MachineFunction *MF = MBB->getParent()) {
107 RemoveRegOperandFromRegInfo();
108 SmallContents.RegNo = Reg;
109 AddRegOperandToRegInfo(&MF->getRegInfo());
113 // Otherwise, just change the register, no problem. :)
114 SmallContents.RegNo = Reg;
117 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
118 const TargetRegisterInfo &TRI) {
119 assert(TargetRegisterInfo::isVirtualRegister(Reg));
120 if (SubIdx && getSubReg())
121 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
127 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
128 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
130 Reg = TRI.getSubReg(Reg, getSubReg());
131 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
132 // That won't happen in legal code.
138 /// ChangeToImmediate - Replace this operand with a new immediate operand of
139 /// the specified value. If an operand is known to be an immediate already,
140 /// the setImm method should be used.
141 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
142 // If this operand is currently a register operand, and if this is in a
143 // function, deregister the operand from the register's use/def list.
144 if (isReg() && getParent() && getParent()->getParent() &&
145 getParent()->getParent()->getParent())
146 RemoveRegOperandFromRegInfo();
148 OpKind = MO_Immediate;
149 Contents.ImmVal = ImmVal;
152 /// ChangeToRegister - Replace this operand with a new register operand of
153 /// the specified value. If an operand is known to be an register already,
154 /// the setReg method should be used.
155 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
156 bool isKill, bool isDead, bool isUndef,
158 // If this operand is already a register operand, use setReg to update the
159 // register's use/def lists.
161 assert(!isEarlyClobber());
164 // Otherwise, change this to a register and set the reg#.
165 OpKind = MO_Register;
166 SmallContents.RegNo = Reg;
168 // If this operand is embedded in a function, add the operand to the
169 // register's use/def list.
170 if (MachineInstr *MI = getParent())
171 if (MachineBasicBlock *MBB = MI->getParent())
172 if (MachineFunction *MF = MBB->getParent())
173 AddRegOperandToRegInfo(&MF->getRegInfo());
181 IsInternalRead = false;
182 IsEarlyClobber = false;
187 /// isIdenticalTo - Return true if this operand is identical to the specified
189 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
190 if (getType() != Other.getType() ||
191 getTargetFlags() != Other.getTargetFlags())
195 default: llvm_unreachable("Unrecognized operand type");
196 case MachineOperand::MO_Register:
197 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
198 getSubReg() == Other.getSubReg();
199 case MachineOperand::MO_Immediate:
200 return getImm() == Other.getImm();
201 case MachineOperand::MO_CImmediate:
202 return getCImm() == Other.getCImm();
203 case MachineOperand::MO_FPImmediate:
204 return getFPImm() == Other.getFPImm();
205 case MachineOperand::MO_MachineBasicBlock:
206 return getMBB() == Other.getMBB();
207 case MachineOperand::MO_FrameIndex:
208 return getIndex() == Other.getIndex();
209 case MachineOperand::MO_ConstantPoolIndex:
210 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
211 case MachineOperand::MO_JumpTableIndex:
212 return getIndex() == Other.getIndex();
213 case MachineOperand::MO_GlobalAddress:
214 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
215 case MachineOperand::MO_ExternalSymbol:
216 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
217 getOffset() == Other.getOffset();
218 case MachineOperand::MO_BlockAddress:
219 return getBlockAddress() == Other.getBlockAddress();
220 case MachineOperand::MO_MCSymbol:
221 return getMCSymbol() == Other.getMCSymbol();
222 case MachineOperand::MO_Metadata:
223 return getMetadata() == Other.getMetadata();
227 /// print - Print the specified machine operand.
229 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
230 // If the instruction is embedded into a basic block, we can find the
231 // target info for the instruction.
233 if (const MachineInstr *MI = getParent())
234 if (const MachineBasicBlock *MBB = MI->getParent())
235 if (const MachineFunction *MF = MBB->getParent())
236 TM = &MF->getTarget();
237 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
240 case MachineOperand::MO_Register:
241 OS << PrintReg(getReg(), TRI, getSubReg());
243 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
244 isInternalRead() || isEarlyClobber()) {
246 bool NeedComma = false;
248 if (NeedComma) OS << ',';
249 if (isEarlyClobber())
250 OS << "earlyclobber,";
255 } else if (isImplicit()) {
260 if (isKill() || isDead() || isUndef() || isInternalRead()) {
261 if (NeedComma) OS << ',';
272 if (NeedComma) OS << ',';
276 if (isInternalRead()) {
277 if (NeedComma) OS << ',';
285 case MachineOperand::MO_Immediate:
288 case MachineOperand::MO_CImmediate:
289 getCImm()->getValue().print(OS, false);
291 case MachineOperand::MO_FPImmediate:
292 if (getFPImm()->getType()->isFloatTy())
293 OS << getFPImm()->getValueAPF().convertToFloat();
295 OS << getFPImm()->getValueAPF().convertToDouble();
297 case MachineOperand::MO_MachineBasicBlock:
298 OS << "<BB#" << getMBB()->getNumber() << ">";
300 case MachineOperand::MO_FrameIndex:
301 OS << "<fi#" << getIndex() << '>';
303 case MachineOperand::MO_ConstantPoolIndex:
304 OS << "<cp#" << getIndex();
305 if (getOffset()) OS << "+" << getOffset();
308 case MachineOperand::MO_JumpTableIndex:
309 OS << "<jt#" << getIndex() << '>';
311 case MachineOperand::MO_GlobalAddress:
313 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
314 if (getOffset()) OS << "+" << getOffset();
317 case MachineOperand::MO_ExternalSymbol:
318 OS << "<es:" << getSymbolName();
319 if (getOffset()) OS << "+" << getOffset();
322 case MachineOperand::MO_BlockAddress:
324 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
327 case MachineOperand::MO_Metadata:
329 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
332 case MachineOperand::MO_MCSymbol:
333 OS << "<MCSym=" << *getMCSymbol() << '>';
336 llvm_unreachable("Unrecognized operand type");
339 if (unsigned TF = getTargetFlags())
340 OS << "[TF=" << TF << ']';
343 //===----------------------------------------------------------------------===//
344 // MachineMemOperand Implementation
345 //===----------------------------------------------------------------------===//
347 /// getAddrSpace - Return the LLVM IR address space number that this pointer
349 unsigned MachinePointerInfo::getAddrSpace() const {
350 if (V == 0) return 0;
351 return cast<PointerType>(V->getType())->getAddressSpace();
354 /// getConstantPool - Return a MachinePointerInfo record that refers to the
356 MachinePointerInfo MachinePointerInfo::getConstantPool() {
357 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
360 /// getFixedStack - Return a MachinePointerInfo record that refers to the
361 /// the specified FrameIndex.
362 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
363 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
366 MachinePointerInfo MachinePointerInfo::getJumpTable() {
367 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
370 MachinePointerInfo MachinePointerInfo::getGOT() {
371 return MachinePointerInfo(PseudoSourceValue::getGOT());
374 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
375 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
378 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
379 uint64_t s, unsigned int a,
380 const MDNode *TBAAInfo)
381 : PtrInfo(ptrinfo), Size(s),
382 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
384 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
385 "invalid pointer value");
386 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
387 assert((isLoad() || isStore()) && "Not a load/store!");
390 /// Profile - Gather unique data for the object.
392 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
393 ID.AddInteger(getOffset());
395 ID.AddPointer(getValue());
396 ID.AddInteger(Flags);
399 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
400 // The Value and Offset may differ due to CSE. But the flags and size
401 // should be the same.
402 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
403 assert(MMO->getSize() == getSize() && "Size mismatch!");
405 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
406 // Update the alignment value.
407 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
408 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
409 // Also update the base and offset, because the new alignment may
410 // not be applicable with the old ones.
411 PtrInfo = MMO->PtrInfo;
415 /// getAlignment - Return the minimum known alignment in bytes of the
416 /// actual memory reference.
417 uint64_t MachineMemOperand::getAlignment() const {
418 return MinAlign(getBaseAlignment(), getOffset());
421 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
422 assert((MMO.isLoad() || MMO.isStore()) &&
423 "SV has to be a load, store or both.");
425 if (MMO.isVolatile())
434 // Print the address information.
439 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
441 // If the alignment of the memory reference itself differs from the alignment
442 // of the base pointer, print the base alignment explicitly, next to the base
444 if (MMO.getBaseAlignment() != MMO.getAlignment())
445 OS << "(align=" << MMO.getBaseAlignment() << ")";
447 if (MMO.getOffset() != 0)
448 OS << "+" << MMO.getOffset();
451 // Print the alignment of the reference.
452 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
453 MMO.getBaseAlignment() != MMO.getSize())
454 OS << "(align=" << MMO.getAlignment() << ")";
457 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
459 if (TBAAInfo->getNumOperands() > 0)
460 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
466 // Print nontemporal info.
467 if (MMO.isNonTemporal())
468 OS << "(nontemporal)";
473 //===----------------------------------------------------------------------===//
474 // MachineInstr Implementation
475 //===----------------------------------------------------------------------===//
477 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
478 /// MCID NULL and no operands.
479 MachineInstr::MachineInstr()
480 : MCID(0), Flags(0), AsmPrinterFlags(0),
481 MemRefs(0), MemRefsEnd(0),
483 // Make sure that we get added to a machine basicblock
484 LeakDetector::addGarbageObject(this);
487 void MachineInstr::addImplicitDefUseOperands() {
488 if (MCID->ImplicitDefs)
489 for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs)
490 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
491 if (MCID->ImplicitUses)
492 for (const unsigned *ImpUses = MCID->ImplicitUses; *ImpUses; ++ImpUses)
493 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
496 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
497 /// implicit operands. It reserves space for the number of operands specified by
499 MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
500 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
501 MemRefs(0), MemRefsEnd(0), Parent(0) {
502 unsigned NumImplicitOps = 0;
504 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
505 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
507 addImplicitDefUseOperands();
508 // Make sure that we get added to a machine basicblock
509 LeakDetector::addGarbageObject(this);
512 /// MachineInstr ctor - As above, but with a DebugLoc.
513 MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
515 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
516 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
517 unsigned NumImplicitOps = 0;
519 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
520 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
522 addImplicitDefUseOperands();
523 // Make sure that we get added to a machine basicblock
524 LeakDetector::addGarbageObject(this);
527 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
528 /// that the MachineInstr is created and added to the end of the specified
530 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
531 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
532 MemRefs(0), MemRefsEnd(0), Parent(0) {
533 assert(MBB && "Cannot use inserting ctor with null basic block!");
534 unsigned NumImplicitOps =
535 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
536 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
537 addImplicitDefUseOperands();
538 // Make sure that we get added to a machine basicblock
539 LeakDetector::addGarbageObject(this);
540 MBB->push_back(this); // Add instruction to end of basic block!
543 /// MachineInstr ctor - As above, but with a DebugLoc.
545 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
546 const MCInstrDesc &tid)
547 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
548 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
549 assert(MBB && "Cannot use inserting ctor with null basic block!");
550 unsigned NumImplicitOps =
551 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
552 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
553 addImplicitDefUseOperands();
554 // Make sure that we get added to a machine basicblock
555 LeakDetector::addGarbageObject(this);
556 MBB->push_back(this); // Add instruction to end of basic block!
559 /// MachineInstr ctor - Copies MachineInstr arg exactly
561 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
562 : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
563 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
564 Parent(0), debugLoc(MI.getDebugLoc()) {
565 Operands.reserve(MI.getNumOperands());
568 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
569 addOperand(MI.getOperand(i));
571 // Copy all the flags.
574 // Set parent to null.
577 LeakDetector::addGarbageObject(this);
580 MachineInstr::~MachineInstr() {
581 LeakDetector::removeGarbageObject(this);
583 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
584 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
585 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
586 "Reg operand def/use list corrupted");
591 /// getRegInfo - If this instruction is embedded into a MachineFunction,
592 /// return the MachineRegisterInfo object for the current function, otherwise
594 MachineRegisterInfo *MachineInstr::getRegInfo() {
595 if (MachineBasicBlock *MBB = getParent())
596 return &MBB->getParent()->getRegInfo();
600 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
601 /// this instruction from their respective use lists. This requires that the
602 /// operands already be on their use lists.
603 void MachineInstr::RemoveRegOperandsFromUseLists() {
604 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
605 if (Operands[i].isReg())
606 Operands[i].RemoveRegOperandFromRegInfo();
610 /// AddRegOperandsToUseLists - Add all of the register operands in
611 /// this instruction from their respective use lists. This requires that the
612 /// operands not be on their use lists yet.
613 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
614 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
615 if (Operands[i].isReg())
616 Operands[i].AddRegOperandToRegInfo(&RegInfo);
621 /// addOperand - Add the specified operand to the instruction. If it is an
622 /// implicit operand, it is added to the end of the operand list. If it is
623 /// an explicit operand it is added at the end of the explicit operand list
624 /// (before the first implicit operand).
625 void MachineInstr::addOperand(const MachineOperand &Op) {
626 assert(MCID && "Cannot add operands before providing an instr descriptor");
627 bool isImpReg = Op.isReg() && Op.isImplicit();
628 MachineRegisterInfo *RegInfo = getRegInfo();
630 // If the Operands backing store is reallocated, all register operands must
631 // be removed and re-added to RegInfo. It is storing pointers to operands.
632 bool Reallocate = RegInfo &&
633 !Operands.empty() && Operands.size() == Operands.capacity();
635 // Find the insert location for the new operand. Implicit registers go at
636 // the end, everything goes before the implicit regs.
637 unsigned OpNo = Operands.size();
639 // Remove all the implicit operands from RegInfo if they need to be shifted.
640 // FIXME: Allow mixed explicit and implicit operands on inline asm.
641 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
642 // implicit-defs, but they must not be moved around. See the FIXME in
644 if (!isImpReg && !isInlineAsm()) {
645 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
648 Operands[OpNo].RemoveRegOperandFromRegInfo();
652 // OpNo now points as the desired insertion point. Unless this is a variadic
653 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
654 assert((isImpReg || MCID->isVariadic() || OpNo < MCID->getNumOperands()) &&
655 "Trying to add an operand to a machine instr that is already done!");
657 // All operands from OpNo have been removed from RegInfo. If the Operands
658 // backing store needs to be reallocated, we also need to remove any other
659 // register operands.
661 for (unsigned i = 0; i != OpNo; ++i)
662 if (Operands[i].isReg())
663 Operands[i].RemoveRegOperandFromRegInfo();
665 // Insert the new operand at OpNo.
666 Operands.insert(Operands.begin() + OpNo, Op);
667 Operands[OpNo].ParentMI = this;
669 // The Operands backing store has now been reallocated, so we can re-add the
670 // operands before OpNo.
672 for (unsigned i = 0; i != OpNo; ++i)
673 if (Operands[i].isReg())
674 Operands[i].AddRegOperandToRegInfo(RegInfo);
676 // When adding a register operand, tell RegInfo about it.
677 if (Operands[OpNo].isReg()) {
678 // Add the new operand to RegInfo, even when RegInfo is NULL.
679 // This will initialize the linked list pointers.
680 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
681 // If the register operand is flagged as early, mark the operand as such.
682 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
683 Operands[OpNo].setIsEarlyClobber(true);
686 // Re-add all the implicit ops.
688 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
689 assert(Operands[i].isReg() && "Should only be an implicit reg!");
690 Operands[i].AddRegOperandToRegInfo(RegInfo);
695 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
696 /// fewer operand than it started with.
698 void MachineInstr::RemoveOperand(unsigned OpNo) {
699 assert(OpNo < Operands.size() && "Invalid operand number");
701 // Special case removing the last one.
702 if (OpNo == Operands.size()-1) {
703 // If needed, remove from the reg def/use list.
704 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
705 Operands.back().RemoveRegOperandFromRegInfo();
711 // Otherwise, we are removing an interior operand. If we have reginfo to
712 // update, remove all operands that will be shifted down from their reg lists,
713 // move everything down, then re-add them.
714 MachineRegisterInfo *RegInfo = getRegInfo();
716 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
717 if (Operands[i].isReg())
718 Operands[i].RemoveRegOperandFromRegInfo();
722 Operands.erase(Operands.begin()+OpNo);
725 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
726 if (Operands[i].isReg())
727 Operands[i].AddRegOperandToRegInfo(RegInfo);
732 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
733 /// This function should be used only occasionally. The setMemRefs function
734 /// is the primary method for setting up a MachineInstr's MemRefs list.
735 void MachineInstr::addMemOperand(MachineFunction &MF,
736 MachineMemOperand *MO) {
737 mmo_iterator OldMemRefs = MemRefs;
738 mmo_iterator OldMemRefsEnd = MemRefsEnd;
740 size_t NewNum = (MemRefsEnd - MemRefs) + 1;
741 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
742 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
744 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
745 NewMemRefs[NewNum - 1] = MO;
747 MemRefs = NewMemRefs;
748 MemRefsEnd = NewMemRefsEnd;
752 MachineInstr::hasProperty(unsigned MCFlag, QueryType Type) const {
753 if (Type == IgnoreBundle || getOpcode() != TargetOpcode::BUNDLE)
754 return getDesc().getFlags() & (1 << MCFlag);
756 const MachineBasicBlock *MBB = getParent();
757 MachineBasicBlock::const_insn_iterator MII = *this; ++MII;
758 while (MII != MBB->end() && MII->isInsideBundle()) {
759 if (MII->getDesc().getFlags() & (1 << MCFlag)) {
760 if (Type == AnyInBundle)
763 if (Type == AllInBundle)
769 return Type == AllInBundle;
772 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
773 MICheckType Check) const {
774 // If opcodes or number of operands are not the same then the two
775 // instructions are obviously not identical.
776 if (Other->getOpcode() != getOpcode() ||
777 Other->getNumOperands() != getNumOperands())
780 // Check operands to make sure they match.
781 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
782 const MachineOperand &MO = getOperand(i);
783 const MachineOperand &OMO = Other->getOperand(i);
785 if (!MO.isIdenticalTo(OMO))
790 // Clients may or may not want to ignore defs when testing for equality.
791 // For example, machine CSE pass only cares about finding common
792 // subexpressions, so it's safe to ignore virtual register defs.
794 if (Check == IgnoreDefs)
796 else if (Check == IgnoreVRegDefs) {
797 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
798 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
799 if (MO.getReg() != OMO.getReg())
802 if (!MO.isIdenticalTo(OMO))
804 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
808 if (!MO.isIdenticalTo(OMO))
810 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
814 // If DebugLoc does not match then two dbg.values are not identical.
816 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
817 && getDebugLoc() != Other->getDebugLoc())
822 /// removeFromParent - This method unlinks 'this' from the containing basic
823 /// block, and returns it, but does not delete it.
824 MachineInstr *MachineInstr::removeFromParent() {
825 assert(getParent() && "Not embedded in a basic block!");
827 // If it's a bundle then remove the MIs inside the bundle as well.
828 if (getOpcode() == TargetOpcode::BUNDLE) {
829 MachineBasicBlock *MBB = getParent();
830 MachineBasicBlock::insn_iterator MII = *this; ++MII;
831 while (MII != MBB->end() && MII->isInsideBundle()) {
832 MachineInstr *MI = &*MII;
837 getParent()->remove(this);
842 /// eraseFromParent - This method unlinks 'this' from the containing basic
843 /// block, and deletes it.
844 void MachineInstr::eraseFromParent() {
845 assert(getParent() && "Not embedded in a basic block!");
846 // If it's a bundle then remove the MIs inside the bundle as well.
847 if (getOpcode() == TargetOpcode::BUNDLE) {
848 MachineBasicBlock *MBB = getParent();
849 MachineBasicBlock::insn_iterator MII = *this; ++MII;
850 while (MII != MBB->end() && MII->isInsideBundle()) {
851 MachineInstr *MI = &*MII;
856 getParent()->erase(this);
860 /// getNumExplicitOperands - Returns the number of non-implicit operands.
862 unsigned MachineInstr::getNumExplicitOperands() const {
863 unsigned NumOperands = MCID->getNumOperands();
864 if (!MCID->isVariadic())
867 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
868 const MachineOperand &MO = getOperand(i);
869 if (!MO.isReg() || !MO.isImplicit())
875 bool MachineInstr::isStackAligningInlineAsm() const {
877 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
878 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
884 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
885 unsigned *GroupNo) const {
886 assert(isInlineAsm() && "Expected an inline asm instruction");
887 assert(OpIdx < getNumOperands() && "OpIdx out of range");
889 // Ignore queries about the initial operands.
890 if (OpIdx < InlineAsm::MIOp_FirstOperand)
895 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
897 const MachineOperand &FlagMO = getOperand(i);
898 // If we reach the implicit register operands, stop looking.
901 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
902 if (i + NumOps > OpIdx) {
912 const TargetRegisterClass*
913 MachineInstr::getRegClassConstraint(unsigned OpIdx,
914 const TargetInstrInfo *TII,
915 const TargetRegisterInfo *TRI) const {
916 // Most opcodes have fixed constraints in their MCInstrDesc.
918 return TII->getRegClass(getDesc(), OpIdx, TRI);
920 if (!getOperand(OpIdx).isReg())
923 // For tied uses on inline asm, get the constraint from the def.
925 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
928 // Inline asm stores register class constraints in the flag word.
929 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
933 unsigned Flag = getOperand(FlagIdx).getImm();
935 if (InlineAsm::hasRegClassConstraint(Flag, RCID))
936 return TRI->getRegClass(RCID);
938 // Assume that all registers in a memory operand are pointers.
939 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
940 return TRI->getPointerRegClass();
945 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
946 /// the specific register or -1 if it is not found. It further tightens
947 /// the search criteria to a use that kills the register if isKill is true.
948 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
949 const TargetRegisterInfo *TRI) const {
950 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
951 const MachineOperand &MO = getOperand(i);
952 if (!MO.isReg() || !MO.isUse())
954 unsigned MOReg = MO.getReg();
959 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
960 TargetRegisterInfo::isPhysicalRegister(Reg) &&
961 TRI->isSubRegister(MOReg, Reg)))
962 if (!isKill || MO.isKill())
968 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
969 /// indicating if this instruction reads or writes Reg. This also considers
972 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
973 SmallVectorImpl<unsigned> *Ops) const {
974 bool PartDef = false; // Partial redefine.
975 bool FullDef = false; // Full define.
978 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
979 const MachineOperand &MO = getOperand(i);
980 if (!MO.isReg() || MO.getReg() != Reg)
985 Use |= !MO.isUndef();
986 else if (MO.getSubReg() && !MO.isUndef())
987 // A partial <def,undef> doesn't count as reading the register.
992 // A partial redefine uses Reg unless there is also a full define.
993 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
996 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
997 /// the specified register or -1 if it is not found. If isDead is true, defs
998 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
999 /// also checks if there is a def of a super-register.
1001 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1002 const TargetRegisterInfo *TRI) const {
1003 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1004 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1005 const MachineOperand &MO = getOperand(i);
1006 if (!MO.isReg() || !MO.isDef())
1008 unsigned MOReg = MO.getReg();
1009 bool Found = (MOReg == Reg);
1010 if (!Found && TRI && isPhys &&
1011 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1013 Found = TRI->regsOverlap(MOReg, Reg);
1015 Found = TRI->isSubRegister(MOReg, Reg);
1017 if (Found && (!isDead || MO.isDead()))
1023 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1024 /// operand list that is used to represent the predicate. It returns -1 if
1026 int MachineInstr::findFirstPredOperandIdx() const {
1027 assert(getOpcode() != TargetOpcode::BUNDLE &&
1028 "MachineInstr::findFirstPredOperandIdx() can't handle bundles");
1030 // Don't call MCID.findFirstPredOperandIdx() because this variant
1031 // is sometimes called on an instruction that's not yet complete, and
1032 // so the number of operands is less than the MCID indicates. In
1033 // particular, the PTX target does this.
1034 const MCInstrDesc &MCID = getDesc();
1035 if (MCID.isPredicable()) {
1036 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1037 if (MCID.OpInfo[i].isPredicate())
1044 /// isRegTiedToUseOperand - Given the index of a register def operand,
1045 /// check if the register def is tied to a source operand, due to either
1046 /// two-address elimination or inline assembly constraints. Returns the
1047 /// first tied use operand index by reference is UseOpIdx is not null.
1049 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
1050 if (isInlineAsm()) {
1051 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
1052 const MachineOperand &MO = getOperand(DefOpIdx);
1053 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
1055 // Determine the actual operand index that corresponds to this index.
1057 int FlagIdx = findInlineAsmFlagIdx(DefOpIdx, &DefNo);
1061 // Which part of the group is DefOpIdx?
1062 unsigned DefPart = DefOpIdx - (FlagIdx + 1);
1064 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
1066 const MachineOperand &FMO = getOperand(i);
1069 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
1072 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
1075 *UseOpIdx = (unsigned)i + 1 + DefPart;
1082 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
1083 const MCInstrDesc &MCID = getDesc();
1084 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
1085 const MachineOperand &MO = getOperand(i);
1086 if (MO.isReg() && MO.isUse() &&
1087 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
1089 *UseOpIdx = (unsigned)i;
1096 /// isRegTiedToDefOperand - Return true if the operand of the specified index
1097 /// is a register use and it is tied to an def operand. It also returns the def
1098 /// operand index by reference.
1100 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
1101 if (isInlineAsm()) {
1102 const MachineOperand &MO = getOperand(UseOpIdx);
1103 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
1106 // Find the flag operand corresponding to UseOpIdx
1107 int FlagIdx = findInlineAsmFlagIdx(UseOpIdx);
1111 const MachineOperand &UFMO = getOperand(FlagIdx);
1113 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1117 unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1118 // Remember to adjust the index. First operand is asm string, second is
1119 // the HasSideEffects and AlignStack bits, then there is a flag for each.
1121 const MachineOperand &FMO = getOperand(DefIdx);
1122 assert(FMO.isImm());
1123 // Skip over this def.
1124 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1127 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1133 const MCInstrDesc &MCID = getDesc();
1134 if (UseOpIdx >= MCID.getNumOperands())
1136 const MachineOperand &MO = getOperand(UseOpIdx);
1137 if (!MO.isReg() || !MO.isUse())
1139 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
1143 *DefOpIdx = (unsigned)DefIdx;
1147 /// clearKillInfo - Clears kill flags on all operands.
1149 void MachineInstr::clearKillInfo() {
1150 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1151 MachineOperand &MO = getOperand(i);
1152 if (MO.isReg() && MO.isUse())
1153 MO.setIsKill(false);
1157 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1159 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1160 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1161 const MachineOperand &MO = MI->getOperand(i);
1162 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1164 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1165 MachineOperand &MOp = getOperand(j);
1166 if (!MOp.isIdenticalTo(MO))
1177 /// copyPredicates - Copies predicate operand(s) from MI.
1178 void MachineInstr::copyPredicates(const MachineInstr *MI) {
1179 assert(getOpcode() != TargetOpcode::BUNDLE &&
1180 "MachineInstr::copyPredicates() can't handle bundles");
1182 const MCInstrDesc &MCID = MI->getDesc();
1183 if (!MCID.isPredicable())
1185 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1186 if (MCID.OpInfo[i].isPredicate()) {
1187 // Predicated operands must be last operands.
1188 addOperand(MI->getOperand(i));
1193 void MachineInstr::substituteRegister(unsigned FromReg,
1196 const TargetRegisterInfo &RegInfo) {
1197 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1199 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1200 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1201 MachineOperand &MO = getOperand(i);
1202 if (!MO.isReg() || MO.getReg() != FromReg)
1204 MO.substPhysReg(ToReg, RegInfo);
1207 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1208 MachineOperand &MO = getOperand(i);
1209 if (!MO.isReg() || MO.getReg() != FromReg)
1211 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1216 /// isSafeToMove - Return true if it is safe to move this instruction. If
1217 /// SawStore is set to true, it means that there is a store (or call) between
1218 /// the instruction's location and its intended destination.
1219 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1221 bool &SawStore) const {
1222 // Ignore stuff that we obviously can't move.
1223 if (mayStore() || isCall()) {
1228 if (isLabel() || isDebugValue() ||
1229 isTerminator() || hasUnmodeledSideEffects())
1232 // See if this instruction does a load. If so, we have to guarantee that the
1233 // loaded value doesn't change between the load and the its intended
1234 // destination. The check for isInvariantLoad gives the targe the chance to
1235 // classify the load as always returning a constant, e.g. a constant pool
1237 if (mayLoad() && !isInvariantLoad(AA))
1238 // Otherwise, this is a real load. If there is a store between the load and
1239 // end of block, or if the load is volatile, we can't move it.
1240 return !SawStore && !hasVolatileMemoryRef();
1245 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1246 /// instruction which defined the specified register instead of copying it.
1247 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1249 unsigned DstReg) const {
1250 bool SawStore = false;
1251 if (!TII->isTriviallyReMaterializable(this, AA) ||
1252 !isSafeToMove(TII, AA, SawStore))
1254 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1255 const MachineOperand &MO = getOperand(i);
1258 // FIXME: For now, do not remat any instruction with register operands.
1259 // Later on, we can loosen the restriction is the register operands have
1260 // not been modified between the def and use. Note, this is different from
1261 // MachineSink because the code is no longer in two-address form (at least
1265 else if (!MO.isDead() && MO.getReg() != DstReg)
1271 /// hasVolatileMemoryRef - Return true if this instruction may have a
1272 /// volatile memory reference, or if the information describing the
1273 /// memory reference is not available. Return false if it is known to
1274 /// have no volatile memory references.
1275 bool MachineInstr::hasVolatileMemoryRef() const {
1276 // An instruction known never to access memory won't have a volatile access.
1280 !hasUnmodeledSideEffects())
1283 // Otherwise, if the instruction has no memory reference information,
1284 // conservatively assume it wasn't preserved.
1285 if (memoperands_empty())
1288 // Check the memory reference information for volatile references.
1289 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1290 if ((*I)->isVolatile())
1296 /// isInvariantLoad - Return true if this instruction is loading from a
1297 /// location whose value is invariant across the function. For example,
1298 /// loading a value from the constant pool or from the argument area
1299 /// of a function if it does not change. This should only return true of
1300 /// *all* loads the instruction does are invariant (if it does multiple loads).
1301 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1302 // If the instruction doesn't load at all, it isn't an invariant load.
1306 // If the instruction has lost its memoperands, conservatively assume that
1307 // it may not be an invariant load.
1308 if (memoperands_empty())
1311 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1313 for (mmo_iterator I = memoperands_begin(),
1314 E = memoperands_end(); I != E; ++I) {
1315 if ((*I)->isVolatile()) return false;
1316 if ((*I)->isStore()) return false;
1317 if ((*I)->isInvariant()) return true;
1319 if (const Value *V = (*I)->getValue()) {
1320 // A load from a constant PseudoSourceValue is invariant.
1321 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1322 if (PSV->isConstant(MFI))
1324 // If we have an AliasAnalysis, ask it whether the memory is constant.
1325 if (AA && AA->pointsToConstantMemory(
1326 AliasAnalysis::Location(V, (*I)->getSize(),
1327 (*I)->getTBAAInfo())))
1331 // Otherwise assume conservatively.
1335 // Everything checks out.
1339 /// isConstantValuePHI - If the specified instruction is a PHI that always
1340 /// merges together the same virtual register, return the register, otherwise
1342 unsigned MachineInstr::isConstantValuePHI() const {
1345 assert(getNumOperands() >= 3 &&
1346 "It's illegal to have a PHI without source operands");
1348 unsigned Reg = getOperand(1).getReg();
1349 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1350 if (getOperand(i).getReg() != Reg)
1355 bool MachineInstr::hasUnmodeledSideEffects() const {
1356 if (hasProperty(MCID::UnmodeledSideEffects))
1358 if (isInlineAsm()) {
1359 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1360 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1367 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1369 bool MachineInstr::allDefsAreDead() const {
1370 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1371 const MachineOperand &MO = getOperand(i);
1372 if (!MO.isReg() || MO.isUse())
1380 /// copyImplicitOps - Copy implicit register operands from specified
1381 /// instruction to this instruction.
1382 void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1383 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1385 const MachineOperand &MO = MI->getOperand(i);
1386 if (MO.isReg() && MO.isImplicit())
1391 void MachineInstr::dump() const {
1392 dbgs() << " " << *this;
1395 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1396 raw_ostream &CommentOS) {
1397 const LLVMContext &Ctx = MF->getFunction()->getContext();
1398 if (!DL.isUnknown()) { // Print source line info.
1399 DIScope Scope(DL.getScope(Ctx));
1400 // Omit the directory, because it's likely to be long and uninteresting.
1402 CommentOS << Scope.getFilename();
1404 CommentOS << "<unknown>";
1405 CommentOS << ':' << DL.getLine();
1406 if (DL.getCol() != 0)
1407 CommentOS << ':' << DL.getCol();
1408 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1409 if (!InlinedAtDL.isUnknown()) {
1410 CommentOS << " @[ ";
1411 printDebugLoc(InlinedAtDL, MF, CommentOS);
1417 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1418 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1419 const MachineFunction *MF = 0;
1420 const MachineRegisterInfo *MRI = 0;
1421 if (const MachineBasicBlock *MBB = getParent()) {
1422 MF = MBB->getParent();
1424 TM = &MF->getTarget();
1426 MRI = &MF->getRegInfo();
1429 // Save a list of virtual registers.
1430 SmallVector<unsigned, 8> VirtRegs;
1432 // Print explicitly defined operands on the left of an assignment syntax.
1433 unsigned StartOp = 0, e = getNumOperands();
1434 for (; StartOp < e && getOperand(StartOp).isReg() &&
1435 getOperand(StartOp).isDef() &&
1436 !getOperand(StartOp).isImplicit();
1438 if (StartOp != 0) OS << ", ";
1439 getOperand(StartOp).print(OS, TM);
1440 unsigned Reg = getOperand(StartOp).getReg();
1441 if (TargetRegisterInfo::isVirtualRegister(Reg))
1442 VirtRegs.push_back(Reg);
1448 // Print the opcode name.
1449 OS << getDesc().getName();
1451 // Print the rest of the operands.
1452 bool OmittedAnyCallClobbers = false;
1453 bool FirstOp = true;
1454 unsigned AsmDescOp = ~0u;
1455 unsigned AsmOpCount = 0;
1457 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1458 // Print asm string.
1460 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1462 // Print HasSideEffects, IsAlignStack
1463 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1464 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1465 OS << " [sideeffect]";
1466 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1467 OS << " [alignstack]";
1469 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1474 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1475 const MachineOperand &MO = getOperand(i);
1477 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1478 VirtRegs.push_back(MO.getReg());
1480 // Omit call-clobbered registers which aren't used anywhere. This makes
1481 // call instructions much less noisy on targets where calls clobber lots
1482 // of registers. Don't rely on MO.isDead() because we may be called before
1483 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1484 if (MF && isCall() &&
1485 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1486 unsigned Reg = MO.getReg();
1487 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1488 const MachineRegisterInfo &MRI = MF->getRegInfo();
1489 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1490 bool HasAliasLive = false;
1491 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1492 unsigned AliasReg = *Alias; ++Alias)
1493 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1494 HasAliasLive = true;
1497 if (!HasAliasLive) {
1498 OmittedAnyCallClobbers = true;
1505 if (FirstOp) FirstOp = false; else OS << ",";
1507 if (i < getDesc().NumOperands) {
1508 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1509 if (MCOI.isPredicate())
1511 if (MCOI.isOptionalDef())
1514 if (isDebugValue() && MO.isMetadata()) {
1515 // Pretty print DBG_VALUE instructions.
1516 const MDNode *MD = MO.getMetadata();
1517 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1518 OS << "!\"" << MDS->getString() << '\"';
1521 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1522 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1523 } else if (i == AsmDescOp && MO.isImm()) {
1524 // Pretty print the inline asm operand descriptor.
1525 OS << '$' << AsmOpCount++;
1526 unsigned Flag = MO.getImm();
1527 switch (InlineAsm::getKind(Flag)) {
1528 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1529 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1530 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1531 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1532 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1533 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1534 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1538 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1540 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1542 OS << ":RC" << RCID;
1545 unsigned TiedTo = 0;
1546 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1547 OS << " tiedto:$" << TiedTo;
1551 // Compute the index of the next operand descriptor.
1552 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1557 // Briefly indicate whether any call clobbers were omitted.
1558 if (OmittedAnyCallClobbers) {
1559 if (!FirstOp) OS << ",";
1563 bool HaveSemi = false;
1565 if (!HaveSemi) OS << ";"; HaveSemi = true;
1568 if (Flags & FrameSetup)
1572 if (!memoperands_empty()) {
1573 if (!HaveSemi) OS << ";"; HaveSemi = true;
1576 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1579 if (llvm::next(i) != e)
1584 // Print the regclass of any virtual registers encountered.
1585 if (MRI && !VirtRegs.empty()) {
1586 if (!HaveSemi) OS << ";"; HaveSemi = true;
1587 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1588 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1589 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1590 for (unsigned j = i+1; j != VirtRegs.size();) {
1591 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1595 if (VirtRegs[i] != VirtRegs[j])
1596 OS << "," << PrintReg(VirtRegs[j]);
1597 VirtRegs.erase(VirtRegs.begin()+j);
1602 // Print debug location information.
1603 if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1604 if (!HaveSemi) OS << ";"; HaveSemi = true;
1605 DIVariable DV(getOperand(e - 1).getMetadata());
1606 OS << " line no:" << DV.getLineNumber();
1607 if (MDNode *InlinedAt = DV.getInlinedAt()) {
1608 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1609 if (!InlinedAtDL.isUnknown()) {
1610 OS << " inlined @[ ";
1611 printDebugLoc(InlinedAtDL, MF, OS);
1615 } else if (!debugLoc.isUnknown() && MF) {
1616 if (!HaveSemi) OS << ";"; HaveSemi = true;
1618 printDebugLoc(debugLoc, MF, OS);
1624 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1625 const TargetRegisterInfo *RegInfo,
1626 bool AddIfNotFound) {
1627 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1628 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1630 SmallVector<unsigned,4> DeadOps;
1631 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1632 MachineOperand &MO = getOperand(i);
1633 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1635 unsigned Reg = MO.getReg();
1639 if (Reg == IncomingReg) {
1642 // The register is already marked kill.
1644 if (isPhysReg && isRegTiedToDefOperand(i))
1645 // Two-address uses of physregs must not be marked kill.
1650 } else if (hasAliases && MO.isKill() &&
1651 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1652 // A super-register kill already exists.
1653 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1655 if (RegInfo->isSubRegister(IncomingReg, Reg))
1656 DeadOps.push_back(i);
1660 // Trim unneeded kill operands.
1661 while (!DeadOps.empty()) {
1662 unsigned OpIdx = DeadOps.back();
1663 if (getOperand(OpIdx).isImplicit())
1664 RemoveOperand(OpIdx);
1666 getOperand(OpIdx).setIsKill(false);
1670 // If not found, this means an alias of one of the operands is killed. Add a
1671 // new implicit operand if required.
1672 if (!Found && AddIfNotFound) {
1673 addOperand(MachineOperand::CreateReg(IncomingReg,
1682 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1683 const TargetRegisterInfo *RegInfo,
1684 bool AddIfNotFound) {
1685 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1686 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1688 SmallVector<unsigned,4> DeadOps;
1689 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1690 MachineOperand &MO = getOperand(i);
1691 if (!MO.isReg() || !MO.isDef())
1693 unsigned Reg = MO.getReg();
1697 if (Reg == IncomingReg) {
1700 } else if (hasAliases && MO.isDead() &&
1701 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1702 // There exists a super-register that's marked dead.
1703 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1705 if (RegInfo->getSubRegisters(IncomingReg) &&
1706 RegInfo->getSuperRegisters(Reg) &&
1707 RegInfo->isSubRegister(IncomingReg, Reg))
1708 DeadOps.push_back(i);
1712 // Trim unneeded dead operands.
1713 while (!DeadOps.empty()) {
1714 unsigned OpIdx = DeadOps.back();
1715 if (getOperand(OpIdx).isImplicit())
1716 RemoveOperand(OpIdx);
1718 getOperand(OpIdx).setIsDead(false);
1722 // If not found, this means an alias of one of the operands is dead. Add a
1723 // new implicit operand if required.
1724 if (Found || !AddIfNotFound)
1727 addOperand(MachineOperand::CreateReg(IncomingReg,
1735 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1736 const TargetRegisterInfo *RegInfo) {
1737 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1738 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1742 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1743 const MachineOperand &MO = getOperand(i);
1744 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1745 MO.getSubReg() == 0)
1749 addOperand(MachineOperand::CreateReg(IncomingReg,
1754 void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
1755 const TargetRegisterInfo &TRI) {
1756 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1757 MachineOperand &MO = getOperand(i);
1758 if (!MO.isReg() || !MO.isDef()) continue;
1759 unsigned Reg = MO.getReg();
1760 if (Reg == 0) continue;
1762 for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
1763 E = UsedRegs.end(); I != E; ++I)
1764 if (TRI.regsOverlap(*I, Reg)) {
1768 // If there are no uses, including partial uses, the def is dead.
1769 if (Dead) MO.setIsDead();
1774 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1775 unsigned Hash = MI->getOpcode() * 37;
1776 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1777 const MachineOperand &MO = MI->getOperand(i);
1778 uint64_t Key = (uint64_t)MO.getType() << 32;
1779 switch (MO.getType()) {
1781 case MachineOperand::MO_Register:
1782 if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1783 continue; // Skip virtual register defs.
1786 case MachineOperand::MO_Immediate:
1789 case MachineOperand::MO_FrameIndex:
1790 case MachineOperand::MO_ConstantPoolIndex:
1791 case MachineOperand::MO_JumpTableIndex:
1792 Key |= MO.getIndex();
1794 case MachineOperand::MO_MachineBasicBlock:
1795 Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1797 case MachineOperand::MO_GlobalAddress:
1798 Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1800 case MachineOperand::MO_BlockAddress:
1801 Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1803 case MachineOperand::MO_MCSymbol:
1804 Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1807 Key += ~(Key << 32);
1809 Key += ~(Key << 13);
1813 Key += ~(Key << 27);
1815 Hash = (unsigned)Key + Hash * 37;
1820 void MachineInstr::emitError(StringRef Msg) const {
1821 // Find the source location cookie.
1822 unsigned LocCookie = 0;
1823 const MDNode *LocMD = 0;
1824 for (unsigned i = getNumOperands(); i != 0; --i) {
1825 if (getOperand(i-1).isMetadata() &&
1826 (LocMD = getOperand(i-1).getMetadata()) &&
1827 LocMD->getNumOperands() != 0) {
1828 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1829 LocCookie = CI->getZExtValue();
1835 if (const MachineBasicBlock *MBB = getParent())
1836 if (const MachineFunction *MF = MBB->getParent())
1837 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1838 report_fatal_error(Msg);