1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/ADT/FoldingSet.h"
16 #include "llvm/ADT/Hashing.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/Assembly/Writer.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/DebugInfo.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/InlineAsm.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/IR/Metadata.h"
31 #include "llvm/IR/Module.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/IR/Value.h"
34 #include "llvm/MC/MCInstrDesc.h"
35 #include "llvm/MC/MCSymbol.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/LeakDetector.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetRegisterInfo.h"
46 //===----------------------------------------------------------------------===//
47 // MachineOperand Implementation
48 //===----------------------------------------------------------------------===//
50 void MachineOperand::setReg(unsigned Reg) {
51 if (getReg() == Reg) return; // No change.
53 // Otherwise, we have to change the register. If this operand is embedded
54 // into a machine function, we need to update the old and new register's
56 if (MachineInstr *MI = getParent())
57 if (MachineBasicBlock *MBB = MI->getParent())
58 if (MachineFunction *MF = MBB->getParent()) {
59 MachineRegisterInfo &MRI = MF->getRegInfo();
60 MRI.removeRegOperandFromUseList(this);
61 SmallContents.RegNo = Reg;
62 MRI.addRegOperandToUseList(this);
66 // Otherwise, just change the register, no problem. :)
67 SmallContents.RegNo = Reg;
70 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
71 const TargetRegisterInfo &TRI) {
72 assert(TargetRegisterInfo::isVirtualRegister(Reg));
73 if (SubIdx && getSubReg())
74 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
80 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
81 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
83 Reg = TRI.getSubReg(Reg, getSubReg());
84 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
85 // That won't happen in legal code.
91 /// Change a def to a use, or a use to a def.
92 void MachineOperand::setIsDef(bool Val) {
93 assert(isReg() && "Wrong MachineOperand accessor");
94 assert((!Val || !isDebug()) && "Marking a debug operation as def");
97 // MRI may keep uses and defs in different list positions.
98 if (MachineInstr *MI = getParent())
99 if (MachineBasicBlock *MBB = MI->getParent())
100 if (MachineFunction *MF = MBB->getParent()) {
101 MachineRegisterInfo &MRI = MF->getRegInfo();
102 MRI.removeRegOperandFromUseList(this);
104 MRI.addRegOperandToUseList(this);
110 /// ChangeToImmediate - Replace this operand with a new immediate operand of
111 /// the specified value. If an operand is known to be an immediate already,
112 /// the setImm method should be used.
113 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
114 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
115 // If this operand is currently a register operand, and if this is in a
116 // function, deregister the operand from the register's use/def list.
117 if (isReg() && isOnRegUseList())
118 if (MachineInstr *MI = getParent())
119 if (MachineBasicBlock *MBB = MI->getParent())
120 if (MachineFunction *MF = MBB->getParent())
121 MF->getRegInfo().removeRegOperandFromUseList(this);
123 OpKind = MO_Immediate;
124 Contents.ImmVal = ImmVal;
127 /// ChangeToRegister - Replace this operand with a new register operand of
128 /// the specified value. If an operand is known to be an register already,
129 /// the setReg method should be used.
130 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
131 bool isKill, bool isDead, bool isUndef,
133 MachineRegisterInfo *RegInfo = 0;
134 if (MachineInstr *MI = getParent())
135 if (MachineBasicBlock *MBB = MI->getParent())
136 if (MachineFunction *MF = MBB->getParent())
137 RegInfo = &MF->getRegInfo();
138 // If this operand is already a register operand, remove it from the
139 // register's use/def lists.
140 bool WasReg = isReg();
141 if (RegInfo && WasReg)
142 RegInfo->removeRegOperandFromUseList(this);
144 // Change this to a register and set the reg#.
145 OpKind = MO_Register;
146 SmallContents.RegNo = Reg;
153 IsInternalRead = false;
154 IsEarlyClobber = false;
156 // Ensure isOnRegUseList() returns false.
157 Contents.Reg.Prev = 0;
158 // Preserve the tie when the operand was already a register.
162 // If this operand is embedded in a function, add the operand to the
163 // register's use/def list.
165 RegInfo->addRegOperandToUseList(this);
168 /// isIdenticalTo - Return true if this operand is identical to the specified
169 /// operand. Note that this should stay in sync with the hash_value overload
171 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
172 if (getType() != Other.getType() ||
173 getTargetFlags() != Other.getTargetFlags())
177 case MachineOperand::MO_Register:
178 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
179 getSubReg() == Other.getSubReg();
180 case MachineOperand::MO_Immediate:
181 return getImm() == Other.getImm();
182 case MachineOperand::MO_CImmediate:
183 return getCImm() == Other.getCImm();
184 case MachineOperand::MO_FPImmediate:
185 return getFPImm() == Other.getFPImm();
186 case MachineOperand::MO_MachineBasicBlock:
187 return getMBB() == Other.getMBB();
188 case MachineOperand::MO_FrameIndex:
189 return getIndex() == Other.getIndex();
190 case MachineOperand::MO_ConstantPoolIndex:
191 case MachineOperand::MO_TargetIndex:
192 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
193 case MachineOperand::MO_JumpTableIndex:
194 return getIndex() == Other.getIndex();
195 case MachineOperand::MO_GlobalAddress:
196 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
197 case MachineOperand::MO_ExternalSymbol:
198 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
199 getOffset() == Other.getOffset();
200 case MachineOperand::MO_BlockAddress:
201 return getBlockAddress() == Other.getBlockAddress() &&
202 getOffset() == Other.getOffset();
203 case MO_RegisterMask:
204 return getRegMask() == Other.getRegMask();
205 case MachineOperand::MO_MCSymbol:
206 return getMCSymbol() == Other.getMCSymbol();
207 case MachineOperand::MO_Metadata:
208 return getMetadata() == Other.getMetadata();
210 llvm_unreachable("Invalid machine operand type");
213 // Note: this must stay exactly in sync with isIdenticalTo above.
214 hash_code llvm::hash_value(const MachineOperand &MO) {
215 switch (MO.getType()) {
216 case MachineOperand::MO_Register:
217 // Register operands don't have target flags.
218 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
219 case MachineOperand::MO_Immediate:
220 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
221 case MachineOperand::MO_CImmediate:
222 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
223 case MachineOperand::MO_FPImmediate:
224 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
225 case MachineOperand::MO_MachineBasicBlock:
226 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
227 case MachineOperand::MO_FrameIndex:
228 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
229 case MachineOperand::MO_ConstantPoolIndex:
230 case MachineOperand::MO_TargetIndex:
231 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
233 case MachineOperand::MO_JumpTableIndex:
234 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
235 case MachineOperand::MO_ExternalSymbol:
236 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
238 case MachineOperand::MO_GlobalAddress:
239 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
241 case MachineOperand::MO_BlockAddress:
242 return hash_combine(MO.getType(), MO.getTargetFlags(),
243 MO.getBlockAddress(), MO.getOffset());
244 case MachineOperand::MO_RegisterMask:
245 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
246 case MachineOperand::MO_Metadata:
247 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
248 case MachineOperand::MO_MCSymbol:
249 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
251 llvm_unreachable("Invalid machine operand type");
254 /// print - Print the specified machine operand.
256 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
257 // If the instruction is embedded into a basic block, we can find the
258 // target info for the instruction.
260 if (const MachineInstr *MI = getParent())
261 if (const MachineBasicBlock *MBB = MI->getParent())
262 if (const MachineFunction *MF = MBB->getParent())
263 TM = &MF->getTarget();
264 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
267 case MachineOperand::MO_Register:
268 OS << PrintReg(getReg(), TRI, getSubReg());
270 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
271 isInternalRead() || isEarlyClobber() || isTied()) {
273 bool NeedComma = false;
275 if (NeedComma) OS << ',';
276 if (isEarlyClobber())
277 OS << "earlyclobber,";
282 // <def,read-undef> only makes sense when getSubReg() is set.
283 // Don't clutter the output otherwise.
284 if (isUndef() && getSubReg())
286 } else if (isImplicit()) {
292 if (NeedComma) OS << ',';
297 if (NeedComma) OS << ',';
301 if (isUndef() && isUse()) {
302 if (NeedComma) OS << ',';
306 if (isInternalRead()) {
307 if (NeedComma) OS << ',';
312 if (NeedComma) OS << ',';
315 OS << unsigned(TiedTo - 1);
321 case MachineOperand::MO_Immediate:
324 case MachineOperand::MO_CImmediate:
325 getCImm()->getValue().print(OS, false);
327 case MachineOperand::MO_FPImmediate:
328 if (getFPImm()->getType()->isFloatTy())
329 OS << getFPImm()->getValueAPF().convertToFloat();
331 OS << getFPImm()->getValueAPF().convertToDouble();
333 case MachineOperand::MO_MachineBasicBlock:
334 OS << "<BB#" << getMBB()->getNumber() << ">";
336 case MachineOperand::MO_FrameIndex:
337 OS << "<fi#" << getIndex() << '>';
339 case MachineOperand::MO_ConstantPoolIndex:
340 OS << "<cp#" << getIndex();
341 if (getOffset()) OS << "+" << getOffset();
344 case MachineOperand::MO_TargetIndex:
345 OS << "<ti#" << getIndex();
346 if (getOffset()) OS << "+" << getOffset();
349 case MachineOperand::MO_JumpTableIndex:
350 OS << "<jt#" << getIndex() << '>';
352 case MachineOperand::MO_GlobalAddress:
354 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
355 if (getOffset()) OS << "+" << getOffset();
358 case MachineOperand::MO_ExternalSymbol:
359 OS << "<es:" << getSymbolName();
360 if (getOffset()) OS << "+" << getOffset();
363 case MachineOperand::MO_BlockAddress:
365 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
366 if (getOffset()) OS << "+" << getOffset();
369 case MachineOperand::MO_RegisterMask:
372 case MachineOperand::MO_Metadata:
374 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
377 case MachineOperand::MO_MCSymbol:
378 OS << "<MCSym=" << *getMCSymbol() << '>';
382 if (unsigned TF = getTargetFlags())
383 OS << "[TF=" << TF << ']';
386 //===----------------------------------------------------------------------===//
387 // MachineMemOperand Implementation
388 //===----------------------------------------------------------------------===//
390 /// getAddrSpace - Return the LLVM IR address space number that this pointer
392 unsigned MachinePointerInfo::getAddrSpace() const {
393 if (V == 0) return 0;
394 return cast<PointerType>(V->getType())->getAddressSpace();
397 /// getConstantPool - Return a MachinePointerInfo record that refers to the
399 MachinePointerInfo MachinePointerInfo::getConstantPool() {
400 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
403 /// getFixedStack - Return a MachinePointerInfo record that refers to the
404 /// the specified FrameIndex.
405 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
406 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
409 MachinePointerInfo MachinePointerInfo::getJumpTable() {
410 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
413 MachinePointerInfo MachinePointerInfo::getGOT() {
414 return MachinePointerInfo(PseudoSourceValue::getGOT());
417 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
418 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
421 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
422 uint64_t s, unsigned int a,
423 const MDNode *TBAAInfo,
424 const MDNode *Ranges)
425 : PtrInfo(ptrinfo), Size(s),
426 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
427 TBAAInfo(TBAAInfo), Ranges(Ranges) {
428 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
429 "invalid pointer value");
430 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
431 assert((isLoad() || isStore()) && "Not a load/store!");
434 /// Profile - Gather unique data for the object.
436 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
437 ID.AddInteger(getOffset());
439 ID.AddPointer(getValue());
440 ID.AddInteger(Flags);
443 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
444 // The Value and Offset may differ due to CSE. But the flags and size
445 // should be the same.
446 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
447 assert(MMO->getSize() == getSize() && "Size mismatch!");
449 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
450 // Update the alignment value.
451 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
452 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
453 // Also update the base and offset, because the new alignment may
454 // not be applicable with the old ones.
455 PtrInfo = MMO->PtrInfo;
459 /// getAlignment - Return the minimum known alignment in bytes of the
460 /// actual memory reference.
461 uint64_t MachineMemOperand::getAlignment() const {
462 return MinAlign(getBaseAlignment(), getOffset());
465 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
466 assert((MMO.isLoad() || MMO.isStore()) &&
467 "SV has to be a load, store or both.");
469 if (MMO.isVolatile())
478 // Print the address information.
483 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
485 // If the alignment of the memory reference itself differs from the alignment
486 // of the base pointer, print the base alignment explicitly, next to the base
488 if (MMO.getBaseAlignment() != MMO.getAlignment())
489 OS << "(align=" << MMO.getBaseAlignment() << ")";
491 if (MMO.getOffset() != 0)
492 OS << "+" << MMO.getOffset();
495 // Print the alignment of the reference.
496 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
497 MMO.getBaseAlignment() != MMO.getSize())
498 OS << "(align=" << MMO.getAlignment() << ")";
501 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
503 if (TBAAInfo->getNumOperands() > 0)
504 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
510 // Print nontemporal info.
511 if (MMO.isNonTemporal())
512 OS << "(nontemporal)";
517 //===----------------------------------------------------------------------===//
518 // MachineInstr Implementation
519 //===----------------------------------------------------------------------===//
521 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
522 if (MCID->ImplicitDefs)
523 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
524 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
525 if (MCID->ImplicitUses)
526 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
527 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
530 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
531 /// implicit operands. It reserves space for the number of operands specified by
533 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
534 const DebugLoc dl, bool NoImp)
535 : MCID(&tid), Parent(0), Operands(0), NumOperands(0),
536 Flags(0), AsmPrinterFlags(0),
537 NumMemRefs(0), MemRefs(0), debugLoc(dl) {
538 // Reserve space for the expected number of operands.
539 if (unsigned NumOps = MCID->getNumOperands() +
540 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
541 CapOperands = OperandCapacity::get(NumOps);
542 Operands = MF.allocateOperandArray(CapOperands);
546 addImplicitDefUseOperands(MF);
547 // Make sure that we get added to a machine basicblock
548 LeakDetector::addGarbageObject(this);
551 /// MachineInstr ctor - Copies MachineInstr arg exactly
553 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
554 : MCID(&MI.getDesc()), Parent(0), Operands(0), NumOperands(0),
555 Flags(0), AsmPrinterFlags(0),
556 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
557 debugLoc(MI.getDebugLoc()) {
558 CapOperands = OperandCapacity::get(MI.getNumOperands());
559 Operands = MF.allocateOperandArray(CapOperands);
562 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
563 addOperand(MF, MI.getOperand(i));
565 // Copy all the sensible flags.
568 // Set parent to null.
571 LeakDetector::addGarbageObject(this);
574 MachineInstr::~MachineInstr() {
575 LeakDetector::removeGarbageObject(this);
577 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
578 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
579 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
580 "Reg operand def/use list corrupted");
585 /// getRegInfo - If this instruction is embedded into a MachineFunction,
586 /// return the MachineRegisterInfo object for the current function, otherwise
588 MachineRegisterInfo *MachineInstr::getRegInfo() {
589 if (MachineBasicBlock *MBB = getParent())
590 return &MBB->getParent()->getRegInfo();
594 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
595 /// this instruction from their respective use lists. This requires that the
596 /// operands already be on their use lists.
597 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
598 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
599 if (Operands[i].isReg())
600 MRI.removeRegOperandFromUseList(&Operands[i]);
603 /// AddRegOperandsToUseLists - Add all of the register operands in
604 /// this instruction from their respective use lists. This requires that the
605 /// operands not be on their use lists yet.
606 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
607 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
608 if (Operands[i].isReg())
609 MRI.addRegOperandToUseList(&Operands[i]);
612 void MachineInstr::addOperand(const MachineOperand &Op) {
613 MachineBasicBlock *MBB = getParent();
614 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
615 MachineFunction *MF = MBB->getParent();
616 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
620 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
621 /// ranges. If MRI is non-null also update use-def chains.
622 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
623 unsigned NumOps, MachineRegisterInfo *MRI) {
625 return MRI->moveOperands(Dst, Src, NumOps);
627 // Here it would be convenient to call memmove, so that isn't allowed because
628 // MachineOperand has a constructor and so isn't a POD type.
630 for (unsigned i = 0; i != NumOps; ++i)
631 new (Dst + i) MachineOperand(Src[i]);
633 for (unsigned i = NumOps; i ; --i)
634 new (Dst + i - 1) MachineOperand(Src[i - 1]);
637 /// addOperand - Add the specified operand to the instruction. If it is an
638 /// implicit operand, it is added to the end of the operand list. If it is
639 /// an explicit operand it is added at the end of the explicit operand list
640 /// (before the first implicit operand).
641 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
642 assert(MCID && "Cannot add operands before providing an instr descriptor");
644 // Check if we're adding one of our existing operands.
645 if (&Op >= Operands && &Op < Operands + NumOperands) {
646 // This is unusual: MI->addOperand(MI->getOperand(i)).
647 // If adding Op requires reallocating or moving existing operands around,
648 // the Op reference could go stale. Support it by copying Op.
649 MachineOperand CopyOp(Op);
650 return addOperand(MF, CopyOp);
653 // Find the insert location for the new operand. Implicit registers go at
654 // the end, everything else goes before the implicit regs.
656 // FIXME: Allow mixed explicit and implicit operands on inline asm.
657 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
658 // implicit-defs, but they must not be moved around. See the FIXME in
660 unsigned OpNo = getNumOperands();
661 bool isImpReg = Op.isReg() && Op.isImplicit();
662 if (!isImpReg && !isInlineAsm()) {
663 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
665 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
669 // OpNo now points as the desired insertion point. Unless this is a variadic
670 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
671 // RegMask operands go between the explicit and implicit operands.
672 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
673 OpNo < MCID->getNumOperands()) &&
674 "Trying to add an operand to a machine instr that is already done!");
676 MachineRegisterInfo *MRI = getRegInfo();
678 // Determine if the Operands array needs to be reallocated.
679 // Save the old capacity and operand array.
680 OperandCapacity OldCap = CapOperands;
681 MachineOperand *OldOperands = Operands;
682 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
683 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
684 Operands = MF.allocateOperandArray(CapOperands);
685 // Move the operands before the insertion point.
687 moveOperands(Operands, OldOperands, OpNo, MRI);
690 // Move the operands following the insertion point.
691 if (OpNo != NumOperands)
692 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
696 // Deallocate the old operand array.
697 if (OldOperands != Operands && OldOperands)
698 MF.deallocateOperandArray(OldCap, OldOperands);
700 // Copy Op into place. It still needs to be inserted into the MRI use lists.
701 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
702 NewMO->ParentMI = this;
704 // When adding a register operand, tell MRI about it.
705 if (NewMO->isReg()) {
706 // Ensure isOnRegUseList() returns false, regardless of Op's status.
707 NewMO->Contents.Reg.Prev = 0;
708 // Ignore existing ties. This is not a property that can be copied.
710 // Add the new operand to MRI, but only for instructions in an MBB.
712 MRI->addRegOperandToUseList(NewMO);
713 // The MCID operand information isn't accurate until we start adding
714 // explicit operands. The implicit operands are added first, then the
715 // explicits are inserted before them.
717 // Tie uses to defs as indicated in MCInstrDesc.
718 if (NewMO->isUse()) {
719 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
721 tieOperands(DefIdx, OpNo);
723 // If the register operand is flagged as early, mark the operand as such.
724 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
725 NewMO->setIsEarlyClobber(true);
730 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
731 /// fewer operand than it started with.
733 void MachineInstr::RemoveOperand(unsigned OpNo) {
734 assert(OpNo < getNumOperands() && "Invalid operand number");
735 untieRegOperand(OpNo);
738 // Moving tied operands would break the ties.
739 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
740 if (Operands[i].isReg())
741 assert(!Operands[i].isTied() && "Cannot move tied operands");
744 MachineRegisterInfo *MRI = getRegInfo();
745 if (MRI && Operands[OpNo].isReg())
746 MRI->removeRegOperandFromUseList(Operands + OpNo);
748 // Don't call the MachineOperand destructor. A lot of this code depends on
749 // MachineOperand having a trivial destructor anyway, and adding a call here
750 // wouldn't make it 'destructor-correct'.
752 if (unsigned N = NumOperands - 1 - OpNo)
753 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
757 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
758 /// This function should be used only occasionally. The setMemRefs function
759 /// is the primary method for setting up a MachineInstr's MemRefs list.
760 void MachineInstr::addMemOperand(MachineFunction &MF,
761 MachineMemOperand *MO) {
762 mmo_iterator OldMemRefs = MemRefs;
763 uint16_t OldNumMemRefs = NumMemRefs;
765 uint16_t NewNum = NumMemRefs + 1;
766 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
768 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
769 NewMemRefs[NewNum - 1] = MO;
771 MemRefs = NewMemRefs;
775 bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
776 const MachineBasicBlock *MBB = getParent();
777 MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
778 while (MII != MBB->end() && MII->isInsideBundle()) {
779 if (MII->getDesc().getFlags() & Mask) {
780 if (Type == AnyInBundle)
783 if (Type == AllInBundle)
789 return Type == AllInBundle;
792 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
793 MICheckType Check) const {
794 // If opcodes or number of operands are not the same then the two
795 // instructions are obviously not identical.
796 if (Other->getOpcode() != getOpcode() ||
797 Other->getNumOperands() != getNumOperands())
801 // Both instructions are bundles, compare MIs inside the bundle.
802 MachineBasicBlock::const_instr_iterator I1 = *this;
803 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
804 MachineBasicBlock::const_instr_iterator I2 = *Other;
805 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
806 while (++I1 != E1 && I1->isInsideBundle()) {
808 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
813 // Check operands to make sure they match.
814 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
815 const MachineOperand &MO = getOperand(i);
816 const MachineOperand &OMO = Other->getOperand(i);
818 if (!MO.isIdenticalTo(OMO))
823 // Clients may or may not want to ignore defs when testing for equality.
824 // For example, machine CSE pass only cares about finding common
825 // subexpressions, so it's safe to ignore virtual register defs.
827 if (Check == IgnoreDefs)
829 else if (Check == IgnoreVRegDefs) {
830 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
831 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
832 if (MO.getReg() != OMO.getReg())
835 if (!MO.isIdenticalTo(OMO))
837 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
841 if (!MO.isIdenticalTo(OMO))
843 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
847 // If DebugLoc does not match then two dbg.values are not identical.
849 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
850 && getDebugLoc() != Other->getDebugLoc())
855 MachineInstr *MachineInstr::removeFromParent() {
856 assert(getParent() && "Not embedded in a basic block!");
857 return getParent()->remove(this);
860 MachineInstr *MachineInstr::removeFromBundle() {
861 assert(getParent() && "Not embedded in a basic block!");
862 return getParent()->remove_instr(this);
865 void MachineInstr::eraseFromParent() {
866 assert(getParent() && "Not embedded in a basic block!");
867 getParent()->erase(this);
870 void MachineInstr::eraseFromBundle() {
871 assert(getParent() && "Not embedded in a basic block!");
872 getParent()->erase_instr(this);
875 /// getNumExplicitOperands - Returns the number of non-implicit operands.
877 unsigned MachineInstr::getNumExplicitOperands() const {
878 unsigned NumOperands = MCID->getNumOperands();
879 if (!MCID->isVariadic())
882 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
883 const MachineOperand &MO = getOperand(i);
884 if (!MO.isReg() || !MO.isImplicit())
890 void MachineInstr::bundleWithPred() {
891 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
892 setFlag(BundledPred);
893 MachineBasicBlock::instr_iterator Pred = this;
895 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
896 Pred->setFlag(BundledSucc);
899 void MachineInstr::bundleWithSucc() {
900 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
901 setFlag(BundledSucc);
902 MachineBasicBlock::instr_iterator Succ = this;
904 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
905 Succ->setFlag(BundledPred);
908 void MachineInstr::unbundleFromPred() {
909 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
910 clearFlag(BundledPred);
911 MachineBasicBlock::instr_iterator Pred = this;
913 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
914 Pred->clearFlag(BundledSucc);
917 void MachineInstr::unbundleFromSucc() {
918 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
919 clearFlag(BundledSucc);
920 MachineBasicBlock::instr_iterator Succ = this;
922 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
923 Succ->clearFlag(BundledPred);
926 bool MachineInstr::isStackAligningInlineAsm() const {
928 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
929 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
935 InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
936 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
937 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
938 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
941 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
942 unsigned *GroupNo) const {
943 assert(isInlineAsm() && "Expected an inline asm instruction");
944 assert(OpIdx < getNumOperands() && "OpIdx out of range");
946 // Ignore queries about the initial operands.
947 if (OpIdx < InlineAsm::MIOp_FirstOperand)
952 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
954 const MachineOperand &FlagMO = getOperand(i);
955 // If we reach the implicit register operands, stop looking.
958 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
959 if (i + NumOps > OpIdx) {
969 const TargetRegisterClass*
970 MachineInstr::getRegClassConstraint(unsigned OpIdx,
971 const TargetInstrInfo *TII,
972 const TargetRegisterInfo *TRI) const {
973 assert(getParent() && "Can't have an MBB reference here!");
974 assert(getParent()->getParent() && "Can't have an MF reference here!");
975 const MachineFunction &MF = *getParent()->getParent();
977 // Most opcodes have fixed constraints in their MCInstrDesc.
979 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
981 if (!getOperand(OpIdx).isReg())
984 // For tied uses on inline asm, get the constraint from the def.
986 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
989 // Inline asm stores register class constraints in the flag word.
990 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
994 unsigned Flag = getOperand(FlagIdx).getImm();
996 if (InlineAsm::hasRegClassConstraint(Flag, RCID))
997 return TRI->getRegClass(RCID);
999 // Assume that all registers in a memory operand are pointers.
1000 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
1001 return TRI->getPointerRegClass(MF);
1006 /// getBundleSize - Return the number of instructions inside the MI bundle.
1007 unsigned MachineInstr::getBundleSize() const {
1008 assert(isBundle() && "Expecting a bundle");
1010 const MachineBasicBlock *MBB = getParent();
1011 MachineBasicBlock::const_instr_iterator I = *this, E = MBB->instr_end();
1013 while ((++I != E) && I->isInsideBundle()) {
1016 assert(Size > 1 && "Malformed bundle");
1021 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1022 /// the specific register or -1 if it is not found. It further tightens
1023 /// the search criteria to a use that kills the register if isKill is true.
1024 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
1025 const TargetRegisterInfo *TRI) const {
1026 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1027 const MachineOperand &MO = getOperand(i);
1028 if (!MO.isReg() || !MO.isUse())
1030 unsigned MOReg = MO.getReg();
1035 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1036 TargetRegisterInfo::isPhysicalRegister(Reg) &&
1037 TRI->isSubRegister(MOReg, Reg)))
1038 if (!isKill || MO.isKill())
1044 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1045 /// indicating if this instruction reads or writes Reg. This also considers
1046 /// partial defines.
1047 std::pair<bool,bool>
1048 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1049 SmallVectorImpl<unsigned> *Ops) const {
1050 bool PartDef = false; // Partial redefine.
1051 bool FullDef = false; // Full define.
1054 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1055 const MachineOperand &MO = getOperand(i);
1056 if (!MO.isReg() || MO.getReg() != Reg)
1061 Use |= !MO.isUndef();
1062 else if (MO.getSubReg() && !MO.isUndef())
1063 // A partial <def,undef> doesn't count as reading the register.
1068 // A partial redefine uses Reg unless there is also a full define.
1069 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1072 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1073 /// the specified register or -1 if it is not found. If isDead is true, defs
1074 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1075 /// also checks if there is a def of a super-register.
1077 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1078 const TargetRegisterInfo *TRI) const {
1079 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1080 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1081 const MachineOperand &MO = getOperand(i);
1082 // Accept regmask operands when Overlap is set.
1083 // Ignore them when looking for a specific def operand (Overlap == false).
1084 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1086 if (!MO.isReg() || !MO.isDef())
1088 unsigned MOReg = MO.getReg();
1089 bool Found = (MOReg == Reg);
1090 if (!Found && TRI && isPhys &&
1091 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1093 Found = TRI->regsOverlap(MOReg, Reg);
1095 Found = TRI->isSubRegister(MOReg, Reg);
1097 if (Found && (!isDead || MO.isDead()))
1103 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1104 /// operand list that is used to represent the predicate. It returns -1 if
1106 int MachineInstr::findFirstPredOperandIdx() const {
1107 // Don't call MCID.findFirstPredOperandIdx() because this variant
1108 // is sometimes called on an instruction that's not yet complete, and
1109 // so the number of operands is less than the MCID indicates. In
1110 // particular, the PTX target does this.
1111 const MCInstrDesc &MCID = getDesc();
1112 if (MCID.isPredicable()) {
1113 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1114 if (MCID.OpInfo[i].isPredicate())
1121 // MachineOperand::TiedTo is 4 bits wide.
1122 const unsigned TiedMax = 15;
1124 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1126 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1127 /// field. TiedTo can have these values:
1129 /// 0: Operand is not tied to anything.
1130 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1131 /// TiedMax: Tied to an operand >= TiedMax-1.
1133 /// The tied def must be one of the first TiedMax operands on a normal
1134 /// instruction. INLINEASM instructions allow more tied defs.
1136 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1137 MachineOperand &DefMO = getOperand(DefIdx);
1138 MachineOperand &UseMO = getOperand(UseIdx);
1139 assert(DefMO.isDef() && "DefIdx must be a def operand");
1140 assert(UseMO.isUse() && "UseIdx must be a use operand");
1141 assert(!DefMO.isTied() && "Def is already tied to another use");
1142 assert(!UseMO.isTied() && "Use is already tied to another def");
1144 if (DefIdx < TiedMax)
1145 UseMO.TiedTo = DefIdx + 1;
1147 // Inline asm can use the group descriptors to find tied operands, but on
1148 // normal instruction, the tied def must be within the first TiedMax
1150 assert(isInlineAsm() && "DefIdx out of range");
1151 UseMO.TiedTo = TiedMax;
1154 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1155 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1158 /// Given the index of a tied register operand, find the operand it is tied to.
1159 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1160 /// which must exist.
1161 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1162 const MachineOperand &MO = getOperand(OpIdx);
1163 assert(MO.isTied() && "Operand isn't tied");
1165 // Normally TiedTo is in range.
1166 if (MO.TiedTo < TiedMax)
1167 return MO.TiedTo - 1;
1169 // Uses on normal instructions can be out of range.
1170 if (!isInlineAsm()) {
1171 // Normal tied defs must be in the 0..TiedMax-1 range.
1174 // MO is a def. Search for the tied use.
1175 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1176 const MachineOperand &UseMO = getOperand(i);
1177 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1180 llvm_unreachable("Can't find tied use");
1183 // Now deal with inline asm by parsing the operand group descriptor flags.
1184 // Find the beginning of each operand group.
1185 SmallVector<unsigned, 8> GroupIdx;
1186 unsigned OpIdxGroup = ~0u;
1188 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1190 const MachineOperand &FlagMO = getOperand(i);
1191 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1192 unsigned CurGroup = GroupIdx.size();
1193 GroupIdx.push_back(i);
1194 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1195 // OpIdx belongs to this operand group.
1196 if (OpIdx > i && OpIdx < i + NumOps)
1197 OpIdxGroup = CurGroup;
1199 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1201 // Operands in this group are tied to operands in TiedGroup which must be
1202 // earlier. Find the number of operands between the two groups.
1203 unsigned Delta = i - GroupIdx[TiedGroup];
1205 // OpIdx is a use tied to TiedGroup.
1206 if (OpIdxGroup == CurGroup)
1207 return OpIdx - Delta;
1209 // OpIdx is a def tied to this use group.
1210 if (OpIdxGroup == TiedGroup)
1211 return OpIdx + Delta;
1213 llvm_unreachable("Invalid tied operand on inline asm");
1216 /// clearKillInfo - Clears kill flags on all operands.
1218 void MachineInstr::clearKillInfo() {
1219 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1220 MachineOperand &MO = getOperand(i);
1221 if (MO.isReg() && MO.isUse())
1222 MO.setIsKill(false);
1226 void MachineInstr::substituteRegister(unsigned FromReg,
1229 const TargetRegisterInfo &RegInfo) {
1230 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1232 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1233 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1234 MachineOperand &MO = getOperand(i);
1235 if (!MO.isReg() || MO.getReg() != FromReg)
1237 MO.substPhysReg(ToReg, RegInfo);
1240 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1241 MachineOperand &MO = getOperand(i);
1242 if (!MO.isReg() || MO.getReg() != FromReg)
1244 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1249 /// isSafeToMove - Return true if it is safe to move this instruction. If
1250 /// SawStore is set to true, it means that there is a store (or call) between
1251 /// the instruction's location and its intended destination.
1252 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1254 bool &SawStore) const {
1255 // Ignore stuff that we obviously can't move.
1257 // Treat volatile loads as stores. This is not strictly necessary for
1258 // volatiles, but it is required for atomic loads. It is not allowed to move
1259 // a load across an atomic load with Ordering > Monotonic.
1260 if (mayStore() || isCall() ||
1261 (mayLoad() && hasOrderedMemoryRef())) {
1266 if (isLabel() || isDebugValue() ||
1267 isTerminator() || hasUnmodeledSideEffects())
1270 // See if this instruction does a load. If so, we have to guarantee that the
1271 // loaded value doesn't change between the load and the its intended
1272 // destination. The check for isInvariantLoad gives the targe the chance to
1273 // classify the load as always returning a constant, e.g. a constant pool
1275 if (mayLoad() && !isInvariantLoad(AA))
1276 // Otherwise, this is a real load. If there is a store between the load and
1277 // end of block, we can't move it.
1283 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1284 /// instruction which defined the specified register instead of copying it.
1285 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1287 unsigned DstReg) const {
1288 bool SawStore = false;
1289 if (!TII->isTriviallyReMaterializable(this, AA) ||
1290 !isSafeToMove(TII, AA, SawStore))
1292 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1293 const MachineOperand &MO = getOperand(i);
1296 // FIXME: For now, do not remat any instruction with register operands.
1297 // Later on, we can loosen the restriction is the register operands have
1298 // not been modified between the def and use. Note, this is different from
1299 // MachineSink because the code is no longer in two-address form (at least
1303 else if (!MO.isDead() && MO.getReg() != DstReg)
1309 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1310 /// or volatile memory reference, or if the information describing the memory
1311 /// reference is not available. Return false if it is known to have no ordered
1312 /// memory references.
1313 bool MachineInstr::hasOrderedMemoryRef() const {
1314 // An instruction known never to access memory won't have a volatile access.
1318 !hasUnmodeledSideEffects())
1321 // Otherwise, if the instruction has no memory reference information,
1322 // conservatively assume it wasn't preserved.
1323 if (memoperands_empty())
1326 // Check the memory reference information for ordered references.
1327 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1328 if (!(*I)->isUnordered())
1334 /// isInvariantLoad - Return true if this instruction is loading from a
1335 /// location whose value is invariant across the function. For example,
1336 /// loading a value from the constant pool or from the argument area
1337 /// of a function if it does not change. This should only return true of
1338 /// *all* loads the instruction does are invariant (if it does multiple loads).
1339 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1340 // If the instruction doesn't load at all, it isn't an invariant load.
1344 // If the instruction has lost its memoperands, conservatively assume that
1345 // it may not be an invariant load.
1346 if (memoperands_empty())
1349 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1351 for (mmo_iterator I = memoperands_begin(),
1352 E = memoperands_end(); I != E; ++I) {
1353 if ((*I)->isVolatile()) return false;
1354 if ((*I)->isStore()) return false;
1355 if ((*I)->isInvariant()) return true;
1357 if (const Value *V = (*I)->getValue()) {
1358 // A load from a constant PseudoSourceValue is invariant.
1359 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1360 if (PSV->isConstant(MFI))
1362 // If we have an AliasAnalysis, ask it whether the memory is constant.
1363 if (AA && AA->pointsToConstantMemory(
1364 AliasAnalysis::Location(V, (*I)->getSize(),
1365 (*I)->getTBAAInfo())))
1369 // Otherwise assume conservatively.
1373 // Everything checks out.
1377 /// isConstantValuePHI - If the specified instruction is a PHI that always
1378 /// merges together the same virtual register, return the register, otherwise
1380 unsigned MachineInstr::isConstantValuePHI() const {
1383 assert(getNumOperands() >= 3 &&
1384 "It's illegal to have a PHI without source operands");
1386 unsigned Reg = getOperand(1).getReg();
1387 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1388 if (getOperand(i).getReg() != Reg)
1393 bool MachineInstr::hasUnmodeledSideEffects() const {
1394 if (hasProperty(MCID::UnmodeledSideEffects))
1396 if (isInlineAsm()) {
1397 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1398 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1405 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1407 bool MachineInstr::allDefsAreDead() const {
1408 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1409 const MachineOperand &MO = getOperand(i);
1410 if (!MO.isReg() || MO.isUse())
1418 /// copyImplicitOps - Copy implicit register operands from specified
1419 /// instruction to this instruction.
1420 void MachineInstr::copyImplicitOps(MachineFunction &MF,
1421 const MachineInstr *MI) {
1422 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1424 const MachineOperand &MO = MI->getOperand(i);
1425 if (MO.isReg() && MO.isImplicit())
1430 void MachineInstr::dump() const {
1431 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1432 dbgs() << " " << *this;
1436 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1437 raw_ostream &CommentOS) {
1438 const LLVMContext &Ctx = MF->getFunction()->getContext();
1439 if (!DL.isUnknown()) { // Print source line info.
1440 DIScope Scope(DL.getScope(Ctx));
1441 // Omit the directory, because it's likely to be long and uninteresting.
1443 CommentOS << Scope.getFilename();
1445 CommentOS << "<unknown>";
1446 CommentOS << ':' << DL.getLine();
1447 if (DL.getCol() != 0)
1448 CommentOS << ':' << DL.getCol();
1449 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1450 if (!InlinedAtDL.isUnknown()) {
1451 CommentOS << " @[ ";
1452 printDebugLoc(InlinedAtDL, MF, CommentOS);
1458 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1459 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1460 const MachineFunction *MF = 0;
1461 const MachineRegisterInfo *MRI = 0;
1462 if (const MachineBasicBlock *MBB = getParent()) {
1463 MF = MBB->getParent();
1465 TM = &MF->getTarget();
1467 MRI = &MF->getRegInfo();
1470 // Save a list of virtual registers.
1471 SmallVector<unsigned, 8> VirtRegs;
1473 // Print explicitly defined operands on the left of an assignment syntax.
1474 unsigned StartOp = 0, e = getNumOperands();
1475 for (; StartOp < e && getOperand(StartOp).isReg() &&
1476 getOperand(StartOp).isDef() &&
1477 !getOperand(StartOp).isImplicit();
1479 if (StartOp != 0) OS << ", ";
1480 getOperand(StartOp).print(OS, TM);
1481 unsigned Reg = getOperand(StartOp).getReg();
1482 if (TargetRegisterInfo::isVirtualRegister(Reg))
1483 VirtRegs.push_back(Reg);
1489 // Print the opcode name.
1490 if (TM && TM->getInstrInfo())
1491 OS << TM->getInstrInfo()->getName(getOpcode());
1495 // Print the rest of the operands.
1496 bool OmittedAnyCallClobbers = false;
1497 bool FirstOp = true;
1498 unsigned AsmDescOp = ~0u;
1499 unsigned AsmOpCount = 0;
1501 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1502 // Print asm string.
1504 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1506 // Print HasSideEffects, IsAlignStack
1507 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1508 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1509 OS << " [sideeffect]";
1510 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1511 OS << " [alignstack]";
1512 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1513 OS << " [attdialect]";
1514 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1515 OS << " [inteldialect]";
1517 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1522 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1523 const MachineOperand &MO = getOperand(i);
1525 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1526 VirtRegs.push_back(MO.getReg());
1528 // Omit call-clobbered registers which aren't used anywhere. This makes
1529 // call instructions much less noisy on targets where calls clobber lots
1530 // of registers. Don't rely on MO.isDead() because we may be called before
1531 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1532 if (MF && isCall() &&
1533 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1534 unsigned Reg = MO.getReg();
1535 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1536 const MachineRegisterInfo &MRI = MF->getRegInfo();
1537 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1538 bool HasAliasLive = false;
1539 for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
1540 AI.isValid(); ++AI) {
1541 unsigned AliasReg = *AI;
1542 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1543 HasAliasLive = true;
1547 if (!HasAliasLive) {
1548 OmittedAnyCallClobbers = true;
1555 if (FirstOp) FirstOp = false; else OS << ",";
1557 if (i < getDesc().NumOperands) {
1558 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1559 if (MCOI.isPredicate())
1561 if (MCOI.isOptionalDef())
1564 if (isDebugValue() && MO.isMetadata()) {
1565 // Pretty print DBG_VALUE instructions.
1566 const MDNode *MD = MO.getMetadata();
1567 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1568 OS << "!\"" << MDS->getString() << '\"';
1571 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1572 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1573 } else if (i == AsmDescOp && MO.isImm()) {
1574 // Pretty print the inline asm operand descriptor.
1575 OS << '$' << AsmOpCount++;
1576 unsigned Flag = MO.getImm();
1577 switch (InlineAsm::getKind(Flag)) {
1578 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1579 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1580 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1581 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1582 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1583 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1584 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1588 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1590 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1592 OS << ":RC" << RCID;
1595 unsigned TiedTo = 0;
1596 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1597 OS << " tiedto:$" << TiedTo;
1601 // Compute the index of the next operand descriptor.
1602 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1607 // Briefly indicate whether any call clobbers were omitted.
1608 if (OmittedAnyCallClobbers) {
1609 if (!FirstOp) OS << ",";
1613 bool HaveSemi = false;
1615 if (!HaveSemi) OS << ";"; HaveSemi = true;
1618 if (Flags & FrameSetup)
1622 if (!memoperands_empty()) {
1623 if (!HaveSemi) OS << ";"; HaveSemi = true;
1626 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1629 if (llvm::next(i) != e)
1634 // Print the regclass of any virtual registers encountered.
1635 if (MRI && !VirtRegs.empty()) {
1636 if (!HaveSemi) OS << ";"; HaveSemi = true;
1637 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1638 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1639 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1640 for (unsigned j = i+1; j != VirtRegs.size();) {
1641 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1645 if (VirtRegs[i] != VirtRegs[j])
1646 OS << "," << PrintReg(VirtRegs[j]);
1647 VirtRegs.erase(VirtRegs.begin()+j);
1652 // Print debug location information.
1653 if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1654 if (!HaveSemi) OS << ";"; HaveSemi = true;
1655 DIVariable DV(getOperand(e - 1).getMetadata());
1656 OS << " line no:" << DV.getLineNumber();
1657 if (MDNode *InlinedAt = DV.getInlinedAt()) {
1658 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1659 if (!InlinedAtDL.isUnknown()) {
1660 OS << " inlined @[ ";
1661 printDebugLoc(InlinedAtDL, MF, OS);
1665 } else if (!debugLoc.isUnknown() && MF) {
1666 if (!HaveSemi) OS << ";"; HaveSemi = true;
1668 printDebugLoc(debugLoc, MF, OS);
1674 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1675 const TargetRegisterInfo *RegInfo,
1676 bool AddIfNotFound) {
1677 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1678 bool hasAliases = isPhysReg &&
1679 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1681 SmallVector<unsigned,4> DeadOps;
1682 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1683 MachineOperand &MO = getOperand(i);
1684 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1686 unsigned Reg = MO.getReg();
1690 if (Reg == IncomingReg) {
1693 // The register is already marked kill.
1695 if (isPhysReg && isRegTiedToDefOperand(i))
1696 // Two-address uses of physregs must not be marked kill.
1701 } else if (hasAliases && MO.isKill() &&
1702 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1703 // A super-register kill already exists.
1704 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1706 if (RegInfo->isSubRegister(IncomingReg, Reg))
1707 DeadOps.push_back(i);
1711 // Trim unneeded kill operands.
1712 while (!DeadOps.empty()) {
1713 unsigned OpIdx = DeadOps.back();
1714 if (getOperand(OpIdx).isImplicit())
1715 RemoveOperand(OpIdx);
1717 getOperand(OpIdx).setIsKill(false);
1721 // If not found, this means an alias of one of the operands is killed. Add a
1722 // new implicit operand if required.
1723 if (!Found && AddIfNotFound) {
1724 addOperand(MachineOperand::CreateReg(IncomingReg,
1733 void MachineInstr::clearRegisterKills(unsigned Reg,
1734 const TargetRegisterInfo *RegInfo) {
1735 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1737 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1738 MachineOperand &MO = getOperand(i);
1739 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1741 unsigned OpReg = MO.getReg();
1742 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1743 MO.setIsKill(false);
1747 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1748 const TargetRegisterInfo *RegInfo,
1749 bool AddIfNotFound) {
1750 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1751 bool hasAliases = isPhysReg &&
1752 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1754 SmallVector<unsigned,4> DeadOps;
1755 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1756 MachineOperand &MO = getOperand(i);
1757 if (!MO.isReg() || !MO.isDef())
1759 unsigned Reg = MO.getReg();
1763 if (Reg == IncomingReg) {
1766 } else if (hasAliases && MO.isDead() &&
1767 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1768 // There exists a super-register that's marked dead.
1769 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1771 if (RegInfo->isSubRegister(IncomingReg, Reg))
1772 DeadOps.push_back(i);
1776 // Trim unneeded dead operands.
1777 while (!DeadOps.empty()) {
1778 unsigned OpIdx = DeadOps.back();
1779 if (getOperand(OpIdx).isImplicit())
1780 RemoveOperand(OpIdx);
1782 getOperand(OpIdx).setIsDead(false);
1786 // If not found, this means an alias of one of the operands is dead. Add a
1787 // new implicit operand if required.
1788 if (Found || !AddIfNotFound)
1791 addOperand(MachineOperand::CreateReg(IncomingReg,
1799 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1800 const TargetRegisterInfo *RegInfo) {
1801 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1802 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1806 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1807 const MachineOperand &MO = getOperand(i);
1808 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1809 MO.getSubReg() == 0)
1813 addOperand(MachineOperand::CreateReg(IncomingReg,
1818 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1819 const TargetRegisterInfo &TRI) {
1820 bool HasRegMask = false;
1821 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1822 MachineOperand &MO = getOperand(i);
1823 if (MO.isRegMask()) {
1827 if (!MO.isReg() || !MO.isDef()) continue;
1828 unsigned Reg = MO.getReg();
1829 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1831 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1833 if (TRI.regsOverlap(*I, Reg)) {
1837 // If there are no uses, including partial uses, the def is dead.
1838 if (Dead) MO.setIsDead();
1841 // This is a call with a register mask operand.
1842 // Mask clobbers are always dead, so add defs for the non-dead defines.
1844 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1846 addRegisterDefined(*I, &TRI);
1850 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1851 // Build up a buffer of hash code components.
1852 SmallVector<size_t, 8> HashComponents;
1853 HashComponents.reserve(MI->getNumOperands() + 1);
1854 HashComponents.push_back(MI->getOpcode());
1855 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1856 const MachineOperand &MO = MI->getOperand(i);
1857 if (MO.isReg() && MO.isDef() &&
1858 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1859 continue; // Skip virtual register defs.
1861 HashComponents.push_back(hash_value(MO));
1863 return hash_combine_range(HashComponents.begin(), HashComponents.end());
1866 void MachineInstr::emitError(StringRef Msg) const {
1867 // Find the source location cookie.
1868 unsigned LocCookie = 0;
1869 const MDNode *LocMD = 0;
1870 for (unsigned i = getNumOperands(); i != 0; --i) {
1871 if (getOperand(i-1).isMetadata() &&
1872 (LocMD = getOperand(i-1).getMetadata()) &&
1873 LocMD->getNumOperands() != 0) {
1874 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1875 LocCookie = CI->getZExtValue();
1881 if (const MachineBasicBlock *MBB = getParent())
1882 if (const MachineFunction *MF = MBB->getParent())
1883 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1884 report_fatal_error(Msg);