1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/InlineAsm.h"
17 #include "llvm/Value.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetInstrDesc.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Support/LeakDetector.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/Streams.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/FoldingSet.h"
33 //===----------------------------------------------------------------------===//
34 // MachineOperand Implementation
35 //===----------------------------------------------------------------------===//
37 /// AddRegOperandToRegInfo - Add this register operand to the specified
38 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
39 /// explicitly nulled out.
40 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
41 assert(isReg() && "Can only add reg operand to use lists");
43 // If the reginfo pointer is null, just explicitly null out or next/prev
44 // pointers, to ensure they are not garbage.
46 Contents.Reg.Prev = 0;
47 Contents.Reg.Next = 0;
51 // Otherwise, add this operand to the head of the registers use/def list.
52 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
54 // For SSA values, we prefer to keep the definition at the start of the list.
55 // we do this by skipping over the definition if it is at the head of the
57 if (*Head && (*Head)->isDef())
58 Head = &(*Head)->Contents.Reg.Next;
60 Contents.Reg.Next = *Head;
61 if (Contents.Reg.Next) {
62 assert(getReg() == Contents.Reg.Next->getReg() &&
63 "Different regs on the same list!");
64 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
67 Contents.Reg.Prev = Head;
71 void MachineOperand::setReg(unsigned Reg) {
72 if (getReg() == Reg) return; // No change.
74 // Otherwise, we have to change the register. If this operand is embedded
75 // into a machine function, we need to update the old and new register's
77 if (MachineInstr *MI = getParent())
78 if (MachineBasicBlock *MBB = MI->getParent())
79 if (MachineFunction *MF = MBB->getParent()) {
80 RemoveRegOperandFromRegInfo();
81 Contents.Reg.RegNo = Reg;
82 AddRegOperandToRegInfo(&MF->getRegInfo());
86 // Otherwise, just change the register, no problem. :)
87 Contents.Reg.RegNo = Reg;
90 /// ChangeToImmediate - Replace this operand with a new immediate operand of
91 /// the specified value. If an operand is known to be an immediate already,
92 /// the setImm method should be used.
93 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
94 // If this operand is currently a register operand, and if this is in a
95 // function, deregister the operand from the register's use/def list.
96 if (isReg() && getParent() && getParent()->getParent() &&
97 getParent()->getParent()->getParent())
98 RemoveRegOperandFromRegInfo();
100 OpKind = MO_Immediate;
101 Contents.ImmVal = ImmVal;
104 /// ChangeToRegister - Replace this operand with a new register operand of
105 /// the specified value. If an operand is known to be an register already,
106 /// the setReg method should be used.
107 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
108 bool isKill, bool isDead) {
109 // If this operand is already a register operand, use setReg to update the
110 // register's use/def lists.
112 assert(!isEarlyClobber());
115 // Otherwise, change this to a register and set the reg#.
116 OpKind = MO_Register;
117 Contents.Reg.RegNo = Reg;
119 // If this operand is embedded in a function, add the operand to the
120 // register's use/def list.
121 if (MachineInstr *MI = getParent())
122 if (MachineBasicBlock *MBB = MI->getParent())
123 if (MachineFunction *MF = MBB->getParent())
124 AddRegOperandToRegInfo(&MF->getRegInfo());
131 IsEarlyClobber = false;
135 /// isIdenticalTo - Return true if this operand is identical to the specified
137 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
138 if (getType() != Other.getType()) return false;
141 default: assert(0 && "Unrecognized operand type");
142 case MachineOperand::MO_Register:
143 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
144 getSubReg() == Other.getSubReg();
145 case MachineOperand::MO_Immediate:
146 return getImm() == Other.getImm();
147 case MachineOperand::MO_FPImmediate:
148 return getFPImm() == Other.getFPImm();
149 case MachineOperand::MO_MachineBasicBlock:
150 return getMBB() == Other.getMBB();
151 case MachineOperand::MO_FrameIndex:
152 return getIndex() == Other.getIndex();
153 case MachineOperand::MO_ConstantPoolIndex:
154 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
155 case MachineOperand::MO_JumpTableIndex:
156 return getIndex() == Other.getIndex();
157 case MachineOperand::MO_GlobalAddress:
158 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
159 case MachineOperand::MO_ExternalSymbol:
160 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
161 getOffset() == Other.getOffset();
165 /// print - Print the specified machine operand.
167 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
168 raw_os_ostream RawOS(OS);
172 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
174 case MachineOperand::MO_Register:
175 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
176 OS << "%reg" << getReg();
178 // If the instruction is embedded into a basic block, we can find the
179 // target info for the instruction.
181 if (const MachineInstr *MI = getParent())
182 if (const MachineBasicBlock *MBB = MI->getParent())
183 if (const MachineFunction *MF = MBB->getParent())
184 TM = &MF->getTarget();
187 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
189 OS << "%mreg" << getReg();
192 if (getSubReg() != 0) {
193 OS << ":" << getSubReg();
196 if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) {
198 bool NeedComma = false;
200 if (NeedComma) OS << ",";
201 OS << (isDef() ? "imp-def" : "imp-use");
203 } else if (isDef()) {
204 if (NeedComma) OS << ",";
205 if (isEarlyClobber())
206 OS << "earlyclobber,";
210 if (isKill() || isDead()) {
211 if (NeedComma) OS << ",";
212 if (isKill()) OS << "kill";
213 if (isDead()) OS << "dead";
218 case MachineOperand::MO_Immediate:
221 case MachineOperand::MO_FPImmediate:
222 if (getFPImm()->getType() == Type::FloatTy) {
223 OS << getFPImm()->getValueAPF().convertToFloat();
225 OS << getFPImm()->getValueAPF().convertToDouble();
228 case MachineOperand::MO_MachineBasicBlock:
230 << ((Value*)getMBB()->getBasicBlock())->getName()
231 << "," << (void*)getMBB() << ">";
233 case MachineOperand::MO_FrameIndex:
234 OS << "<fi#" << getIndex() << ">";
236 case MachineOperand::MO_ConstantPoolIndex:
237 OS << "<cp#" << getIndex();
238 if (getOffset()) OS << "+" << getOffset();
241 case MachineOperand::MO_JumpTableIndex:
242 OS << "<jt#" << getIndex() << ">";
244 case MachineOperand::MO_GlobalAddress:
245 OS << "<ga:" << ((Value*)getGlobal())->getName();
246 if (getOffset()) OS << "+" << getOffset();
249 case MachineOperand::MO_ExternalSymbol:
250 OS << "<es:" << getSymbolName();
251 if (getOffset()) OS << "+" << getOffset();
255 assert(0 && "Unrecognized operand type");
259 //===----------------------------------------------------------------------===//
260 // MachineMemOperand Implementation
261 //===----------------------------------------------------------------------===//
263 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
264 int64_t o, uint64_t s, unsigned int a)
265 : Offset(o), Size(s), V(v),
266 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
267 assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
268 assert((isLoad() || isStore()) && "Not a load/store!");
271 /// Profile - Gather unique data for the object.
273 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
274 ID.AddInteger(Offset);
277 ID.AddInteger(Flags);
280 //===----------------------------------------------------------------------===//
281 // MachineInstr Implementation
282 //===----------------------------------------------------------------------===//
284 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
285 /// TID NULL and no operands.
286 MachineInstr::MachineInstr()
287 : TID(0), NumImplicitOps(0), Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
288 // Make sure that we get added to a machine basicblock
289 LeakDetector::addGarbageObject(this);
292 void MachineInstr::addImplicitDefUseOperands() {
293 if (TID->ImplicitDefs)
294 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
295 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
296 if (TID->ImplicitUses)
297 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
298 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
301 /// MachineInstr ctor - This constructor create a MachineInstr and add the
302 /// implicit operands. It reserves space for number of operands specified by
303 /// TargetInstrDesc or the numOperands if it is not zero. (for
304 /// instructions with variable number of operands).
305 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
306 : TID(&tid), NumImplicitOps(0), Parent(0),
307 debugLoc(DebugLoc::getUnknownLoc()) {
308 if (!NoImp && TID->getImplicitDefs())
309 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
311 if (!NoImp && TID->getImplicitUses())
312 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
314 Operands.reserve(NumImplicitOps + TID->getNumOperands());
316 addImplicitDefUseOperands();
317 // Make sure that we get added to a machine basicblock
318 LeakDetector::addGarbageObject(this);
321 /// MachineInstr ctor - As above, but with a DebugLoc.
322 MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
324 : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
325 if (!NoImp && TID->getImplicitDefs())
326 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
328 if (!NoImp && TID->getImplicitUses())
329 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
331 Operands.reserve(NumImplicitOps + TID->getNumOperands());
333 addImplicitDefUseOperands();
334 // Make sure that we get added to a machine basicblock
335 LeakDetector::addGarbageObject(this);
338 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
339 /// that the MachineInstr is created and added to the end of the specified
342 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
343 : TID(&tid), NumImplicitOps(0), Parent(0),
344 debugLoc(DebugLoc::getUnknownLoc()) {
345 assert(MBB && "Cannot use inserting ctor with null basic block!");
346 if (TID->ImplicitDefs)
347 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
349 if (TID->ImplicitUses)
350 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
352 Operands.reserve(NumImplicitOps + TID->getNumOperands());
353 addImplicitDefUseOperands();
354 // Make sure that we get added to a machine basicblock
355 LeakDetector::addGarbageObject(this);
356 MBB->push_back(this); // Add instruction to end of basic block!
359 /// MachineInstr ctor - As above, but with a DebugLoc.
361 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
362 const TargetInstrDesc &tid)
363 : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
364 assert(MBB && "Cannot use inserting ctor with null basic block!");
365 if (TID->ImplicitDefs)
366 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
368 if (TID->ImplicitUses)
369 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
371 Operands.reserve(NumImplicitOps + TID->getNumOperands());
372 addImplicitDefUseOperands();
373 // Make sure that we get added to a machine basicblock
374 LeakDetector::addGarbageObject(this);
375 MBB->push_back(this); // Add instruction to end of basic block!
378 /// MachineInstr ctor - Copies MachineInstr arg exactly
380 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
381 : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0),
382 debugLoc(MI.getDebugLoc()) {
383 Operands.reserve(MI.getNumOperands());
386 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
387 addOperand(MI.getOperand(i));
388 NumImplicitOps = MI.NumImplicitOps;
390 // Add memory operands.
391 for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
392 j = MI.memoperands_end(); i != j; ++i)
393 addMemOperand(MF, *i);
395 // Set parent to null.
398 LeakDetector::addGarbageObject(this);
401 MachineInstr::~MachineInstr() {
402 LeakDetector::removeGarbageObject(this);
403 assert(MemOperands.empty() &&
404 "MachineInstr being deleted with live memoperands!");
406 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
407 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
408 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
409 "Reg operand def/use list corrupted");
414 /// getRegInfo - If this instruction is embedded into a MachineFunction,
415 /// return the MachineRegisterInfo object for the current function, otherwise
417 MachineRegisterInfo *MachineInstr::getRegInfo() {
418 if (MachineBasicBlock *MBB = getParent())
419 return &MBB->getParent()->getRegInfo();
423 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
424 /// this instruction from their respective use lists. This requires that the
425 /// operands already be on their use lists.
426 void MachineInstr::RemoveRegOperandsFromUseLists() {
427 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
428 if (Operands[i].isReg())
429 Operands[i].RemoveRegOperandFromRegInfo();
433 /// AddRegOperandsToUseLists - Add all of the register operands in
434 /// this instruction from their respective use lists. This requires that the
435 /// operands not be on their use lists yet.
436 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
437 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
438 if (Operands[i].isReg())
439 Operands[i].AddRegOperandToRegInfo(&RegInfo);
444 /// addOperand - Add the specified operand to the instruction. If it is an
445 /// implicit operand, it is added to the end of the operand list. If it is
446 /// an explicit operand it is added at the end of the explicit operand list
447 /// (before the first implicit operand).
448 void MachineInstr::addOperand(const MachineOperand &Op) {
449 bool isImpReg = Op.isReg() && Op.isImplicit();
450 assert((isImpReg || !OperandsComplete()) &&
451 "Trying to add an operand to a machine instr that is already done!");
453 MachineRegisterInfo *RegInfo = getRegInfo();
455 // If we are adding the operand to the end of the list, our job is simpler.
456 // This is true most of the time, so this is a reasonable optimization.
457 if (isImpReg || NumImplicitOps == 0) {
458 // We can only do this optimization if we know that the operand list won't
460 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
461 Operands.push_back(Op);
463 // Set the parent of the operand.
464 Operands.back().ParentMI = this;
466 // If the operand is a register, update the operand's use list.
468 Operands.back().AddRegOperandToRegInfo(RegInfo);
473 // Otherwise, we have to insert a real operand before any implicit ones.
474 unsigned OpNo = Operands.size()-NumImplicitOps;
476 // If this instruction isn't embedded into a function, then we don't need to
477 // update any operand lists.
479 // Simple insertion, no reginfo update needed for other register operands.
480 Operands.insert(Operands.begin()+OpNo, Op);
481 Operands[OpNo].ParentMI = this;
483 // Do explicitly set the reginfo for this operand though, to ensure the
484 // next/prev fields are properly nulled out.
485 if (Operands[OpNo].isReg())
486 Operands[OpNo].AddRegOperandToRegInfo(0);
488 } else if (Operands.size()+1 <= Operands.capacity()) {
489 // Otherwise, we have to remove register operands from their register use
490 // list, add the operand, then add the register operands back to their use
491 // list. This also must handle the case when the operand list reallocates
492 // to somewhere else.
494 // If insertion of this operand won't cause reallocation of the operand
495 // list, just remove the implicit operands, add the operand, then re-add all
496 // the rest of the operands.
497 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
498 assert(Operands[i].isReg() && "Should only be an implicit reg!");
499 Operands[i].RemoveRegOperandFromRegInfo();
502 // Add the operand. If it is a register, add it to the reg list.
503 Operands.insert(Operands.begin()+OpNo, Op);
504 Operands[OpNo].ParentMI = this;
506 if (Operands[OpNo].isReg())
507 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
509 // Re-add all the implicit ops.
510 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
511 assert(Operands[i].isReg() && "Should only be an implicit reg!");
512 Operands[i].AddRegOperandToRegInfo(RegInfo);
515 // Otherwise, we will be reallocating the operand list. Remove all reg
516 // operands from their list, then readd them after the operand list is
518 RemoveRegOperandsFromUseLists();
520 Operands.insert(Operands.begin()+OpNo, Op);
521 Operands[OpNo].ParentMI = this;
523 // Re-add all the operands.
524 AddRegOperandsToUseLists(*RegInfo);
528 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
529 /// fewer operand than it started with.
531 void MachineInstr::RemoveOperand(unsigned OpNo) {
532 assert(OpNo < Operands.size() && "Invalid operand number");
534 // Special case removing the last one.
535 if (OpNo == Operands.size()-1) {
536 // If needed, remove from the reg def/use list.
537 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
538 Operands.back().RemoveRegOperandFromRegInfo();
544 // Otherwise, we are removing an interior operand. If we have reginfo to
545 // update, remove all operands that will be shifted down from their reg lists,
546 // move everything down, then re-add them.
547 MachineRegisterInfo *RegInfo = getRegInfo();
549 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
550 if (Operands[i].isReg())
551 Operands[i].RemoveRegOperandFromRegInfo();
555 Operands.erase(Operands.begin()+OpNo);
558 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
559 if (Operands[i].isReg())
560 Operands[i].AddRegOperandToRegInfo(RegInfo);
565 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
566 /// referencing arbitrary storage.
567 void MachineInstr::addMemOperand(MachineFunction &MF,
568 const MachineMemOperand &MO) {
569 MemOperands.push_back(MO);
572 /// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
573 void MachineInstr::clearMemOperands(MachineFunction &MF) {
578 /// removeFromParent - This method unlinks 'this' from the containing basic
579 /// block, and returns it, but does not delete it.
580 MachineInstr *MachineInstr::removeFromParent() {
581 assert(getParent() && "Not embedded in a basic block!");
582 getParent()->remove(this);
587 /// eraseFromParent - This method unlinks 'this' from the containing basic
588 /// block, and deletes it.
589 void MachineInstr::eraseFromParent() {
590 assert(getParent() && "Not embedded in a basic block!");
591 getParent()->erase(this);
595 /// OperandComplete - Return true if it's illegal to add a new operand
597 bool MachineInstr::OperandsComplete() const {
598 unsigned short NumOperands = TID->getNumOperands();
599 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
600 return true; // Broken: we have all the operands of this instruction!
604 /// getNumExplicitOperands - Returns the number of non-implicit operands.
606 unsigned MachineInstr::getNumExplicitOperands() const {
607 unsigned NumOperands = TID->getNumOperands();
608 if (!TID->isVariadic())
611 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
612 const MachineOperand &MO = getOperand(NumOperands);
613 if (!MO.isReg() || !MO.isImplicit())
620 /// isLabel - Returns true if the MachineInstr represents a label.
622 bool MachineInstr::isLabel() const {
623 return getOpcode() == TargetInstrInfo::DBG_LABEL ||
624 getOpcode() == TargetInstrInfo::EH_LABEL ||
625 getOpcode() == TargetInstrInfo::GC_LABEL;
628 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
630 bool MachineInstr::isDebugLabel() const {
631 return getOpcode() == TargetInstrInfo::DBG_LABEL;
634 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
635 /// the specific register or -1 if it is not found. It further tightening
636 /// the search criteria to a use that kills the register if isKill is true.
637 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
638 const TargetRegisterInfo *TRI) const {
639 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
640 const MachineOperand &MO = getOperand(i);
641 if (!MO.isReg() || !MO.isUse())
643 unsigned MOReg = MO.getReg();
648 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
649 TargetRegisterInfo::isPhysicalRegister(Reg) &&
650 TRI->isSubRegister(MOReg, Reg)))
651 if (!isKill || MO.isKill())
657 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
658 /// the specified register or -1 if it is not found. If isDead is true, defs
659 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
660 /// also checks if there is a def of a super-register.
661 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
662 const TargetRegisterInfo *TRI) const {
663 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
664 const MachineOperand &MO = getOperand(i);
665 if (!MO.isReg() || !MO.isDef())
667 unsigned MOReg = MO.getReg();
670 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
671 TargetRegisterInfo::isPhysicalRegister(Reg) &&
672 TRI->isSubRegister(MOReg, Reg)))
673 if (!isDead || MO.isDead())
679 /// findFirstPredOperandIdx() - Find the index of the first operand in the
680 /// operand list that is used to represent the predicate. It returns -1 if
682 int MachineInstr::findFirstPredOperandIdx() const {
683 const TargetInstrDesc &TID = getDesc();
684 if (TID.isPredicable()) {
685 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
686 if (TID.OpInfo[i].isPredicate())
693 /// isRegTiedToUseOperand - Given the index of a register def operand,
694 /// check if the register def is tied to a source operand, due to either
695 /// two-address elimination or inline assembly constraints. Returns the
696 /// first tied use operand index by reference is UseOpIdx is not null.
697 bool MachineInstr::isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx){
698 if (getOpcode() == TargetInstrInfo::INLINEASM) {
699 assert(DefOpIdx >= 2);
700 const MachineOperand &MO = getOperand(DefOpIdx);
701 if (!MO.isReg() || !MO.isDef())
703 // Determine the actual operand no corresponding to this index.
705 for (unsigned i = 1, e = getNumOperands(); i < e; ) {
706 const MachineOperand &FMO = getOperand(i);
708 // Skip over this def.
709 i += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
714 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
715 const MachineOperand &FMO = getOperand(i);
718 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
721 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
724 *UseOpIdx = (unsigned)i + 1;
730 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
731 const TargetInstrDesc &TID = getDesc();
732 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
733 const MachineOperand &MO = getOperand(i);
734 if (MO.isReg() && MO.isUse() &&
735 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
737 *UseOpIdx = (unsigned)i;
744 /// isRegTiedToDefOperand - Return true if the operand of the specified index
745 /// is a register use and it is tied to an def operand. It also returns the def
746 /// operand index by reference.
747 bool MachineInstr::isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx){
748 if (getOpcode() == TargetInstrInfo::INLINEASM) {
749 const MachineOperand &MO = getOperand(UseOpIdx);
750 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
752 assert(UseOpIdx > 0);
753 const MachineOperand &UFMO = getOperand(UseOpIdx-1);
755 return false; // Must be physreg uses.
757 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
762 // Remember to adjust the index. First operand is asm string, then there
763 // is a flag for each.
765 const MachineOperand &FMO = getOperand(DefIdx);
767 // Skip over this def.
768 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
771 *DefOpIdx = DefIdx+1;
777 const TargetInstrDesc &TID = getDesc();
778 if (UseOpIdx >= TID.getNumOperands())
780 const MachineOperand &MO = getOperand(UseOpIdx);
781 if (!MO.isReg() || !MO.isUse())
783 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
787 *DefOpIdx = (unsigned)DefIdx;
791 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
793 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
794 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
795 const MachineOperand &MO = MI->getOperand(i);
796 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
798 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
799 MachineOperand &MOp = getOperand(j);
800 if (!MOp.isIdenticalTo(MO))
811 /// copyPredicates - Copies predicate operand(s) from MI.
812 void MachineInstr::copyPredicates(const MachineInstr *MI) {
813 const TargetInstrDesc &TID = MI->getDesc();
814 if (!TID.isPredicable())
816 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
817 if (TID.OpInfo[i].isPredicate()) {
818 // Predicated operands must be last operands.
819 addOperand(MI->getOperand(i));
824 /// isSafeToMove - Return true if it is safe to move this instruction. If
825 /// SawStore is set to true, it means that there is a store (or call) between
826 /// the instruction's location and its intended destination.
827 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
828 bool &SawStore) const {
829 // Ignore stuff that we obviously can't move.
830 if (TID->mayStore() || TID->isCall()) {
834 if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
837 // See if this instruction does a load. If so, we have to guarantee that the
838 // loaded value doesn't change between the load and the its intended
839 // destination. The check for isInvariantLoad gives the targe the chance to
840 // classify the load as always returning a constant, e.g. a constant pool
842 if (TID->mayLoad() && !TII->isInvariantLoad(this))
843 // Otherwise, this is a real load. If there is a store between the load and
844 // end of block, or if the laod is volatile, we can't move it.
845 return !SawStore && !hasVolatileMemoryRef();
850 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
851 /// instruction which defined the specified register instead of copying it.
852 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
853 unsigned DstReg) const {
854 bool SawStore = false;
855 if (!getDesc().isRematerializable() ||
856 !TII->isTriviallyReMaterializable(this) ||
857 !isSafeToMove(TII, SawStore))
859 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
860 const MachineOperand &MO = getOperand(i);
863 // FIXME: For now, do not remat any instruction with register operands.
864 // Later on, we can loosen the restriction is the register operands have
865 // not been modified between the def and use. Note, this is different from
866 // MachineSink because the code is no longer in two-address form (at least
870 else if (!MO.isDead() && MO.getReg() != DstReg)
876 /// hasVolatileMemoryRef - Return true if this instruction may have a
877 /// volatile memory reference, or if the information describing the
878 /// memory reference is not available. Return false if it is known to
879 /// have no volatile memory references.
880 bool MachineInstr::hasVolatileMemoryRef() const {
881 // An instruction known never to access memory won't have a volatile access.
882 if (!TID->mayStore() &&
885 !TID->hasUnmodeledSideEffects())
888 // Otherwise, if the instruction has no memory reference information,
889 // conservatively assume it wasn't preserved.
890 if (memoperands_empty())
893 // Check the memory reference information for volatile references.
894 for (std::list<MachineMemOperand>::const_iterator I = memoperands_begin(),
895 E = memoperands_end(); I != E; ++I)
902 void MachineInstr::dump() const {
903 cerr << " " << *this;
906 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
907 raw_os_ostream RawOS(OS);
911 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
912 // Specialize printing if op#0 is definition
913 unsigned StartOp = 0;
914 if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
915 getOperand(0).print(OS, TM);
917 ++StartOp; // Don't print this operand again!
920 OS << getDesc().getName();
922 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
926 getOperand(i).print(OS, TM);
929 if (!memoperands_empty()) {
931 for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(),
932 e = memoperands_end(); i != e; ++i) {
933 const MachineMemOperand &MRO = *i;
934 const Value *V = MRO.getValue();
936 assert((MRO.isLoad() || MRO.isStore()) &&
937 "SV has to be a load, store or both.");
939 if (MRO.isVolatile())
947 OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
951 else if (!V->getName().empty())
953 else if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
958 OS << " + " << MRO.getOffset() << "]";
962 if (!debugLoc.isUnknown()) {
963 const MachineFunction *MF = getParent()->getParent();
964 DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc);
974 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
975 const TargetRegisterInfo *RegInfo,
976 bool AddIfNotFound) {
977 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
978 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
980 SmallVector<unsigned,4> DeadOps;
981 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
982 MachineOperand &MO = getOperand(i);
983 if (!MO.isReg() || !MO.isUse())
985 unsigned Reg = MO.getReg();
989 if (Reg == IncomingReg) {
992 // The register is already marked kill.
997 } else if (hasAliases && MO.isKill() &&
998 TargetRegisterInfo::isPhysicalRegister(Reg)) {
999 // A super-register kill already exists.
1000 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1002 if (RegInfo->isSubRegister(IncomingReg, Reg))
1003 DeadOps.push_back(i);
1007 // Trim unneeded kill operands.
1008 while (!DeadOps.empty()) {
1009 unsigned OpIdx = DeadOps.back();
1010 if (getOperand(OpIdx).isImplicit())
1011 RemoveOperand(OpIdx);
1013 getOperand(OpIdx).setIsKill(false);
1017 // If not found, this means an alias of one of the operands is killed. Add a
1018 // new implicit operand if required.
1019 if (!Found && AddIfNotFound) {
1020 addOperand(MachineOperand::CreateReg(IncomingReg,
1029 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1030 const TargetRegisterInfo *RegInfo,
1031 bool AddIfNotFound) {
1032 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1033 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1035 SmallVector<unsigned,4> DeadOps;
1036 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1037 MachineOperand &MO = getOperand(i);
1038 if (!MO.isReg() || !MO.isDef())
1040 unsigned Reg = MO.getReg();
1044 if (Reg == IncomingReg) {
1047 // The register is already marked dead.
1052 } else if (hasAliases && MO.isDead() &&
1053 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1054 // There exists a super-register that's marked dead.
1055 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1057 if (RegInfo->getSubRegisters(IncomingReg) &&
1058 RegInfo->getSuperRegisters(Reg) &&
1059 RegInfo->isSubRegister(IncomingReg, Reg))
1060 DeadOps.push_back(i);
1064 // Trim unneeded dead operands.
1065 while (!DeadOps.empty()) {
1066 unsigned OpIdx = DeadOps.back();
1067 if (getOperand(OpIdx).isImplicit())
1068 RemoveOperand(OpIdx);
1070 getOperand(OpIdx).setIsDead(false);
1074 // If not found, this means an alias of one of the operands is dead. Add a
1075 // new implicit operand if required.
1076 if (!Found && AddIfNotFound) {
1077 addOperand(MachineOperand::CreateReg(IncomingReg,