1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Function.h"
17 #include "llvm/InlineAsm.h"
18 #include "llvm/LLVMContext.h"
19 #include "llvm/Metadata.h"
20 #include "llvm/Module.h"
21 #include "llvm/Type.h"
22 #include "llvm/Value.h"
23 #include "llvm/Assembly/Writer.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCSymbol.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Analysis/AliasAnalysis.h"
36 #include "llvm/Analysis/DebugInfo.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/LeakDetector.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/FoldingSet.h"
45 //===----------------------------------------------------------------------===//
46 // MachineOperand Implementation
47 //===----------------------------------------------------------------------===//
49 /// AddRegOperandToRegInfo - Add this register operand to the specified
50 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
51 /// explicitly nulled out.
52 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
53 assert(isReg() && "Can only add reg operand to use lists");
55 // If the reginfo pointer is null, just explicitly null out or next/prev
56 // pointers, to ensure they are not garbage.
58 Contents.Reg.Prev = 0;
59 Contents.Reg.Next = 0;
63 // Otherwise, add this operand to the head of the registers use/def list.
64 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
66 // For SSA values, we prefer to keep the definition at the start of the list.
67 // we do this by skipping over the definition if it is at the head of the
69 if (*Head && (*Head)->isDef())
70 Head = &(*Head)->Contents.Reg.Next;
72 Contents.Reg.Next = *Head;
73 if (Contents.Reg.Next) {
74 assert(getReg() == Contents.Reg.Next->getReg() &&
75 "Different regs on the same list!");
76 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
79 Contents.Reg.Prev = Head;
83 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
84 /// MachineRegisterInfo it is linked with.
85 void MachineOperand::RemoveRegOperandFromRegInfo() {
86 assert(isOnRegUseList() && "Reg operand is not on a use list");
87 // Unlink this from the doubly linked list of operands.
88 MachineOperand *NextOp = Contents.Reg.Next;
89 *Contents.Reg.Prev = NextOp;
91 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
92 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
94 Contents.Reg.Prev = 0;
95 Contents.Reg.Next = 0;
98 void MachineOperand::setReg(unsigned Reg) {
99 if (getReg() == Reg) return; // No change.
101 // Otherwise, we have to change the register. If this operand is embedded
102 // into a machine function, we need to update the old and new register's
104 if (MachineInstr *MI = getParent())
105 if (MachineBasicBlock *MBB = MI->getParent())
106 if (MachineFunction *MF = MBB->getParent()) {
107 RemoveRegOperandFromRegInfo();
108 SmallContents.RegNo = Reg;
109 AddRegOperandToRegInfo(&MF->getRegInfo());
113 // Otherwise, just change the register, no problem. :)
114 SmallContents.RegNo = Reg;
117 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
118 const TargetRegisterInfo &TRI) {
119 assert(TargetRegisterInfo::isVirtualRegister(Reg));
120 if (SubIdx && getSubReg())
121 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
127 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
128 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
130 Reg = TRI.getSubReg(Reg, getSubReg());
131 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
132 // That won't happen in legal code.
138 /// ChangeToImmediate - Replace this operand with a new immediate operand of
139 /// the specified value. If an operand is known to be an immediate already,
140 /// the setImm method should be used.
141 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
142 // If this operand is currently a register operand, and if this is in a
143 // function, deregister the operand from the register's use/def list.
144 if (isReg() && getParent() && getParent()->getParent() &&
145 getParent()->getParent()->getParent())
146 RemoveRegOperandFromRegInfo();
148 OpKind = MO_Immediate;
149 Contents.ImmVal = ImmVal;
152 /// ChangeToRegister - Replace this operand with a new register operand of
153 /// the specified value. If an operand is known to be an register already,
154 /// the setReg method should be used.
155 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
156 bool isKill, bool isDead, bool isUndef,
158 // If this operand is already a register operand, use setReg to update the
159 // register's use/def lists.
161 assert(!isEarlyClobber());
164 // Otherwise, change this to a register and set the reg#.
165 OpKind = MO_Register;
166 SmallContents.RegNo = Reg;
168 // If this operand is embedded in a function, add the operand to the
169 // register's use/def list.
170 if (MachineInstr *MI = getParent())
171 if (MachineBasicBlock *MBB = MI->getParent())
172 if (MachineFunction *MF = MBB->getParent())
173 AddRegOperandToRegInfo(&MF->getRegInfo());
181 IsEarlyClobber = false;
186 /// isIdenticalTo - Return true if this operand is identical to the specified
188 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
189 if (getType() != Other.getType() ||
190 getTargetFlags() != Other.getTargetFlags())
194 default: llvm_unreachable("Unrecognized operand type");
195 case MachineOperand::MO_Register:
196 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
197 getSubReg() == Other.getSubReg();
198 case MachineOperand::MO_Immediate:
199 return getImm() == Other.getImm();
200 case MachineOperand::MO_CImmediate:
201 return getCImm() == Other.getCImm();
202 case MachineOperand::MO_FPImmediate:
203 return getFPImm() == Other.getFPImm();
204 case MachineOperand::MO_MachineBasicBlock:
205 return getMBB() == Other.getMBB();
206 case MachineOperand::MO_FrameIndex:
207 return getIndex() == Other.getIndex();
208 case MachineOperand::MO_ConstantPoolIndex:
209 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
210 case MachineOperand::MO_JumpTableIndex:
211 return getIndex() == Other.getIndex();
212 case MachineOperand::MO_GlobalAddress:
213 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
214 case MachineOperand::MO_ExternalSymbol:
215 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
216 getOffset() == Other.getOffset();
217 case MachineOperand::MO_BlockAddress:
218 return getBlockAddress() == Other.getBlockAddress();
219 case MachineOperand::MO_MCSymbol:
220 return getMCSymbol() == Other.getMCSymbol();
221 case MachineOperand::MO_Metadata:
222 return getMetadata() == Other.getMetadata();
226 /// print - Print the specified machine operand.
228 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
229 // If the instruction is embedded into a basic block, we can find the
230 // target info for the instruction.
232 if (const MachineInstr *MI = getParent())
233 if (const MachineBasicBlock *MBB = MI->getParent())
234 if (const MachineFunction *MF = MBB->getParent())
235 TM = &MF->getTarget();
236 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
239 case MachineOperand::MO_Register:
240 OS << PrintReg(getReg(), TRI, getSubReg());
242 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
245 bool NeedComma = false;
247 if (NeedComma) OS << ',';
248 if (isEarlyClobber())
249 OS << "earlyclobber,";
254 } else if (isImplicit()) {
259 if (isKill() || isDead() || isUndef()) {
260 if (NeedComma) OS << ',';
261 if (isKill()) OS << "kill";
262 if (isDead()) OS << "dead";
264 if (isKill() || isDead())
272 case MachineOperand::MO_Immediate:
275 case MachineOperand::MO_CImmediate:
276 getCImm()->getValue().print(OS, false);
278 case MachineOperand::MO_FPImmediate:
279 if (getFPImm()->getType()->isFloatTy())
280 OS << getFPImm()->getValueAPF().convertToFloat();
282 OS << getFPImm()->getValueAPF().convertToDouble();
284 case MachineOperand::MO_MachineBasicBlock:
285 OS << "<BB#" << getMBB()->getNumber() << ">";
287 case MachineOperand::MO_FrameIndex:
288 OS << "<fi#" << getIndex() << '>';
290 case MachineOperand::MO_ConstantPoolIndex:
291 OS << "<cp#" << getIndex();
292 if (getOffset()) OS << "+" << getOffset();
295 case MachineOperand::MO_JumpTableIndex:
296 OS << "<jt#" << getIndex() << '>';
298 case MachineOperand::MO_GlobalAddress:
300 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
301 if (getOffset()) OS << "+" << getOffset();
304 case MachineOperand::MO_ExternalSymbol:
305 OS << "<es:" << getSymbolName();
306 if (getOffset()) OS << "+" << getOffset();
309 case MachineOperand::MO_BlockAddress:
311 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
314 case MachineOperand::MO_Metadata:
316 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
319 case MachineOperand::MO_MCSymbol:
320 OS << "<MCSym=" << *getMCSymbol() << '>';
323 llvm_unreachable("Unrecognized operand type");
326 if (unsigned TF = getTargetFlags())
327 OS << "[TF=" << TF << ']';
330 //===----------------------------------------------------------------------===//
331 // MachineMemOperand Implementation
332 //===----------------------------------------------------------------------===//
334 /// getAddrSpace - Return the LLVM IR address space number that this pointer
336 unsigned MachinePointerInfo::getAddrSpace() const {
337 if (V == 0) return 0;
338 return cast<PointerType>(V->getType())->getAddressSpace();
341 /// getConstantPool - Return a MachinePointerInfo record that refers to the
343 MachinePointerInfo MachinePointerInfo::getConstantPool() {
344 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
347 /// getFixedStack - Return a MachinePointerInfo record that refers to the
348 /// the specified FrameIndex.
349 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
350 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
353 MachinePointerInfo MachinePointerInfo::getJumpTable() {
354 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
357 MachinePointerInfo MachinePointerInfo::getGOT() {
358 return MachinePointerInfo(PseudoSourceValue::getGOT());
361 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
362 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
365 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
366 uint64_t s, unsigned int a,
367 const MDNode *TBAAInfo)
368 : PtrInfo(ptrinfo), Size(s),
369 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
371 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
372 "invalid pointer value");
373 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
374 assert((isLoad() || isStore()) && "Not a load/store!");
377 /// Profile - Gather unique data for the object.
379 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
380 ID.AddInteger(getOffset());
382 ID.AddPointer(getValue());
383 ID.AddInteger(Flags);
386 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
387 // The Value and Offset may differ due to CSE. But the flags and size
388 // should be the same.
389 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
390 assert(MMO->getSize() == getSize() && "Size mismatch!");
392 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
393 // Update the alignment value.
394 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
395 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
396 // Also update the base and offset, because the new alignment may
397 // not be applicable with the old ones.
398 PtrInfo = MMO->PtrInfo;
402 /// getAlignment - Return the minimum known alignment in bytes of the
403 /// actual memory reference.
404 uint64_t MachineMemOperand::getAlignment() const {
405 return MinAlign(getBaseAlignment(), getOffset());
408 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
409 assert((MMO.isLoad() || MMO.isStore()) &&
410 "SV has to be a load, store or both.");
412 if (MMO.isVolatile())
421 // Print the address information.
426 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
428 // If the alignment of the memory reference itself differs from the alignment
429 // of the base pointer, print the base alignment explicitly, next to the base
431 if (MMO.getBaseAlignment() != MMO.getAlignment())
432 OS << "(align=" << MMO.getBaseAlignment() << ")";
434 if (MMO.getOffset() != 0)
435 OS << "+" << MMO.getOffset();
438 // Print the alignment of the reference.
439 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
440 MMO.getBaseAlignment() != MMO.getSize())
441 OS << "(align=" << MMO.getAlignment() << ")";
444 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
446 if (TBAAInfo->getNumOperands() > 0)
447 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
453 // Print nontemporal info.
454 if (MMO.isNonTemporal())
455 OS << "(nontemporal)";
460 //===----------------------------------------------------------------------===//
461 // MachineInstr Implementation
462 //===----------------------------------------------------------------------===//
464 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
465 /// MCID NULL and no operands.
466 MachineInstr::MachineInstr()
467 : MCID(0), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
468 MemRefs(0), MemRefsEnd(0),
470 // Make sure that we get added to a machine basicblock
471 LeakDetector::addGarbageObject(this);
474 void MachineInstr::addImplicitDefUseOperands() {
475 if (MCID->ImplicitDefs)
476 for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs)
477 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
478 if (MCID->ImplicitUses)
479 for (const unsigned *ImpUses = MCID->ImplicitUses; *ImpUses; ++ImpUses)
480 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
483 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
484 /// implicit operands. It reserves space for the number of operands specified by
486 MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
487 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
488 MemRefs(0), MemRefsEnd(0), Parent(0) {
490 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
491 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
493 addImplicitDefUseOperands();
494 // Make sure that we get added to a machine basicblock
495 LeakDetector::addGarbageObject(this);
498 /// MachineInstr ctor - As above, but with a DebugLoc.
499 MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
501 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
502 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
504 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
505 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
507 addImplicitDefUseOperands();
508 // Make sure that we get added to a machine basicblock
509 LeakDetector::addGarbageObject(this);
512 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
513 /// that the MachineInstr is created and added to the end of the specified
515 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
516 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
517 MemRefs(0), MemRefsEnd(0), Parent(0) {
518 assert(MBB && "Cannot use inserting ctor with null basic block!");
519 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
520 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
521 addImplicitDefUseOperands();
522 // Make sure that we get added to a machine basicblock
523 LeakDetector::addGarbageObject(this);
524 MBB->push_back(this); // Add instruction to end of basic block!
527 /// MachineInstr ctor - As above, but with a DebugLoc.
529 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
530 const MCInstrDesc &tid)
531 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
532 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
533 assert(MBB && "Cannot use inserting ctor with null basic block!");
534 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
535 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
536 addImplicitDefUseOperands();
537 // Make sure that we get added to a machine basicblock
538 LeakDetector::addGarbageObject(this);
539 MBB->push_back(this); // Add instruction to end of basic block!
542 /// MachineInstr ctor - Copies MachineInstr arg exactly
544 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
545 : MCID(&MI.getDesc()), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
546 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
547 Parent(0), debugLoc(MI.getDebugLoc()) {
548 Operands.reserve(MI.getNumOperands());
551 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
552 addOperand(MI.getOperand(i));
553 NumImplicitOps = MI.NumImplicitOps;
555 // Copy all the flags.
558 // Set parent to null.
561 LeakDetector::addGarbageObject(this);
564 MachineInstr::~MachineInstr() {
565 LeakDetector::removeGarbageObject(this);
567 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
568 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
569 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
570 "Reg operand def/use list corrupted");
575 /// getRegInfo - If this instruction is embedded into a MachineFunction,
576 /// return the MachineRegisterInfo object for the current function, otherwise
578 MachineRegisterInfo *MachineInstr::getRegInfo() {
579 if (MachineBasicBlock *MBB = getParent())
580 return &MBB->getParent()->getRegInfo();
584 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
585 /// this instruction from their respective use lists. This requires that the
586 /// operands already be on their use lists.
587 void MachineInstr::RemoveRegOperandsFromUseLists() {
588 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
589 if (Operands[i].isReg())
590 Operands[i].RemoveRegOperandFromRegInfo();
594 /// AddRegOperandsToUseLists - Add all of the register operands in
595 /// this instruction from their respective use lists. This requires that the
596 /// operands not be on their use lists yet.
597 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
598 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
599 if (Operands[i].isReg())
600 Operands[i].AddRegOperandToRegInfo(&RegInfo);
605 /// addOperand - Add the specified operand to the instruction. If it is an
606 /// implicit operand, it is added to the end of the operand list. If it is
607 /// an explicit operand it is added at the end of the explicit operand list
608 /// (before the first implicit operand).
609 void MachineInstr::addOperand(const MachineOperand &Op) {
610 bool isImpReg = Op.isReg() && Op.isImplicit();
611 assert((isImpReg || !OperandsComplete()) &&
612 "Trying to add an operand to a machine instr that is already done!");
614 MachineRegisterInfo *RegInfo = getRegInfo();
616 // If we are adding the operand to the end of the list, our job is simpler.
617 // This is true most of the time, so this is a reasonable optimization.
618 if (isImpReg || NumImplicitOps == 0) {
619 // We can only do this optimization if we know that the operand list won't
621 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
622 Operands.push_back(Op);
624 // Set the parent of the operand.
625 Operands.back().ParentMI = this;
627 // If the operand is a register, update the operand's use list.
629 Operands.back().AddRegOperandToRegInfo(RegInfo);
630 // If the register operand is flagged as early, mark the operand as such
631 unsigned OpNo = Operands.size() - 1;
632 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
633 Operands[OpNo].setIsEarlyClobber(true);
639 // Otherwise, we have to insert a real operand before any implicit ones.
640 unsigned OpNo = Operands.size()-NumImplicitOps;
642 // If this instruction isn't embedded into a function, then we don't need to
643 // update any operand lists.
645 // Simple insertion, no reginfo update needed for other register operands.
646 Operands.insert(Operands.begin()+OpNo, Op);
647 Operands[OpNo].ParentMI = this;
649 // Do explicitly set the reginfo for this operand though, to ensure the
650 // next/prev fields are properly nulled out.
651 if (Operands[OpNo].isReg()) {
652 Operands[OpNo].AddRegOperandToRegInfo(0);
653 // If the register operand is flagged as early, mark the operand as such
654 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
655 Operands[OpNo].setIsEarlyClobber(true);
658 } else if (Operands.size()+1 <= Operands.capacity()) {
659 // Otherwise, we have to remove register operands from their register use
660 // list, add the operand, then add the register operands back to their use
661 // list. This also must handle the case when the operand list reallocates
662 // to somewhere else.
664 // If insertion of this operand won't cause reallocation of the operand
665 // list, just remove the implicit operands, add the operand, then re-add all
666 // the rest of the operands.
667 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
668 assert(Operands[i].isReg() && "Should only be an implicit reg!");
669 Operands[i].RemoveRegOperandFromRegInfo();
672 // Add the operand. If it is a register, add it to the reg list.
673 Operands.insert(Operands.begin()+OpNo, Op);
674 Operands[OpNo].ParentMI = this;
676 if (Operands[OpNo].isReg()) {
677 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
678 // If the register operand is flagged as early, mark the operand as such
679 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
680 Operands[OpNo].setIsEarlyClobber(true);
683 // Re-add all the implicit ops.
684 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
685 assert(Operands[i].isReg() && "Should only be an implicit reg!");
686 Operands[i].AddRegOperandToRegInfo(RegInfo);
689 // Otherwise, we will be reallocating the operand list. Remove all reg
690 // operands from their list, then readd them after the operand list is
692 RemoveRegOperandsFromUseLists();
694 Operands.insert(Operands.begin()+OpNo, Op);
695 Operands[OpNo].ParentMI = this;
697 // Re-add all the operands.
698 AddRegOperandsToUseLists(*RegInfo);
700 // If the register operand is flagged as early, mark the operand as such
701 if (Operands[OpNo].isReg()
702 && MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
703 Operands[OpNo].setIsEarlyClobber(true);
707 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
708 /// fewer operand than it started with.
710 void MachineInstr::RemoveOperand(unsigned OpNo) {
711 assert(OpNo < Operands.size() && "Invalid operand number");
713 // Special case removing the last one.
714 if (OpNo == Operands.size()-1) {
715 // If needed, remove from the reg def/use list.
716 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
717 Operands.back().RemoveRegOperandFromRegInfo();
723 // Otherwise, we are removing an interior operand. If we have reginfo to
724 // update, remove all operands that will be shifted down from their reg lists,
725 // move everything down, then re-add them.
726 MachineRegisterInfo *RegInfo = getRegInfo();
728 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
729 if (Operands[i].isReg())
730 Operands[i].RemoveRegOperandFromRegInfo();
734 Operands.erase(Operands.begin()+OpNo);
737 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
738 if (Operands[i].isReg())
739 Operands[i].AddRegOperandToRegInfo(RegInfo);
744 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
745 /// This function should be used only occasionally. The setMemRefs function
746 /// is the primary method for setting up a MachineInstr's MemRefs list.
747 void MachineInstr::addMemOperand(MachineFunction &MF,
748 MachineMemOperand *MO) {
749 mmo_iterator OldMemRefs = MemRefs;
750 mmo_iterator OldMemRefsEnd = MemRefsEnd;
752 size_t NewNum = (MemRefsEnd - MemRefs) + 1;
753 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
754 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
756 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
757 NewMemRefs[NewNum - 1] = MO;
759 MemRefs = NewMemRefs;
760 MemRefsEnd = NewMemRefsEnd;
763 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
764 MICheckType Check) const {
765 // If opcodes or number of operands are not the same then the two
766 // instructions are obviously not identical.
767 if (Other->getOpcode() != getOpcode() ||
768 Other->getNumOperands() != getNumOperands())
771 // Check operands to make sure they match.
772 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
773 const MachineOperand &MO = getOperand(i);
774 const MachineOperand &OMO = Other->getOperand(i);
776 if (!MO.isIdenticalTo(OMO))
781 // Clients may or may not want to ignore defs when testing for equality.
782 // For example, machine CSE pass only cares about finding common
783 // subexpressions, so it's safe to ignore virtual register defs.
785 if (Check == IgnoreDefs)
787 else if (Check == IgnoreVRegDefs) {
788 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
789 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
790 if (MO.getReg() != OMO.getReg())
793 if (!MO.isIdenticalTo(OMO))
795 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
799 if (!MO.isIdenticalTo(OMO))
801 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
805 // If DebugLoc does not match then two dbg.values are not identical.
807 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
808 && getDebugLoc() != Other->getDebugLoc())
813 /// removeFromParent - This method unlinks 'this' from the containing basic
814 /// block, and returns it, but does not delete it.
815 MachineInstr *MachineInstr::removeFromParent() {
816 assert(getParent() && "Not embedded in a basic block!");
817 getParent()->remove(this);
822 /// eraseFromParent - This method unlinks 'this' from the containing basic
823 /// block, and deletes it.
824 void MachineInstr::eraseFromParent() {
825 assert(getParent() && "Not embedded in a basic block!");
826 getParent()->erase(this);
830 /// OperandComplete - Return true if it's illegal to add a new operand
832 bool MachineInstr::OperandsComplete() const {
833 unsigned short NumOperands = MCID->getNumOperands();
834 if (!MCID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
835 return true; // Broken: we have all the operands of this instruction!
839 /// getNumExplicitOperands - Returns the number of non-implicit operands.
841 unsigned MachineInstr::getNumExplicitOperands() const {
842 unsigned NumOperands = MCID->getNumOperands();
843 if (!MCID->isVariadic())
846 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
847 const MachineOperand &MO = getOperand(i);
848 if (!MO.isReg() || !MO.isImplicit())
854 bool MachineInstr::isStackAligningInlineAsm() const {
856 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
857 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
863 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
864 /// the specific register or -1 if it is not found. It further tightens
865 /// the search criteria to a use that kills the register if isKill is true.
866 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
867 const TargetRegisterInfo *TRI) const {
868 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
869 const MachineOperand &MO = getOperand(i);
870 if (!MO.isReg() || !MO.isUse())
872 unsigned MOReg = MO.getReg();
877 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
878 TargetRegisterInfo::isPhysicalRegister(Reg) &&
879 TRI->isSubRegister(MOReg, Reg)))
880 if (!isKill || MO.isKill())
886 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
887 /// indicating if this instruction reads or writes Reg. This also considers
890 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
891 SmallVectorImpl<unsigned> *Ops) const {
892 bool PartDef = false; // Partial redefine.
893 bool FullDef = false; // Full define.
896 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
897 const MachineOperand &MO = getOperand(i);
898 if (!MO.isReg() || MO.getReg() != Reg)
903 Use |= !MO.isUndef();
904 else if (MO.getSubReg() && !MO.isUndef())
905 // A partial <def,undef> doesn't count as reading the register.
910 // A partial redefine uses Reg unless there is also a full define.
911 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
914 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
915 /// the specified register or -1 if it is not found. If isDead is true, defs
916 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
917 /// also checks if there is a def of a super-register.
919 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
920 const TargetRegisterInfo *TRI) const {
921 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
922 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
923 const MachineOperand &MO = getOperand(i);
924 if (!MO.isReg() || !MO.isDef())
926 unsigned MOReg = MO.getReg();
927 bool Found = (MOReg == Reg);
928 if (!Found && TRI && isPhys &&
929 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
931 Found = TRI->regsOverlap(MOReg, Reg);
933 Found = TRI->isSubRegister(MOReg, Reg);
935 if (Found && (!isDead || MO.isDead()))
941 /// findFirstPredOperandIdx() - Find the index of the first operand in the
942 /// operand list that is used to represent the predicate. It returns -1 if
944 int MachineInstr::findFirstPredOperandIdx() const {
945 // Don't call MCID.findFirstPredOperandIdx() because this variant
946 // is sometimes called on an instruction that's not yet complete, and
947 // so the number of operands is less than the MCID indicates. In
948 // particular, the PTX target does this.
949 const MCInstrDesc &MCID = getDesc();
950 if (MCID.isPredicable()) {
951 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
952 if (MCID.OpInfo[i].isPredicate())
959 /// isRegTiedToUseOperand - Given the index of a register def operand,
960 /// check if the register def is tied to a source operand, due to either
961 /// two-address elimination or inline assembly constraints. Returns the
962 /// first tied use operand index by reference is UseOpIdx is not null.
964 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
966 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
967 const MachineOperand &MO = getOperand(DefOpIdx);
968 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
970 // Determine the actual operand index that corresponds to this index.
972 unsigned DefPart = 0;
973 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
975 const MachineOperand &FMO = getOperand(i);
976 // After the normal asm operands there may be additional imp-def regs.
979 // Skip over this def.
980 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
981 unsigned PrevDef = i + 1;
982 i = PrevDef + NumOps;
984 DefPart = DefOpIdx - PrevDef;
989 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
991 const MachineOperand &FMO = getOperand(i);
994 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
997 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
1000 *UseOpIdx = (unsigned)i + 1 + DefPart;
1007 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
1008 const MCInstrDesc &MCID = getDesc();
1009 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
1010 const MachineOperand &MO = getOperand(i);
1011 if (MO.isReg() && MO.isUse() &&
1012 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
1014 *UseOpIdx = (unsigned)i;
1021 /// isRegTiedToDefOperand - Return true if the operand of the specified index
1022 /// is a register use and it is tied to an def operand. It also returns the def
1023 /// operand index by reference.
1025 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
1026 if (isInlineAsm()) {
1027 const MachineOperand &MO = getOperand(UseOpIdx);
1028 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
1031 // Find the flag operand corresponding to UseOpIdx
1032 unsigned FlagIdx, NumOps=0;
1033 for (FlagIdx = InlineAsm::MIOp_FirstOperand;
1034 FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
1035 const MachineOperand &UFMO = getOperand(FlagIdx);
1036 // After the normal asm operands there may be additional imp-def regs.
1039 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
1040 assert(NumOps < getNumOperands() && "Invalid inline asm flag");
1041 if (UseOpIdx < FlagIdx+NumOps+1)
1044 if (FlagIdx >= UseOpIdx)
1046 const MachineOperand &UFMO = getOperand(FlagIdx);
1048 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1052 unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1053 // Remember to adjust the index. First operand is asm string, second is
1054 // the HasSideEffects and AlignStack bits, then there is a flag for each.
1056 const MachineOperand &FMO = getOperand(DefIdx);
1057 assert(FMO.isImm());
1058 // Skip over this def.
1059 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1062 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1068 const MCInstrDesc &MCID = getDesc();
1069 if (UseOpIdx >= MCID.getNumOperands())
1071 const MachineOperand &MO = getOperand(UseOpIdx);
1072 if (!MO.isReg() || !MO.isUse())
1074 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
1078 *DefOpIdx = (unsigned)DefIdx;
1082 /// clearKillInfo - Clears kill flags on all operands.
1084 void MachineInstr::clearKillInfo() {
1085 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1086 MachineOperand &MO = getOperand(i);
1087 if (MO.isReg() && MO.isUse())
1088 MO.setIsKill(false);
1092 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1094 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1095 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1096 const MachineOperand &MO = MI->getOperand(i);
1097 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1099 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1100 MachineOperand &MOp = getOperand(j);
1101 if (!MOp.isIdenticalTo(MO))
1112 /// copyPredicates - Copies predicate operand(s) from MI.
1113 void MachineInstr::copyPredicates(const MachineInstr *MI) {
1114 const MCInstrDesc &MCID = MI->getDesc();
1115 if (!MCID.isPredicable())
1117 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1118 if (MCID.OpInfo[i].isPredicate()) {
1119 // Predicated operands must be last operands.
1120 addOperand(MI->getOperand(i));
1125 void MachineInstr::substituteRegister(unsigned FromReg,
1128 const TargetRegisterInfo &RegInfo) {
1129 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1131 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1132 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1133 MachineOperand &MO = getOperand(i);
1134 if (!MO.isReg() || MO.getReg() != FromReg)
1136 MO.substPhysReg(ToReg, RegInfo);
1139 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1140 MachineOperand &MO = getOperand(i);
1141 if (!MO.isReg() || MO.getReg() != FromReg)
1143 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1148 /// isSafeToMove - Return true if it is safe to move this instruction. If
1149 /// SawStore is set to true, it means that there is a store (or call) between
1150 /// the instruction's location and its intended destination.
1151 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1153 bool &SawStore) const {
1154 // Ignore stuff that we obviously can't move.
1155 if (MCID->mayStore() || MCID->isCall()) {
1160 if (isLabel() || isDebugValue() ||
1161 MCID->isTerminator() || hasUnmodeledSideEffects())
1164 // See if this instruction does a load. If so, we have to guarantee that the
1165 // loaded value doesn't change between the load and the its intended
1166 // destination. The check for isInvariantLoad gives the targe the chance to
1167 // classify the load as always returning a constant, e.g. a constant pool
1169 if (MCID->mayLoad() && !isInvariantLoad(AA))
1170 // Otherwise, this is a real load. If there is a store between the load and
1171 // end of block, or if the load is volatile, we can't move it.
1172 return !SawStore && !hasVolatileMemoryRef();
1177 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1178 /// instruction which defined the specified register instead of copying it.
1179 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1181 unsigned DstReg) const {
1182 bool SawStore = false;
1183 if (!TII->isTriviallyReMaterializable(this, AA) ||
1184 !isSafeToMove(TII, AA, SawStore))
1186 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1187 const MachineOperand &MO = getOperand(i);
1190 // FIXME: For now, do not remat any instruction with register operands.
1191 // Later on, we can loosen the restriction is the register operands have
1192 // not been modified between the def and use. Note, this is different from
1193 // MachineSink because the code is no longer in two-address form (at least
1197 else if (!MO.isDead() && MO.getReg() != DstReg)
1203 /// hasVolatileMemoryRef - Return true if this instruction may have a
1204 /// volatile memory reference, or if the information describing the
1205 /// memory reference is not available. Return false if it is known to
1206 /// have no volatile memory references.
1207 bool MachineInstr::hasVolatileMemoryRef() const {
1208 // An instruction known never to access memory won't have a volatile access.
1209 if (!MCID->mayStore() &&
1212 !hasUnmodeledSideEffects())
1215 // Otherwise, if the instruction has no memory reference information,
1216 // conservatively assume it wasn't preserved.
1217 if (memoperands_empty())
1220 // Check the memory reference information for volatile references.
1221 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1222 if ((*I)->isVolatile())
1228 /// isInvariantLoad - Return true if this instruction is loading from a
1229 /// location whose value is invariant across the function. For example,
1230 /// loading a value from the constant pool or from the argument area
1231 /// of a function if it does not change. This should only return true of
1232 /// *all* loads the instruction does are invariant (if it does multiple loads).
1233 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1234 // If the instruction doesn't load at all, it isn't an invariant load.
1235 if (!MCID->mayLoad())
1238 // If the instruction has lost its memoperands, conservatively assume that
1239 // it may not be an invariant load.
1240 if (memoperands_empty())
1243 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1245 for (mmo_iterator I = memoperands_begin(),
1246 E = memoperands_end(); I != E; ++I) {
1247 if ((*I)->isVolatile()) return false;
1248 if ((*I)->isStore()) return false;
1250 if (const Value *V = (*I)->getValue()) {
1251 // A load from a constant PseudoSourceValue is invariant.
1252 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1253 if (PSV->isConstant(MFI))
1255 // If we have an AliasAnalysis, ask it whether the memory is constant.
1256 if (AA && AA->pointsToConstantMemory(
1257 AliasAnalysis::Location(V, (*I)->getSize(),
1258 (*I)->getTBAAInfo())))
1262 // Otherwise assume conservatively.
1266 // Everything checks out.
1270 /// isConstantValuePHI - If the specified instruction is a PHI that always
1271 /// merges together the same virtual register, return the register, otherwise
1273 unsigned MachineInstr::isConstantValuePHI() const {
1276 assert(getNumOperands() >= 3 &&
1277 "It's illegal to have a PHI without source operands");
1279 unsigned Reg = getOperand(1).getReg();
1280 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1281 if (getOperand(i).getReg() != Reg)
1286 bool MachineInstr::hasUnmodeledSideEffects() const {
1287 if (getDesc().hasUnmodeledSideEffects())
1289 if (isInlineAsm()) {
1290 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1291 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1298 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1300 bool MachineInstr::allDefsAreDead() const {
1301 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1302 const MachineOperand &MO = getOperand(i);
1303 if (!MO.isReg() || MO.isUse())
1311 /// copyImplicitOps - Copy implicit register operands from specified
1312 /// instruction to this instruction.
1313 void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1314 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1316 const MachineOperand &MO = MI->getOperand(i);
1317 if (MO.isReg() && MO.isImplicit())
1322 void MachineInstr::dump() const {
1323 dbgs() << " " << *this;
1326 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1327 raw_ostream &CommentOS) {
1328 const LLVMContext &Ctx = MF->getFunction()->getContext();
1329 if (!DL.isUnknown()) { // Print source line info.
1330 DIScope Scope(DL.getScope(Ctx));
1331 // Omit the directory, because it's likely to be long and uninteresting.
1333 CommentOS << Scope.getFilename();
1335 CommentOS << "<unknown>";
1336 CommentOS << ':' << DL.getLine();
1337 if (DL.getCol() != 0)
1338 CommentOS << ':' << DL.getCol();
1339 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1340 if (!InlinedAtDL.isUnknown()) {
1341 CommentOS << " @[ ";
1342 printDebugLoc(InlinedAtDL, MF, CommentOS);
1348 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1349 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1350 const MachineFunction *MF = 0;
1351 const MachineRegisterInfo *MRI = 0;
1352 if (const MachineBasicBlock *MBB = getParent()) {
1353 MF = MBB->getParent();
1355 TM = &MF->getTarget();
1357 MRI = &MF->getRegInfo();
1360 // Save a list of virtual registers.
1361 SmallVector<unsigned, 8> VirtRegs;
1363 // Print explicitly defined operands on the left of an assignment syntax.
1364 unsigned StartOp = 0, e = getNumOperands();
1365 for (; StartOp < e && getOperand(StartOp).isReg() &&
1366 getOperand(StartOp).isDef() &&
1367 !getOperand(StartOp).isImplicit();
1369 if (StartOp != 0) OS << ", ";
1370 getOperand(StartOp).print(OS, TM);
1371 unsigned Reg = getOperand(StartOp).getReg();
1372 if (TargetRegisterInfo::isVirtualRegister(Reg))
1373 VirtRegs.push_back(Reg);
1379 // Print the opcode name.
1380 OS << getDesc().getName();
1382 // Print the rest of the operands.
1383 bool OmittedAnyCallClobbers = false;
1384 bool FirstOp = true;
1385 unsigned AsmDescOp = ~0u;
1386 unsigned AsmOpCount = 0;
1388 if (isInlineAsm()) {
1389 // Print asm string.
1391 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1393 // Print HasSideEffects, IsAlignStack
1394 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1395 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1396 OS << " [sideeffect]";
1397 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1398 OS << " [alignstack]";
1400 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1405 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1406 const MachineOperand &MO = getOperand(i);
1408 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1409 VirtRegs.push_back(MO.getReg());
1411 // Omit call-clobbered registers which aren't used anywhere. This makes
1412 // call instructions much less noisy on targets where calls clobber lots
1413 // of registers. Don't rely on MO.isDead() because we may be called before
1414 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1415 if (MF && getDesc().isCall() &&
1416 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1417 unsigned Reg = MO.getReg();
1418 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1419 const MachineRegisterInfo &MRI = MF->getRegInfo();
1420 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1421 bool HasAliasLive = false;
1422 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1423 unsigned AliasReg = *Alias; ++Alias)
1424 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1425 HasAliasLive = true;
1428 if (!HasAliasLive) {
1429 OmittedAnyCallClobbers = true;
1436 if (FirstOp) FirstOp = false; else OS << ",";
1438 if (i < getDesc().NumOperands) {
1439 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1440 if (MCOI.isPredicate())
1442 if (MCOI.isOptionalDef())
1445 if (isDebugValue() && MO.isMetadata()) {
1446 // Pretty print DBG_VALUE instructions.
1447 const MDNode *MD = MO.getMetadata();
1448 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1449 OS << "!\"" << MDS->getString() << '\"';
1452 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1453 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1454 } else if (i == AsmDescOp && MO.isImm()) {
1455 // Pretty print the inline asm operand descriptor.
1456 OS << '$' << AsmOpCount++;
1457 unsigned Flag = MO.getImm();
1458 switch (InlineAsm::getKind(Flag)) {
1459 case InlineAsm::Kind_RegUse: OS << ":[reguse]"; break;
1460 case InlineAsm::Kind_RegDef: OS << ":[regdef]"; break;
1461 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec]"; break;
1462 case InlineAsm::Kind_Clobber: OS << ":[clobber]"; break;
1463 case InlineAsm::Kind_Imm: OS << ":[imm]"; break;
1464 case InlineAsm::Kind_Mem: OS << ":[mem]"; break;
1465 default: OS << ":[??" << InlineAsm::getKind(Flag) << ']'; break;
1468 unsigned TiedTo = 0;
1469 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1470 OS << " [tiedto:$" << TiedTo << ']';
1472 // Compute the index of the next operand descriptor.
1473 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1478 // Briefly indicate whether any call clobbers were omitted.
1479 if (OmittedAnyCallClobbers) {
1480 if (!FirstOp) OS << ",";
1484 bool HaveSemi = false;
1486 if (!HaveSemi) OS << ";"; HaveSemi = true;
1489 if (Flags & FrameSetup)
1493 if (!memoperands_empty()) {
1494 if (!HaveSemi) OS << ";"; HaveSemi = true;
1497 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1500 if (llvm::next(i) != e)
1505 // Print the regclass of any virtual registers encountered.
1506 if (MRI && !VirtRegs.empty()) {
1507 if (!HaveSemi) OS << ";"; HaveSemi = true;
1508 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1509 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1510 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1511 for (unsigned j = i+1; j != VirtRegs.size();) {
1512 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1516 if (VirtRegs[i] != VirtRegs[j])
1517 OS << "," << PrintReg(VirtRegs[j]);
1518 VirtRegs.erase(VirtRegs.begin()+j);
1523 // Print debug location information.
1524 if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1525 if (!HaveSemi) OS << ";"; HaveSemi = true;
1526 DIVariable DV(getOperand(e - 1).getMetadata());
1527 OS << " line no:" << DV.getLineNumber();
1528 if (MDNode *InlinedAt = DV.getInlinedAt()) {
1529 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1530 if (!InlinedAtDL.isUnknown()) {
1531 OS << " inlined @[ ";
1532 printDebugLoc(InlinedAtDL, MF, OS);
1536 } else if (!debugLoc.isUnknown() && MF) {
1537 if (!HaveSemi) OS << ";"; HaveSemi = true;
1539 printDebugLoc(debugLoc, MF, OS);
1545 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1546 const TargetRegisterInfo *RegInfo,
1547 bool AddIfNotFound) {
1548 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1549 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1551 SmallVector<unsigned,4> DeadOps;
1552 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1553 MachineOperand &MO = getOperand(i);
1554 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1556 unsigned Reg = MO.getReg();
1560 if (Reg == IncomingReg) {
1563 // The register is already marked kill.
1565 if (isPhysReg && isRegTiedToDefOperand(i))
1566 // Two-address uses of physregs must not be marked kill.
1571 } else if (hasAliases && MO.isKill() &&
1572 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1573 // A super-register kill already exists.
1574 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1576 if (RegInfo->isSubRegister(IncomingReg, Reg))
1577 DeadOps.push_back(i);
1581 // Trim unneeded kill operands.
1582 while (!DeadOps.empty()) {
1583 unsigned OpIdx = DeadOps.back();
1584 if (getOperand(OpIdx).isImplicit())
1585 RemoveOperand(OpIdx);
1587 getOperand(OpIdx).setIsKill(false);
1591 // If not found, this means an alias of one of the operands is killed. Add a
1592 // new implicit operand if required.
1593 if (!Found && AddIfNotFound) {
1594 addOperand(MachineOperand::CreateReg(IncomingReg,
1603 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1604 const TargetRegisterInfo *RegInfo,
1605 bool AddIfNotFound) {
1606 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1607 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1609 SmallVector<unsigned,4> DeadOps;
1610 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1611 MachineOperand &MO = getOperand(i);
1612 if (!MO.isReg() || !MO.isDef())
1614 unsigned Reg = MO.getReg();
1618 if (Reg == IncomingReg) {
1621 } else if (hasAliases && MO.isDead() &&
1622 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1623 // There exists a super-register that's marked dead.
1624 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1626 if (RegInfo->getSubRegisters(IncomingReg) &&
1627 RegInfo->getSuperRegisters(Reg) &&
1628 RegInfo->isSubRegister(IncomingReg, Reg))
1629 DeadOps.push_back(i);
1633 // Trim unneeded dead operands.
1634 while (!DeadOps.empty()) {
1635 unsigned OpIdx = DeadOps.back();
1636 if (getOperand(OpIdx).isImplicit())
1637 RemoveOperand(OpIdx);
1639 getOperand(OpIdx).setIsDead(false);
1643 // If not found, this means an alias of one of the operands is dead. Add a
1644 // new implicit operand if required.
1645 if (Found || !AddIfNotFound)
1648 addOperand(MachineOperand::CreateReg(IncomingReg,
1656 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1657 const TargetRegisterInfo *RegInfo) {
1658 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1659 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1663 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1664 const MachineOperand &MO = getOperand(i);
1665 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1666 MO.getSubReg() == 0)
1670 addOperand(MachineOperand::CreateReg(IncomingReg,
1675 void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
1676 const TargetRegisterInfo &TRI) {
1677 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1678 MachineOperand &MO = getOperand(i);
1679 if (!MO.isReg() || !MO.isDef()) continue;
1680 unsigned Reg = MO.getReg();
1681 if (Reg == 0) continue;
1683 for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
1684 E = UsedRegs.end(); I != E; ++I)
1685 if (TRI.regsOverlap(*I, Reg)) {
1689 // If there are no uses, including partial uses, the def is dead.
1690 if (Dead) MO.setIsDead();
1695 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1696 unsigned Hash = MI->getOpcode() * 37;
1697 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1698 const MachineOperand &MO = MI->getOperand(i);
1699 uint64_t Key = (uint64_t)MO.getType() << 32;
1700 switch (MO.getType()) {
1702 case MachineOperand::MO_Register:
1703 if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1704 continue; // Skip virtual register defs.
1707 case MachineOperand::MO_Immediate:
1710 case MachineOperand::MO_FrameIndex:
1711 case MachineOperand::MO_ConstantPoolIndex:
1712 case MachineOperand::MO_JumpTableIndex:
1713 Key |= MO.getIndex();
1715 case MachineOperand::MO_MachineBasicBlock:
1716 Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1718 case MachineOperand::MO_GlobalAddress:
1719 Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1721 case MachineOperand::MO_BlockAddress:
1722 Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1724 case MachineOperand::MO_MCSymbol:
1725 Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1728 Key += ~(Key << 32);
1730 Key += ~(Key << 13);
1734 Key += ~(Key << 27);
1736 Hash = (unsigned)Key + Hash * 37;
1741 void MachineInstr::emitError(StringRef Msg) const {
1742 // Find the source location cookie.
1743 unsigned LocCookie = 0;
1744 const MDNode *LocMD = 0;
1745 for (unsigned i = getNumOperands(); i != 0; --i) {
1746 if (getOperand(i-1).isMetadata() &&
1747 (LocMD = getOperand(i-1).getMetadata()) &&
1748 LocMD->getNumOperands() != 0) {
1749 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1750 LocCookie = CI->getZExtValue();
1756 if (const MachineBasicBlock *MBB = getParent())
1757 if (const MachineFunction *MF = MBB->getParent())
1758 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1759 report_fatal_error(Msg);