1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Value.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/TargetInstrDesc.h"
21 #include "llvm/Target/MRegisterInfo.h"
22 #include "llvm/Support/LeakDetector.h"
23 #include "llvm/Support/Streams.h"
27 //===----------------------------------------------------------------------===//
28 // MachineOperand Implementation
29 //===----------------------------------------------------------------------===//
31 /// AddRegOperandToRegInfo - Add this register operand to the specified
32 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
33 /// explicitly nulled out.
34 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
35 assert(isReg() && "Can only add reg operand to use lists");
37 // If the reginfo pointer is null, just explicitly null out or next/prev
38 // pointers, to ensure they are not garbage.
40 Contents.Reg.Prev = 0;
41 Contents.Reg.Next = 0;
45 // Otherwise, add this operand to the head of the registers use/def list.
46 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
48 // For SSA values, we prefer to keep the definition at the start of the list.
49 // we do this by skipping over the definition if it is at the head of the
51 if (*Head && (*Head)->isDef())
52 Head = &(*Head)->Contents.Reg.Next;
54 Contents.Reg.Next = *Head;
55 if (Contents.Reg.Next) {
56 assert(getReg() == Contents.Reg.Next->getReg() &&
57 "Different regs on the same list!");
58 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
61 Contents.Reg.Prev = Head;
65 void MachineOperand::setReg(unsigned Reg) {
66 if (getReg() == Reg) return; // No change.
68 // Otherwise, we have to change the register. If this operand is embedded
69 // into a machine function, we need to update the old and new register's
71 if (MachineInstr *MI = getParent())
72 if (MachineBasicBlock *MBB = MI->getParent())
73 if (MachineFunction *MF = MBB->getParent()) {
74 RemoveRegOperandFromRegInfo();
75 Contents.Reg.RegNo = Reg;
76 AddRegOperandToRegInfo(&MF->getRegInfo());
80 // Otherwise, just change the register, no problem. :)
81 Contents.Reg.RegNo = Reg;
84 /// ChangeToImmediate - Replace this operand with a new immediate operand of
85 /// the specified value. If an operand is known to be an immediate already,
86 /// the setImm method should be used.
87 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
88 // If this operand is currently a register operand, and if this is in a
89 // function, deregister the operand from the register's use/def list.
90 if (isReg() && getParent() && getParent()->getParent() &&
91 getParent()->getParent()->getParent())
92 RemoveRegOperandFromRegInfo();
94 OpKind = MO_Immediate;
95 Contents.ImmVal = ImmVal;
98 /// ChangeToRegister - Replace this operand with a new register operand of
99 /// the specified value. If an operand is known to be an register already,
100 /// the setReg method should be used.
101 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
102 bool isKill, bool isDead) {
103 // If this operand is already a register operand, use setReg to update the
104 // register's use/def lists.
108 // Otherwise, change this to a register and set the reg#.
109 OpKind = MO_Register;
110 Contents.Reg.RegNo = Reg;
112 // If this operand is embedded in a function, add the operand to the
113 // register's use/def list.
114 if (MachineInstr *MI = getParent())
115 if (MachineBasicBlock *MBB = MI->getParent())
116 if (MachineFunction *MF = MBB->getParent())
117 AddRegOperandToRegInfo(&MF->getRegInfo());
127 /// isIdenticalTo - Return true if this operand is identical to the specified
129 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
130 if (getType() != Other.getType()) return false;
133 default: assert(0 && "Unrecognized operand type");
134 case MachineOperand::MO_Register:
135 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
136 getSubReg() == Other.getSubReg();
137 case MachineOperand::MO_Immediate:
138 return getImm() == Other.getImm();
139 case MachineOperand::MO_MachineBasicBlock:
140 return getMBB() == Other.getMBB();
141 case MachineOperand::MO_FrameIndex:
142 return getIndex() == Other.getIndex();
143 case MachineOperand::MO_ConstantPoolIndex:
144 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
145 case MachineOperand::MO_JumpTableIndex:
146 return getIndex() == Other.getIndex();
147 case MachineOperand::MO_GlobalAddress:
148 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
149 case MachineOperand::MO_ExternalSymbol:
150 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
151 getOffset() == Other.getOffset();
155 /// print - Print the specified machine operand.
157 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
159 case MachineOperand::MO_Register:
160 if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) {
161 OS << "%reg" << getReg();
163 // If the instruction is embedded into a basic block, we can find the
164 // target info for the instruction.
166 if (const MachineInstr *MI = getParent())
167 if (const MachineBasicBlock *MBB = MI->getParent())
168 if (const MachineFunction *MF = MBB->getParent())
169 TM = &MF->getTarget();
172 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
174 OS << "%mreg" << getReg();
177 if (isDef() || isKill() || isDead() || isImplicit()) {
179 bool NeedComma = false;
181 OS << (isDef() ? "imp-def" : "imp-use");
183 } else if (isDef()) {
187 if (isKill() || isDead()) {
188 if (NeedComma) OS << ",";
189 if (isKill()) OS << "kill";
190 if (isDead()) OS << "dead";
195 case MachineOperand::MO_Immediate:
198 case MachineOperand::MO_MachineBasicBlock:
200 << ((Value*)getMBB()->getBasicBlock())->getName()
201 << "," << (void*)getMBB() << ">";
203 case MachineOperand::MO_FrameIndex:
204 OS << "<fi#" << getIndex() << ">";
206 case MachineOperand::MO_ConstantPoolIndex:
207 OS << "<cp#" << getIndex();
208 if (getOffset()) OS << "+" << getOffset();
211 case MachineOperand::MO_JumpTableIndex:
212 OS << "<jt#" << getIndex() << ">";
214 case MachineOperand::MO_GlobalAddress:
215 OS << "<ga:" << ((Value*)getGlobal())->getName();
216 if (getOffset()) OS << "+" << getOffset();
219 case MachineOperand::MO_ExternalSymbol:
220 OS << "<es:" << getSymbolName();
221 if (getOffset()) OS << "+" << getOffset();
225 assert(0 && "Unrecognized operand type");
229 //===----------------------------------------------------------------------===//
230 // MachineInstr Implementation
231 //===----------------------------------------------------------------------===//
233 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
234 /// TID NULL and no operands.
235 MachineInstr::MachineInstr()
236 : TID(0), NumImplicitOps(0), Parent(0) {
237 // Make sure that we get added to a machine basicblock
238 LeakDetector::addGarbageObject(this);
241 void MachineInstr::addImplicitDefUseOperands() {
242 if (TID->ImplicitDefs)
243 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
244 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
245 if (TID->ImplicitUses)
246 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
247 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
250 /// MachineInstr ctor - This constructor create a MachineInstr and add the
251 /// implicit operands. It reserves space for number of operands specified by
252 /// TargetInstrDesc or the numOperands if it is not zero. (for
253 /// instructions with variable number of operands).
254 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
255 : TID(&tid), NumImplicitOps(0), Parent(0) {
256 if (!NoImp && TID->getImplicitDefs())
257 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
259 if (!NoImp && TID->getImplicitUses())
260 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
262 Operands.reserve(NumImplicitOps + TID->getNumOperands());
264 addImplicitDefUseOperands();
265 // Make sure that we get added to a machine basicblock
266 LeakDetector::addGarbageObject(this);
269 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
270 /// MachineInstr is created and added to the end of the specified basic block.
272 MachineInstr::MachineInstr(MachineBasicBlock *MBB,
273 const TargetInstrDesc &tid)
274 : TID(&tid), NumImplicitOps(0), Parent(0) {
275 assert(MBB && "Cannot use inserting ctor with null basic block!");
276 if (TID->ImplicitDefs)
277 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
279 if (TID->ImplicitUses)
280 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
282 Operands.reserve(NumImplicitOps + TID->getNumOperands());
283 addImplicitDefUseOperands();
284 // Make sure that we get added to a machine basicblock
285 LeakDetector::addGarbageObject(this);
286 MBB->push_back(this); // Add instruction to end of basic block!
289 /// MachineInstr ctor - Copies MachineInstr arg exactly
291 MachineInstr::MachineInstr(const MachineInstr &MI) {
293 NumImplicitOps = MI.NumImplicitOps;
294 Operands.reserve(MI.getNumOperands());
297 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
298 Operands.push_back(MI.getOperand(i));
299 Operands.back().ParentMI = this;
302 // Set parent, next, and prev to null
309 MachineInstr::~MachineInstr() {
310 LeakDetector::removeGarbageObject(this);
312 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
313 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
314 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
315 "Reg operand def/use list corrupted");
320 /// getOpcode - Returns the opcode of this MachineInstr.
322 int MachineInstr::getOpcode() const {
326 /// getRegInfo - If this instruction is embedded into a MachineFunction,
327 /// return the MachineRegisterInfo object for the current function, otherwise
329 MachineRegisterInfo *MachineInstr::getRegInfo() {
330 if (MachineBasicBlock *MBB = getParent())
331 if (MachineFunction *MF = MBB->getParent())
332 return &MF->getRegInfo();
336 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
337 /// this instruction from their respective use lists. This requires that the
338 /// operands already be on their use lists.
339 void MachineInstr::RemoveRegOperandsFromUseLists() {
340 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
341 if (Operands[i].isReg())
342 Operands[i].RemoveRegOperandFromRegInfo();
346 /// AddRegOperandsToUseLists - Add all of the register operands in
347 /// this instruction from their respective use lists. This requires that the
348 /// operands not be on their use lists yet.
349 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
350 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
351 if (Operands[i].isReg())
352 Operands[i].AddRegOperandToRegInfo(&RegInfo);
357 /// addOperand - Add the specified operand to the instruction. If it is an
358 /// implicit operand, it is added to the end of the operand list. If it is
359 /// an explicit operand it is added at the end of the explicit operand list
360 /// (before the first implicit operand).
361 void MachineInstr::addOperand(const MachineOperand &Op) {
362 bool isImpReg = Op.isReg() && Op.isImplicit();
363 assert((isImpReg || !OperandsComplete()) &&
364 "Trying to add an operand to a machine instr that is already done!");
366 // If we are adding the operand to the end of the list, our job is simpler.
367 // This is true most of the time, so this is a reasonable optimization.
368 if (isImpReg || NumImplicitOps == 0) {
369 // We can only do this optimization if we know that the operand list won't
371 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
372 Operands.push_back(Op);
374 // Set the parent of the operand.
375 Operands.back().ParentMI = this;
377 // If the operand is a register, update the operand's use list.
379 Operands.back().AddRegOperandToRegInfo(getRegInfo());
384 // Otherwise, we have to insert a real operand before any implicit ones.
385 unsigned OpNo = Operands.size()-NumImplicitOps;
387 MachineRegisterInfo *RegInfo = getRegInfo();
389 // If this instruction isn't embedded into a function, then we don't need to
390 // update any operand lists.
392 // Simple insertion, no reginfo update needed for other register operands.
393 Operands.insert(Operands.begin()+OpNo, Op);
394 Operands[OpNo].ParentMI = this;
396 // Do explicitly set the reginfo for this operand though, to ensure the
397 // next/prev fields are properly nulled out.
398 if (Operands[OpNo].isReg())
399 Operands[OpNo].AddRegOperandToRegInfo(0);
401 } else if (Operands.size()+1 <= Operands.capacity()) {
402 // Otherwise, we have to remove register operands from their register use
403 // list, add the operand, then add the register operands back to their use
404 // list. This also must handle the case when the operand list reallocates
405 // to somewhere else.
407 // If insertion of this operand won't cause reallocation of the operand
408 // list, just remove the implicit operands, add the operand, then re-add all
409 // the rest of the operands.
410 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
411 assert(Operands[i].isReg() && "Should only be an implicit reg!");
412 Operands[i].RemoveRegOperandFromRegInfo();
415 // Add the operand. If it is a register, add it to the reg list.
416 Operands.insert(Operands.begin()+OpNo, Op);
417 Operands[OpNo].ParentMI = this;
419 if (Operands[OpNo].isReg())
420 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
422 // Re-add all the implicit ops.
423 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
424 assert(Operands[i].isReg() && "Should only be an implicit reg!");
425 Operands[i].AddRegOperandToRegInfo(RegInfo);
428 // Otherwise, we will be reallocating the operand list. Remove all reg
429 // operands from their list, then readd them after the operand list is
431 RemoveRegOperandsFromUseLists();
433 Operands.insert(Operands.begin()+OpNo, Op);
434 Operands[OpNo].ParentMI = this;
436 // Re-add all the operands.
437 AddRegOperandsToUseLists(*RegInfo);
441 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
442 /// fewer operand than it started with.
444 void MachineInstr::RemoveOperand(unsigned OpNo) {
445 assert(OpNo < Operands.size() && "Invalid operand number");
447 // Special case removing the last one.
448 if (OpNo == Operands.size()-1) {
449 // If needed, remove from the reg def/use list.
450 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
451 Operands.back().RemoveRegOperandFromRegInfo();
457 // Otherwise, we are removing an interior operand. If we have reginfo to
458 // update, remove all operands that will be shifted down from their reg lists,
459 // move everything down, then re-add them.
460 MachineRegisterInfo *RegInfo = getRegInfo();
462 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
463 if (Operands[i].isReg())
464 Operands[i].RemoveRegOperandFromRegInfo();
468 Operands.erase(Operands.begin()+OpNo);
471 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
472 if (Operands[i].isReg())
473 Operands[i].AddRegOperandToRegInfo(RegInfo);
479 /// removeFromParent - This method unlinks 'this' from the containing basic
480 /// block, and returns it, but does not delete it.
481 MachineInstr *MachineInstr::removeFromParent() {
482 assert(getParent() && "Not embedded in a basic block!");
483 getParent()->remove(this);
488 /// OperandComplete - Return true if it's illegal to add a new operand
490 bool MachineInstr::OperandsComplete() const {
491 unsigned short NumOperands = TID->getNumOperands();
492 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
493 return true; // Broken: we have all the operands of this instruction!
497 /// getNumExplicitOperands - Returns the number of non-implicit operands.
499 unsigned MachineInstr::getNumExplicitOperands() const {
500 unsigned NumOperands = TID->getNumOperands();
501 if (!TID->isVariadic())
504 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
505 const MachineOperand &MO = getOperand(NumOperands);
506 if (!MO.isRegister() || !MO.isImplicit())
513 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
515 bool MachineInstr::isDebugLabel() const {
516 return getOpcode() == TargetInstrInfo::LABEL && getOperand(1).getImm() == 0;
519 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
520 /// the specific register or -1 if it is not found. It further tightening
521 /// the search criteria to a use that kills the register if isKill is true.
522 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
523 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
524 const MachineOperand &MO = getOperand(i);
525 if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
526 if (!isKill || MO.isKill())
532 /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
533 /// the specific register or NULL if it is not found.
534 MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
535 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
536 MachineOperand &MO = getOperand(i);
537 if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
543 /// findFirstPredOperandIdx() - Find the index of the first operand in the
544 /// operand list that is used to represent the predicate. It returns -1 if
546 int MachineInstr::findFirstPredOperandIdx() const {
547 const TargetInstrDesc &TID = getDesc();
548 if (TID.isPredicable()) {
549 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
550 if (TID.OpInfo[i].isPredicate())
557 /// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
558 /// to two addr elimination.
559 bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
560 const TargetInstrDesc &TID = getDesc();
561 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
562 const MachineOperand &MO1 = getOperand(i);
563 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
564 for (unsigned j = i+1; j < e; ++j) {
565 const MachineOperand &MO2 = getOperand(j);
566 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
567 TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i)
575 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
577 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
578 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
579 const MachineOperand &MO = MI->getOperand(i);
580 if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
582 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
583 MachineOperand &MOp = getOperand(j);
584 if (!MOp.isIdenticalTo(MO))
595 /// copyPredicates - Copies predicate operand(s) from MI.
596 void MachineInstr::copyPredicates(const MachineInstr *MI) {
597 const TargetInstrDesc &TID = MI->getDesc();
598 if (TID.isPredicable()) {
599 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
600 if (TID.OpInfo[i].isPredicate()) {
601 // Predicated operands must be last operands.
602 addOperand(MI->getOperand(i));
608 void MachineInstr::dump() const {
609 cerr << " " << *this;
612 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
613 // Specialize printing if op#0 is definition
614 unsigned StartOp = 0;
615 if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
616 getOperand(0).print(OS, TM);
618 ++StartOp; // Don't print this operand again!
621 OS << getDesc().getName();
623 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
627 getOperand(i).print(OS, TM);
633 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
634 const MRegisterInfo *RegInfo,
635 bool AddIfNotFound) {
637 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
638 MachineOperand &MO = getOperand(i);
639 if (MO.isRegister() && MO.isUse()) {
640 unsigned Reg = MO.getReg();
643 if (Reg == IncomingReg) {
647 } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
648 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
649 RegInfo->isSuperRegister(IncomingReg, Reg) &&
651 // A super-register kill already exists.
656 // If not found, this means an alias of one of the operand is killed. Add a
657 // new implicit operand if required.
658 if (!Found && AddIfNotFound) {
659 addOperand(MachineOperand::CreateReg(IncomingReg, false/*IsDef*/,
660 true/*IsImp*/,true/*IsKill*/));
666 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
667 const MRegisterInfo *RegInfo,
668 bool AddIfNotFound) {
670 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
671 MachineOperand &MO = getOperand(i);
672 if (MO.isRegister() && MO.isDef()) {
673 unsigned Reg = MO.getReg();
676 if (Reg == IncomingReg) {
680 } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
681 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
682 RegInfo->isSuperRegister(IncomingReg, Reg) &&
684 // There exists a super-register that's marked dead.
689 // If not found, this means an alias of one of the operand is dead. Add a
690 // new implicit operand.
691 if (!Found && AddIfNotFound) {
692 addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/,
693 true/*IsImp*/,false/*IsKill*/,
700 /// copyKillDeadInfo - copies killed/dead information from one instr to another
701 void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI,
702 const MRegisterInfo *RegInfo) {
703 // If the instruction defines any virtual registers, update the VarInfo,
704 // kill and dead information for the instruction.
705 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
706 MachineOperand &MO = OldMI->getOperand(i);
707 if (MO.isRegister() && MO.getReg() &&
708 MRegisterInfo::isVirtualRegister(MO.getReg())) {
709 unsigned Reg = MO.getReg();
713 addRegisterDead(Reg, RegInfo);
718 addRegisterKilled(Reg, RegInfo);